Merge zizzer:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem --HG-- extra : convert_revision : 659f84c883b9992ae48f26c837983b9f8fcf18ab
This commit is contained in:
commit
27d60c27fa
7 changed files with 81 additions and 12 deletions
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@ -672,9 +672,9 @@ DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid)
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assert(cacheBlocked);
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cacheBlocked = false;
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retryTid = -1;
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retryPkt = NULL;
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delete retryPkt->req;
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delete retryPkt;
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retryPkt = NULL;
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}
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fetchStatus[tid] = Squashing;
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@ -71,6 +71,11 @@ template <class Impl>
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void
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LSQ<Impl>::DcachePort::recvRetry()
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{
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if (lsq->retryTid == -1)
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{
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//Squashed, so drop it
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return;
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}
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lsq->thread[lsq->retryTid].recvRetry();
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// Speculatively clear the retry Tid. This will get set again if
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// the LSQUnit was unable to complete its access.
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@ -646,6 +646,8 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
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// handle it.
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if (lsq->cacheBlocked()) {
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++lsqCacheBlocked;
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iewStage->decrWb(load_inst->seqNum);
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// There's an older load that's already going to squash.
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if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum)
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return NoFault;
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@ -626,6 +626,7 @@ LSQUnit<Impl>::writebackStores()
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++lsqCacheBlocked;
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assert(retryPkt == NULL);
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retryPkt = data_pkt;
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lsq->setRetryTid(lsqID);
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} else {
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storePostSend(data_pkt);
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}
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@ -869,6 +870,7 @@ LSQUnit<Impl>::recvRetry()
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storePostSend(retryPkt);
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retryPkt = NULL;
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isStoreBlocked = false;
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lsq->setRetryTid(-1);
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} else {
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// Still blocked!
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++lsqCacheBlocked;
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56
src/mem/cache/base_cache.cc
vendored
56
src/mem/cache/base_cache.cc
vendored
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@ -73,6 +73,7 @@ BaseCache::CachePort::recvTiming(Packet *pkt)
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{
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if (blocked)
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{
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DPRINTF(Cache,"Scheduling a retry while blocked\n");
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mustSendRetry = true;
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return false;
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}
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@ -91,21 +92,63 @@ BaseCache::CachePort::recvFunctional(Packet *pkt)
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cache->doFunctionalAccess(pkt, isCpuSide);
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}
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void
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BaseCache::CachePort::recvRetry()
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{
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Packet *pkt;
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if (!isCpuSide)
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{
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pkt = cache->getPacket();
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bool success = sendTiming(pkt);
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DPRINTF(Cache, "Address %x was %s in sending the timing request\n",
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pkt->getAddr(), success ? "succesful" : "unsuccesful");
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cache->sendResult(pkt, success);
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if (success && cache->doMasterRequest())
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{
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//Still more to issue, rerequest in 1 cycle
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pkt = NULL;
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BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this);
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reqCpu->schedule(curTick + 1);
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}
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}
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else
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{
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pkt = cache->getCoherencePacket();
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bool success = sendTiming(pkt);
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if (success && cache->doSlaveRequest())
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{
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//Still more to issue, rerequest in 1 cycle
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pkt = NULL;
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BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this);
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reqCpu->schedule(curTick + 1);
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}
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}
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return;
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}
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void
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BaseCache::CachePort::setBlocked()
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{
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assert(!blocked);
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DPRINTF(Cache, "Cache Blocking\n");
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blocked = true;
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//Clear the retry flag
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mustSendRetry = false;
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}
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void
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BaseCache::CachePort::clearBlocked()
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{
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assert(blocked);
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DPRINTF(Cache, "Cache Unblocking\n");
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blocked = false;
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if (mustSendRetry)
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{
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DPRINTF(Cache, "Cache Sending Retry\n");
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mustSendRetry = false;
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sendRetry();
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}
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blocked = false;
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}
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BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort)
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@ -128,6 +171,7 @@ BaseCache::CacheEvent::process()
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{
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if (!cachePort->isCpuSide)
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{
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//MSHR
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pkt = cachePort->cache->getPacket();
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bool success = cachePort->sendTiming(pkt);
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DPRINTF(Cache, "Address %x was %s in sending the timing request\n",
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@ -142,11 +186,19 @@ BaseCache::CacheEvent::process()
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}
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else
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{
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//CSHR
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pkt = cachePort->cache->getCoherencePacket();
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cachePort->sendTiming(pkt);
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bool success = cachePort->sendTiming(pkt);
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if (success && cachePort->cache->doSlaveRequest())
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{
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//Still more to issue, rerequest in 1 cycle
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pkt = NULL;
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this->schedule(curTick+1);
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}
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}
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return;
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}
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//Response
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//Know the packet to send, no need to mark in service (must succed)
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bool success = cachePort->sendTiming(pkt);
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assert(success);
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24
src/mem/cache/base_cache.hh
vendored
24
src/mem/cache/base_cache.hh
vendored
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@ -98,6 +98,8 @@ class BaseCache : public MemObject
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virtual int deviceBlockSize();
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virtual void recvRetry();
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public:
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void setBlocked();
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@ -407,17 +409,23 @@ class BaseCache : public MemObject
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void clearBlocked(BlockedCause cause)
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{
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uint8_t flag = 1 << cause;
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blocked &= ~flag;
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blockedSnoop &= ~flag;
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DPRINTF(Cache,"Unblocking for cause %s, causes left=%i\n",
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cause, blocked);
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if (!isBlocked()) {
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blocked_cycles[cause] += curTick - blockedCycle;
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DPRINTF(Cache,"Unblocking from all causes\n");
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cpuSidePort->clearBlocked();
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if (blocked & flag)
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{
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blocked &= ~flag;
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if (!isBlocked()) {
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blocked_cycles[cause] += curTick - blockedCycle;
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DPRINTF(Cache,"Unblocking from all causes\n");
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cpuSidePort->clearBlocked();
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}
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}
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if (!isBlockedForSnoop()) {
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memSidePort->clearBlocked();
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if (blockedSnoop & flag)
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{
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blockedSnoop &= ~flag;
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if (!isBlockedForSnoop()) {
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memSidePort->clearBlocked();
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}
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}
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}
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@ -217,7 +217,7 @@ class Packet
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bool isRequest() { return (cmd & IsRequest) != 0; }
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bool isResponse() { return (cmd & IsResponse) != 0; }
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bool needsResponse() { return (cmd & NeedsResponse) != 0; }
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bool isInvalidate() { return (cmd * IsInvalidate) != 0; }
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bool isInvalidate() { return (cmd & IsInvalidate) != 0; }
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bool isCacheFill() { return (flags & CACHE_LINE_FILL) != 0; }
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bool isNoAllocate() { return (flags & NO_ALLOCATE) != 0; }
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