gem5/src
Kevin Lim 8ade33d324 Support Ron's changes for hooking up ports.
src/cpu/checker/cpu.hh:
    Now that BaseCPU is a MemObject, the checker must define this function.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_unit.hh:
    Implement getPort function so the connector can connect the ports properly.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
    The connector handles connecting the ports now.
src/python/m5/objects/O3CPU.py:
    Add ports to the parameters.

--HG--
extra : convert_revision : 0b1a216b9a5d0574e62165d7c6c242498104d918
2006-07-07 17:33:24 -04:00
..
arch Various serialization changes to make it possible for the O3CPU to checkpoint. 2006-07-06 17:53:26 -04:00
base Fix up some merge problems. 2006-07-05 16:54:24 -04:00
cpu Support Ron's changes for hooking up ports. 2006-07-07 17:33:24 -04:00
dev Two minor FS compile fixes. 2006-07-06 16:26:44 -04:00
kern Merge zizzer.eecs.umich.edu:/bk/newmem 2006-06-17 18:28:21 -04:00
mem Fix address range calculation. Still need bus to handle snoop ranges. 2006-07-07 16:02:22 -04:00
python Support Ron's changes for hooking up ports. 2006-07-07 17:33:24 -04:00
sim Take the name of the checkpoint directory in when calling checkpoint() or restoreCheckpoint(). 2006-07-07 16:46:08 -04:00
unittest Merge iceaxe.:/Volumes/work/research/m5/head 2006-06-11 22:01:34 -04:00
Doxyfile New directory structure: 2006-05-22 14:29:33 -04:00
SConscript Remove sampler and serializer. Now they are handled through C++ interacting with Python. 2006-07-05 21:14:36 -04:00