Kevin Lim 8ade33d324 Support Ron's changes for hooking up ports. ... src/cpu/checker/cpu.hh: Now that BaseCPU is a MemObject, the checker must define this function. src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch.hh: src/cpu/o3/iew.hh: src/cpu/o3/lsq.hh: src/cpu/o3/lsq_unit.hh: Implement getPort function so the connector can connect the ports properly. src/cpu/o3/fetch_impl.hh: src/cpu/o3/lsq_unit_impl.hh: The connector handles connecting the ports now. src/python/m5/objects/O3CPU.py: Add ports to the parameters. --HG-- extra : convert_revision : 0b1a216b9a5d0574e62165d7c6c242498104d918		2006-07-07 17:33:24 -04:00
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m5	Support Ron's changes for hooking up ports.	2006-07-07 17:33:24 -04:00
SConscript	Rename SWIG "main" module to "cc_main" so it's	2006-06-17 12:08:19 -04:00