Commit graph

8207 commits

Author SHA1 Message Date
William Wang 16fcad3907 ARM: Cleanup and small fixes to some NEON ops to match the spec.
Only certain bits of the cpacr can be written, some must be equal.
Mult instructions that write the same register should do something sane
2011-04-04 11:42:28 -05:00
Ali Saidi a679cd917a ARM: Cleanup implementation of ITSTATE and put important code in PCState.
Consolidate all code to handle ITSTATE in the PCState object rather than
touching a variety of structures/objects.
2011-04-04 11:42:28 -05:00
Ali Saidi ac650199ee ARM: Fix m5op parameters bug.
All the m5op parameters are 64 bits, but we were only sending 32 bits;
and the static register indexes were incorrectly specified.
2011-04-04 11:42:28 -05:00
Ali Saidi be096f91b9 ARM: Tag appropriate instructions as IsReturn 2011-04-04 11:42:27 -05:00
Ali Saidi 55920a5ca7 ARM: Fix table walk going on while ASID changes error 2011-04-04 11:42:27 -05:00
Ali Saidi 5962fecc1d CPU: Remove references to memory copy operations 2011-04-04 11:42:26 -05:00
Ali Saidi 1114be4b78 O3: Update stats for memory order violation checking patch. 2011-04-04 11:42:25 -05:00
Ali Saidi 7dde557fdc O3: Tighten memory order violation checking to 16 bytes.
The comment in the code suggests that the checking granularity should be 16
bytes, however in reality the shift by 8 is 256 bytes which seems much
larger than required.
2011-04-04 11:42:23 -05:00
Ali Saidi ee489a541a IDE: Support x86, Alpha, and ARM use of the IDE controller. 2011-04-04 11:42:23 -05:00
Ali Saidi c56eb8fb3c ARM: Fix checkpointing case where PL111 is powered off. 2011-04-04 11:42:23 -05:00
Ali Saidi 6fd271ffb3 ARM: Remove debugging warn that was accidently left in. 2011-04-04 11:42:23 -05:00
Ali Saidi dfdabbd751 ARM: Fix multiplication error in udelay 2011-04-04 11:42:23 -05:00
Brad Beckmann 0788ea7b3b hammer: fixed dma uniproc error
Fixed an error reguarding DMA for uninprocessor systems.  Basically removed an
overly agressive optimization that lead to inconsistent state between the
cache and the directory.
2011-04-01 15:50:23 -07:00
Lisa Hsu 01fc529bb2 CacheMemory: add allocateVoid() that is == allocate() but no return value.
This function duplicates the functionality of allocate() exactly, except that it does not return
a return value.  In protocols where you just want to allocate a block
but do not want that block to be your implicitly passed cache_entry, use this function.
Otherwise, SLICC will complain if you do not consume the pointer returned by allocate(),
and if you do a dummy assignment Entry foo := cache.allocate(address), the C++
compiler will complain of an unused variable.  This is kind of a hack to get around
those issues, but suggestions welcome.
2011-03-31 18:20:12 -07:00
Lisa Hsu d857105b5a Ruby: Simplify SLICC and Entry/TBE handling.
Before this changeset, all local variables of type Entry and TBE were considered
to be pointers, but an immediate use of said variables would not be automatically
deferenced in SLICC-generated code.  Instead, deferences occurred when such
variables were passed to functions, and were automatically dereferenced in
the bodies of the functions (e.g. the implicitly passed cache_entry).

This is a more general way to do it, which leaves in place the
assumption that parameters to functions and local variables of type AbstractCacheEntry
and TBE are always pointers, but instead of dereferencing to access member variables
on a contextual basis, the dereferencing automatically occurs on a type basis at the
moment a member is being accessed.  So, now, things you can do that you couldn't before
include:

Entry foo := getCacheEntry(address);
cache_entry.DataBlk := foo.DataBlk;

or

cache_entry.DataBlk := getCacheEntry(address).DataBlk;

or even

cache_entry.DataBlk := static_cast(Entry, pointer, cache.lookup(address)).DataBlk;
2011-03-31 17:18:00 -07:00
Lisa Hsu 322b9ca2c5 Ruby: Add new object called WireBuffer to mimic a Wire.
This is a substitute for MessageBuffers between controllers where you don't
want messages to actually go through the Network, because requests/responses can
always get reordered wrt to one another (even if you turn off Randomization and turn on Ordered)
because you are, after all, going through a network with contention. For systems where you model
multiple controllers that are very tightly coupled and do not actually go through a network,
it is a pain to have to write a coherence protocol to account for mixed up request/response orderings
despite the fact that it's completely unrealistic.  This is *not* meant as a substitute for real
MessageBuffers when messages do in fact go over a network.
2011-03-31 17:17:57 -07:00
Lisa Hsu 06fcaf9104 Ruby: have the rubytester pass contextId to Ruby. 2011-03-31 17:17:51 -07:00
Lisa Hsu c9621cc69b Ruby: enable multiple sequencers in one controller. 2011-03-31 17:17:49 -07:00
Lisa Hsu 225e67f531 Ruby: pass Packet->Req->contextId() to Ruby.
It is useful for Ruby to understand from whence request packets came.
This has all request packets going into Ruby pass the contextId value, if
it exists.  This supplants the old libruby proc_id value passed around in
all the Messages, so I've also removed the unused unsigned proc_id; member
generated by SLICC for all Message types.
2011-03-31 17:17:47 -07:00
Lisa Hsu f6a0b63d7b Ruby: Bug in SLICC forgot semicolon at end of code. 2011-03-31 12:20:16 -07:00
Korey Sewell 473bc21977 sim: typecast Tick to UTick for eventQ assert 2011-03-29 19:36:36 -04:00
Gabe Black ccc8ba2033 Power: Fix compilation. 2011-03-29 13:04:19 -04:00
Somayeh Sardashti c8bbfed937 This patch supports cache flushing in MOESI_hammer 2011-03-28 10:49:45 -05:00
Nilay Vaish ef987a4064 Config: Import math in MI_example.py 2011-03-28 10:49:36 -05:00
Steve Reinhardt bb67c706d6 tests: update reference outputs for ruby cache index change
MOESI_CMP_token is the only protocol that showed noticeable stats
differences.
2011-03-26 22:24:36 -07:00
Korey Sewell e0fdd86fd9 mips: cleanup ISA-specific code
***
(1): get rid of expandForMT function
MIPS is the only ISA that cares about having a piece of ISA state integrate
multiple threads so add constants for MIPS and relieve the other ISAs from having
to define this. Also, InOrder was the only core that was actively calling
this function
* * *
(2): get rid of corespecific type
The CoreSpecific type was used as a proxy to pass in HW specific params to
a MIPS CPU, but since MIPS FS hasnt been touched for awhile, it makes sense
to not force every other ISA to use CoreSpecific as well use a special
reset function to set it. That probably should go in a PowerOn reset fault
 anyway.
2011-03-26 09:23:52 -04:00
Brad Beckmann 48b58b3332 ruby: fixed cache index setting 2011-03-25 10:13:50 -07:00
Gabe Black 6db65b40c1 Arm: Add in a missing miscRegName. 2011-03-25 00:46:14 -04:00
Gabe Black 475685df49 Arm: Get rid of unused and incomplete setCp15Register and readCp15Register. 2011-03-24 14:39:00 -04:00
Gabe Black 5d09a78dce Arm: Get rid of the unused copyStringArray32 method from Arm process classes. 2011-03-24 14:00:15 -04:00
Gabe Black 57ed5e77fe ISA parser: Set up op_src_decl and op_dest_decl for pc operands. 2011-03-24 13:55:16 -04:00
Tushar Krishna 531f54fb51 This patch fixes a build error in networktest.cc that occurs with gcc4.2 2011-03-22 23:38:09 -04:00
Nilay Vaish 1764ebbf30 Ruby: Remove CacheMsg class from SLICC
The goal of the patch is to do away with the CacheMsg class currently in use
in coherence protocols. In place of CacheMsg, the RubyRequest class will used.
This class is already present in slicc_interface/RubyRequest.hh. In fact,
objects of class CacheMsg are generated by copying values from a RubyRequest
object.
2011-03-22 06:41:54 -05:00
Tushar Krishna 46cce440be This patch makes garnet use the info about active and inactive vnets during allocation and power estimations etc 2011-03-21 22:51:59 -04:00
Tushar Krishna 1b9002eefc fix garnet fleible pipeline 2011-03-21 22:51:59 -04:00
Tushar Krishna 09c3a97a4c This patch adds the network tester for simple and garnet networks.
The tester code is in testers/networktest.
The tester can be invoked by configs/example/ruby_network_test.py.
A dummy coherence protocol called Network_test is also addded for network-only simulations and testing. The protocol takes in messages from the tester and just pushes them into the network in the appropriate vnet, without storing any state.
2011-03-21 22:51:58 -04:00
Nilay Vaish d7aa794155 SLICC: Remove WakeUp* import calls from ast/__init__.py
I had recently committed a patch that removed the WakeUp*.py files from the
slicc/ast directory. I had forgotten to remove the import  calls for these
files from slicc/ast/__init__.py. This resulted in error while running
regressions on zizzer. This patch does the needful.
2011-03-20 09:23:27 -05:00
Lisa Hsu 8957b09da1 configs: combine ruby_se.py and se.py to avoid all that code duplication 2011-03-19 21:13:04 -07:00
Lisa Hsu 0e75e3fd5f enable x86 workloads on se.py 2011-03-19 21:13:02 -07:00
Lisa Hsu 5103c6fe88 se.py: Modify script to make multiprogramming much easier.
Now, instead of --bench benchname, you can do --bench bench1-bench2-bench3 and it will
set up a simulation that instantiates those three workloads.  Only caveat is that now,
for sanity checking, your -n X must match the number of benches in the list.
2011-03-19 21:12:59 -07:00
Lisa Hsu 83664630ee util: update aggregator to handle x86 checkpoints.
Also, make update to understand some of the newer serialized variables
2011-03-19 21:12:55 -07:00
Nilay Vaish 611f052e96 Ruby: Convert CacheRequestType to RubyRequestType
This patch converts CacheRequestType to RubyRequestType so that both the
protocol dependent and independent code makes use of the same request type.
2011-03-19 18:34:59 -05:00
Nilay Vaish 2f4276448b Ruby: Convert AccessModeType to RubyAccessMode
This patch converts AccessModeType to RubyAccessMode so that both the
protocol dependent and independent code uses the same access mode.
2011-03-19 18:34:37 -05:00
Brad Beckmann dd9083115e MOESI_hammer: minor fixes to full-bit dir 2011-03-19 14:17:48 -07:00
Brad Beckmann 541fa1091a Ruby: dma retry fix
This patch fixes the problem where Ruby would fail to call sendRetry on ports
after it nacked the port.  This patch is particularly helpful for bursty dma
requests which often include several packets.
2011-03-19 14:17:48 -07:00
Brad Beckmann d1cecc2241 RubyPort: minor fixes to trace flag and dprintfs 2011-03-19 14:17:48 -07:00
Brad Beckmann 8e61805a21 ruby: added useful dma progress dprintf 2011-03-19 14:17:48 -07:00
Brad Beckmann 08d73529bc slicc: improved invalid transition message 2011-03-19 14:17:48 -07:00
Brad Beckmann 31d0a421a9 MOESI_hammer: fixed dma bug with shared data 2011-03-19 14:17:48 -07:00
Brad Beckmann a2e98f191f MOESI_CMP_directory: significant dma bug fixes 2011-03-19 14:17:48 -07:00