sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

ruby: fixed cache index setting

Browse source
This commit is contained in:
Brad Beckmann 2011-03-25 10:13:50 -07:00
parent 6db65b40c1
commit 48b58b3332
5 changed files with 41 additions and 22 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

17
configs/ruby/MESI_CMP_directory.py
View file

@ -68,15 +68,19 @@ def create_system(options, system, piobus, dma_devices):
# Must create the individual controllers before the network to ensure the
# controller constructors are called before the network constructor
#
l2_bits = int(math.log(options.num_l2caches, 2))
block_size_bits = int(math.log(options.cacheline_size, 2))
for i in xrange(options.num_cpus):
#
# First create the Ruby objects associated with this cpu
#
l1i_cache = L1Cache(size = options.l1i_size,
assoc = options.l1i_assoc)
assoc = options.l1i_assoc,
start_index_bit = block_size_bits)
l1d_cache = L1Cache(size = options.l1d_size,
assoc = options.l1d_assoc)
assoc = options.l1d_assoc,
start_index_bit = block_size_bits)
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
@ -91,9 +95,7 @@ def create_system(options, system, piobus, dma_devices):
sequencer = cpu_seq,
L1IcacheMemory = l1i_cache,
L1DcacheMemory = l1d_cache,
l2_select_num_bits = \
math.log(options.num_l2caches,
2))
l2_select_num_bits = l2_bits)
exec("system.l1_cntrl%d = l1_cntrl" % i)
@ -103,12 +105,15 @@ def create_system(options, system, piobus, dma_devices):
cpu_sequencers.append(cpu_seq)
l1_cntrl_nodes.append(l1_cntrl)
l2_index_start = block_size_bits + l2_bits
for i in xrange(options.num_l2caches):
#
# First create the Ruby objects associated with this cpu
#
l2_cache = L2Cache(size = options.l2_size,
assoc = options.l2_assoc)
assoc = options.l2_assoc,
start_index_bit = l2_index_start)
l2_cntrl = L2Cache_Controller(version = i,
L2cacheMemory = l2_cache)

4
configs/ruby/MI_example.py
View file

@ -60,6 +60,7 @@ def create_system(options, system, piobus, dma_devices):
# Must create the individual controllers before the network to ensure the
# controller constructors are called before the network constructor
#
block_size_bits = int(math.log(options.cacheline_size, 2))
for i in xrange(options.num_cpus):
#
@ -68,7 +69,8 @@ def create_system(options, system, piobus, dma_devices):
# config parameters.
#
cache = Cache(size = options.l1d_size,
assoc = options.l1d_assoc)
assoc = options.l1d_assoc,
start_index_bit = block_size_bits)
#
# Only one unified L1 cache exists. Can cache instructions and data.

17
configs/ruby/MOESI_CMP_directory.py
View file

@ -68,15 +68,19 @@ def create_system(options, system, piobus, dma_devices):
# Must create the individual controllers before the network to ensure the
# controller constructors are called before the network constructor
#
l2_bits = int(math.log(options.num_l2caches, 2))
block_size_bits = int(math.log(options.cacheline_size, 2))
for i in xrange(options.num_cpus):
#
# First create the Ruby objects associated with this cpu
#
l1i_cache = L1Cache(size = options.l1i_size,
assoc = options.l1i_assoc)
assoc = options.l1i_assoc,
start_index_bit = block_size_bits)
l1d_cache = L1Cache(size = options.l1d_size,
assoc = options.l1d_assoc)
assoc = options.l1d_assoc,
start_index_bit = block_size_bits)
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
@ -91,9 +95,7 @@ def create_system(options, system, piobus, dma_devices):
sequencer = cpu_seq,
L1IcacheMemory = l1i_cache,
L1DcacheMemory = l1d_cache,
l2_select_num_bits = \
math.log(options.num_l2caches,
2))
l2_select_num_bits = l2_bits)
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
@ -102,12 +104,15 @@ def create_system(options, system, piobus, dma_devices):
cpu_sequencers.append(cpu_seq)
l1_cntrl_nodes.append(l1_cntrl)
l2_index_start = block_size_bits + l2_bits
for i in xrange(options.num_l2caches):
#
# First create the Ruby objects associated with this cpu
#
l2_cache = L2Cache(size = options.l2_size,
assoc = options.l2_assoc)
assoc = options.l2_assoc,
start_index_bit = l2_index_start)
l2_cntrl = L2Cache_Controller(version = i,
L2cacheMemory = l2_cache)

15
configs/ruby/MOESI_CMP_token.py
View file

@ -82,15 +82,18 @@ def create_system(options, system, piobus, dma_devices):
# controller constructors are called before the network constructor
#
l2_bits = int(math.log(options.num_l2caches, 2))
block_size_bits = int(math.log(options.cacheline_size, 2))
for i in xrange(options.num_cpus):
#
# First create the Ruby objects associated with this cpu
#
l1i_cache = L1Cache(size = options.l1i_size,
assoc = options.l1i_assoc)
assoc = options.l1i_assoc,
start_index_bit = block_size_bits)
l1d_cache = L1Cache(size = options.l1d_size,
assoc = options.l1d_assoc)
assoc = options.l1d_assoc,
start_index_bit = block_size_bits)
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
@ -123,13 +126,15 @@ def create_system(options, system, piobus, dma_devices):
cpu_sequencers.append(cpu_seq)
l1_cntrl_nodes.append(l1_cntrl)
l2_index_start = block_size_bits + l2_bits
for i in xrange(options.num_l2caches):
#
# First create the Ruby objects associated with this cpu
#
l2_cache = L2Cache(size = options.l2_size,
assoc = options.l2_assoc,
start_index_bit = l2_bits)
start_index_bit = l2_index_start)
l2_cntrl = L2Cache_Controller(version = i,
L2cacheMemory = l2_cache,
@ -158,9 +163,7 @@ def create_system(options, system, piobus, dma_devices):
size = \
dir_size),
memBuffer = mem_cntrl,
l2_select_num_bits = \
math.log(options.num_l2caches,
2))
l2_select_num_bits = l2_bits)
exec("system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)

10
configs/ruby/MOESI_hammer.py
View file

@ -78,17 +78,21 @@ def create_system(options, system, piobus, dma_devices):
# Must create the individual controllers before the network to ensure the
# controller constructors are called before the network constructor
#
block_size_bits = int(math.log(options.cacheline_size, 2))
for i in xrange(options.num_cpus):
#
# First create the Ruby objects associated with this cpu
#
l1i_cache = L1Cache(size = options.l1i_size,
assoc = options.l1i_assoc)
assoc = options.l1i_assoc,
start_index_bit = block_size_bits)
l1d_cache = L1Cache(size = options.l1d_size,
assoc = options.l1d_assoc)
assoc = options.l1d_assoc,
start_index_bit = block_size_bits)
l2_cache = L2Cache(size = options.l2_size,
assoc = options.l2_assoc)
assoc = options.l2_assoc,
start_index_bit = block_size_bits)
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,