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gem5/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt

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More regression updates. Get rid of caches in simple-timing config for now. tests/SConscript: another line for diff to ignore tests/configs/simple-timing.py: turn off caches for now tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt: tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout: tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt: tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout: update for inst/tick rate (old one was debug?) tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout: works now (no caches) --HG-- extra : convert_revision : 472030f63297346976db6274a78235c93d4eef8e
2006-08-17 00:48:15 +02:00
---------- Begin Simulation Statistics ----------
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
sim_seconds 0.000031 # Number of seconds simulated
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
sim_ticks 30902500 # Number of ticks simulated
final_tick 30902500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
MIPS: Update MIPS stats for cleaned up operand checks.
2011-09-09 10:35:05 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
host_inst_rate 544856 # Simulator instruction rate (inst/s)
host_op_rate 544118 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2985748792 # Simulator tick rate (ticks/s)
host_mem_usage 288768 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
sim_insts 5624 # Number of instructions simulated
sim_ops 5624 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.physmem.bytes_read::cpu.inst 18752 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8768 # Number of bytes read from this memory
system.physmem.bytes_read::total 27520 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 18752 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 18752 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 293 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory
system.physmem.num_reads::total 430 # Number of read requests responded to by this memory
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.bw_read::cpu.inst 606811747 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 283731090 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 890542836 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 606811747 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 606811747 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 606811747 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 283731090 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 890542836 # Total bandwidth to/from this memory (bytes/s)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
Bus: Update the stats for the recent bus fix. --HG-- extra : convert_revision : dc29f7b5e6fa30a50305193cb0e5aed942f7e407
2008-02-26 08:20:40 +01:00
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
MIPS: Update MIPS stats for cleaned up operand checks.
2011-09-09 10:35:05 +02:00
system.cpu.dtb.read_accesses 0 # DTB read accesses
Bus: Update the stats for the recent bus fix. --HG-- extra : convert_revision : dc29f7b5e6fa30a50305193cb0e5aed942f7e407
2008-02-26 08:20:40 +01:00
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
MIPS: Update MIPS stats for cleaned up operand checks.
2011-09-09 10:35:05 +02:00
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.workload.num_syscalls 7 # Number of system calls
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.numCycles 61805 # number of cpu cycles simulated
MIPS: Update MIPS stats for cleaned up operand checks.
2011-09-09 10:35:05 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.committedInsts 5624 # Number of instructions committed
system.cpu.committedOps 5624 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4944 # Number of integer alu accesses
MIPS: Update MIPS stats for cleaned up operand checks.
2011-09-09 10:35:05 +02:00
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.num_func_calls 190 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 649 # number of instructions that are conditional controls
system.cpu.num_int_insts 4944 # number of integer instructions
MIPS: Update MIPS stats for cleaned up operand checks.
2011-09-09 10:35:05 +02:00
system.cpu.num_fp_insts 2 # number of float instructions
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.num_int_register_reads 7054 # number of times the integer registers were read
system.cpu.num_int_register_writes 3281 # number of times the integer registers were written
MIPS: Update MIPS stats for cleaned up operand checks.
2011-09-09 10:35:05 +02:00
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.num_mem_refs 2034 # number of memory refs
system.cpu.num_load_insts 1132 # Number of load instructions
system.cpu.num_store_insts 902 # Number of store instructions
MIPS: Update MIPS stats for cleaned up operand checks.
2011-09-09 10:35:05 +02:00
system.cpu.num_idle_cycles 0 # Number of idle cycles
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.num_busy_cycles 61805 # Number of busy cycles
MIPS: Update MIPS stats for cleaned up operand checks.
2011-09-09 10:35:05 +02:00
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.Branches 883 # Number of branches fetched
system.cpu.op_class::No_OpClass 637 11.32% 11.32% # Class of executed instruction
system.cpu.op_class::IntAlu 2950 52.44% 63.77% # Class of executed instruction
system.cpu.op_class::IntMult 2 0.04% 63.80% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 63.80% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.04% 63.84% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::MemRead 1132 20.12% 83.96% # Class of executed instruction
system.cpu.op_class::MemWrite 902 16.04% 100.00% # Class of executed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.op_class::total 5625 # Class of executed instruction
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 86.155054 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 13.839416 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 86.155054 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.021034 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.021034 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 1045 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1045 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits
system.cpu.dcache.overall_hits::total 1896 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 50 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 137 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses
system.cpu.dcache.overall_misses::total 137 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4785000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 4785000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2750000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 2750000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 7535000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 7535000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 7535000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 7535000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076855 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.076855 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.067388 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.067388 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.067388 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.067388 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4654500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4654500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2675000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2675000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7329500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7329500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7329500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7329500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.replacements 13 # number of replacements
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.tags.tagsinuse 129.101534 # Cycle average of tags in use
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.icache.tags.total_refs 5331 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 18.071186 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 129.101534 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.063038 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.063038 # Average percentage of cache occupancy
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.icache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.137695 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 11547 # Number of tag accesses
system.cpu.icache.tags.data_accesses 11547 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 5331 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 5331 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 5331 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 5331 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 5331 # number of overall hits
system.cpu.icache.overall_hits::total 5331 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 295 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 295 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 295 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 295 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 295 # number of overall misses
system.cpu.icache.overall_misses::total 295 # number of overall misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.ReadReq_miss_latency::cpu.inst 16141500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 16141500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 16141500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 16141500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 16141500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 16141500 # number of overall miss cycles
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.icache.ReadReq_accesses::cpu.inst 5626 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 5626 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 5626 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 5626 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 5626 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 5626 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052435 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.052435 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.052435 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.052435 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.052435 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.052435 # miss rate for overall accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54716.949153 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 54716.949153 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54716.949153 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 54716.949153 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54716.949153 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 54716.949153 # average overall miss latency
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
MIPS: Update MIPS stats for cleaned up operand checks.
2011-09-09 10:35:05 +02:00
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
MIPS: Update MIPS stats for cleaned up operand checks.
2011-09-09 10:35:05 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
Update reference outputs --HG-- extra : convert_revision : 110a6c51cc1c562d115492b7360bfdbbded8eefd
2006-08-18 06:17:21 +02:00
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 295 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 295 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 295 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 295 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 295 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 295 # number of overall MSHR misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15699000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 15699000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15699000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 15699000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15699000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 15699000 # number of overall MSHR miss cycles
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052435 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.052435 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.052435 # mshr miss rate for overall accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53216.949153 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53216.949153 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53216.949153 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 53216.949153 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53216.949153 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53216.949153 # average overall mshr miss latency
MIPS: Update MIPS stats for cleaned up operand checks.
2011-09-09 10:35:05 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.replacements 0 # number of replacements
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.tags.tagsinuse 183.714965 # Cycle average of tags in use
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.005263 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.257719 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 53.457246 # Average occupied blocks per requestor
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003975 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001631 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.005607 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011597 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 3886 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 3886 # Number of data accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.inst 293 # number of ReadReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.l2cache.ReadReq_misses::total 380 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 50 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 293 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 137 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 430 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 293 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 137 # number of overall misses
system.cpu.l2cache.overall_misses::total 430 # number of overall misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15383000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4567500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 19950500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2625000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 2625000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 15383000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 7192500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 22575500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 15383000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 7192500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 22575500 # number of overall miss cycles
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.l2cache.ReadReq_accesses::cpu.inst 295 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses)
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.l2cache.ReadReq_accesses::total 382 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 295 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 137 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 432 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 295 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 137 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 432 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993220 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.l2cache.ReadReq_miss_rate::total 0.994764 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993220 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.l2cache.demand_miss_rate::total 0.995370 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993220 # miss rate for overall accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.l2cache.overall_miss_rate::total 0.995370 # miss rate for overall accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.706485 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.315789 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.706485 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52501.162791 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.706485 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52501.162791 # average overall miss latency
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
MIPS: Update MIPS stats for cleaned up operand checks.
2011-09-09 10:35:05 +02:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
MIPS: Update MIPS stats for cleaned up operand checks.
2011-09-09 10:35:05 +02:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
Update reference outputs --HG-- extra : convert_revision : 110a6c51cc1c562d115492b7360bfdbbded8eefd
2006-08-18 06:17:21 +02:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 293 # number of ReadReq MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::total 380 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11866500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3523500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15390000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2025000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2025000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11866500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5548500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 17415000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11866500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5548500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 17415000 # number of overall MSHR miss cycles
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994764 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::total 0.995370 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for overall accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995370 # mshr miss rate for overall accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
MIPS: Update MIPS stats for cleaned up operand checks.
2011-09-09 10:35:05 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.toL2Bus.trans_dist::ReadReq 382 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 590 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 864 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 27648 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.toL2Bus.snoop_fanout::samples 432 # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.toL2Bus.snoop_fanout::1 432 100.00% 100.00% # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.toL2Bus.snoop_fanout::total 432 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 216000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 442500 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%)
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 205500 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.trans_dist::ReadReq 380 # Transaction distribution
system.membus.trans_dist::ReadResp 380 # Transaction distribution
system.membus.trans_dist::ReadExReq 50 # Transaction distribution
system.membus.trans_dist::ReadExResp 50 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 860 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27520 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 430 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 430 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 430 # Request fanout histogram
system.membus.reqLayer0.occupancy 430500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
system.membus.respLayer1.occupancy 2150500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 7.0 # Layer utilization (%)
More regression updates. Get rid of caches in simple-timing config for now. tests/SConscript: another line for diff to ignore tests/configs/simple-timing.py: turn off caches for now tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt: tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout: tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt: tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout: update for inst/tick rate (old one was debug?) tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout: works now (no caches) --HG-- extra : convert_revision : 472030f63297346976db6274a78235c93d4eef8e
2006-08-17 00:48:15 +02:00
---------- End Simulation Statistics ----------
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