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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt

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arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
---------- Begin Simulation Statistics ----------
stats: update references
2016-07-21 18:19:18 +02:00
sim_seconds 51.316261 # Number of seconds simulated
sim_ticks 51316261201000 # Number of ticks simulated
final_tick 51316261201000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: update references
2016-08-02 12:34:32 +02:00
host_inst_rate 303672 # Simulator instruction rate (inst/s)
host_op_rate 356843 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 18193830206 # Simulator tick rate (ticks/s)
host_mem_usage 686184 # Number of bytes of host memory used
host_seconds 2820.53 # Real time elapsed on the host
stats: update references
2016-07-21 18:19:18 +02:00
sim_insts 856517636 # Number of instructions simulated
sim_ops 1006486660 # Number of ops (including micro ops) simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: update references
2016-07-21 18:19:18 +02:00
system.physmem.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker 89408 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 88064 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 2284980 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 19216392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 19648 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 18624 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 651264 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 5282880 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker 33920 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.itb.walker 30784 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 1695808 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 7120960 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.dtb.walker 74240 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.itb.walker 63168 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst 1609856 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data 11459776 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 417920 # Number of bytes read from this memory
system.physmem.bytes_read::total 50157692 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 2284980 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 651264 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 1695808 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst 1609856 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 6241908 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 69878272 # Number of bytes written to this memory
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
stats: update references
2016-07-21 18:19:18 +02:00
system.physmem.bytes_written::total 69898852 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 1397 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1376 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 76110 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 300269 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 307 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 291 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 10176 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 82545 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker 530 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.itb.walker 481 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 26497 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 111265 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.dtb.walker 1160 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.itb.walker 987 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst 25154 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 179059 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6530 # Number of read requests responded to by this memory
system.physmem.num_reads::total 824134 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1091848 # Number of write requests responded to by this memory
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
stats: update references
2016-07-21 18:19:18 +02:00
system.physmem.num_writes::total 1094421 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 1742 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 1716 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 44527 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 374470 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 383 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 363 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 12691 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 102947 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker 661 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.itb.walker 600 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 33046 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 138766 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.dtb.walker 1447 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.itb.walker 1231 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst 31371 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data 223317 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 8144 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 977423 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 44527 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 12691 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 33046 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst 31371 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 121636 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1361718 # Write bandwidth from this memory (bytes/s)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s)
stats: update references
2016-07-21 18:19:18 +02:00
system.physmem.bw_write::total 1362119 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1361718 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 1742 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 1716 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 44527 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 374871 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 383 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 363 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 12691 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 102947 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker 661 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.itb.walker 600 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 33046 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 138766 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.dtb.walker 1447 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.itb.walker 1231 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst 31371 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data 223317 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 8144 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2339542 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 438929 # Number of read requests accepted
system.physmem.writeReqs 487711 # Number of write requests accepted
system.physmem.readBursts 438929 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 487711 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 28073280 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 18176 # Total number of bytes read from write queue
system.physmem.bytesWritten 31211968 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 28091456 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 31213504 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 284 # Number of DRAM read bursts serviced by the write queue
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
stats: update references
2016-07-21 18:19:18 +02:00
system.physmem.perBankRdBursts::0 25285 # Per bank write bursts
system.physmem.perBankRdBursts::1 29259 # Per bank write bursts
system.physmem.perBankRdBursts::2 26350 # Per bank write bursts
system.physmem.perBankRdBursts::3 25668 # Per bank write bursts
system.physmem.perBankRdBursts::4 27357 # Per bank write bursts
system.physmem.perBankRdBursts::5 30719 # Per bank write bursts
system.physmem.perBankRdBursts::6 26473 # Per bank write bursts
system.physmem.perBankRdBursts::7 28031 # Per bank write bursts
system.physmem.perBankRdBursts::8 25079 # Per bank write bursts
system.physmem.perBankRdBursts::9 30131 # Per bank write bursts
system.physmem.perBankRdBursts::10 27758 # Per bank write bursts
system.physmem.perBankRdBursts::11 30805 # Per bank write bursts
system.physmem.perBankRdBursts::12 27043 # Per bank write bursts
system.physmem.perBankRdBursts::13 27394 # Per bank write bursts
system.physmem.perBankRdBursts::14 24672 # Per bank write bursts
system.physmem.perBankRdBursts::15 26621 # Per bank write bursts
system.physmem.perBankWrBursts::0 26756 # Per bank write bursts
system.physmem.perBankWrBursts::1 29816 # Per bank write bursts
system.physmem.perBankWrBursts::2 28574 # Per bank write bursts
system.physmem.perBankWrBursts::3 30074 # Per bank write bursts
system.physmem.perBankWrBursts::4 31364 # Per bank write bursts
system.physmem.perBankWrBursts::5 33348 # Per bank write bursts
system.physmem.perBankWrBursts::6 29983 # Per bank write bursts
system.physmem.perBankWrBursts::7 32184 # Per bank write bursts
system.physmem.perBankWrBursts::8 30191 # Per bank write bursts
system.physmem.perBankWrBursts::9 34064 # Per bank write bursts
system.physmem.perBankWrBursts::10 29741 # Per bank write bursts
system.physmem.perBankWrBursts::11 31916 # Per bank write bursts
system.physmem.perBankWrBursts::12 29919 # Per bank write bursts
system.physmem.perBankWrBursts::13 30461 # Per bank write bursts
system.physmem.perBankWrBursts::14 29114 # Per bank write bursts
system.physmem.perBankWrBursts::15 30182 # Per bank write bursts
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: update references
2016-07-21 18:19:18 +02:00
system.physmem.numWrRetry 9 # Number of times write queue was full causing retry
system.physmem.totGap 51315260920500 # Total gap between requests
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: update references
2016-07-21 18:19:18 +02:00
system.physmem.readPktSize::6 438929 # Read request sizes (log2)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: update references
2016-07-21 18:19:18 +02:00
system.physmem.writePktSize::6 487711 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 342866 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 67593 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 19478 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 8245 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 94 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 44 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 61 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 41 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 89 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 20 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 30 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 13 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 14 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 9 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 9 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 9 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 9 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.physmem.wrQLenPdf::0 578 # What write queue length does an incoming req see
stats: update references
2016-07-21 18:19:18 +02:00
system.physmem.wrQLenPdf::1 575 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 569 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 568 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 563 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 564 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 560 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 555 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 556 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 554 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 551 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 549 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 549 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 544 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 543 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 10806 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 12800 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 21548 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 23833 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 26317 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 27236 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 28042 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 28569 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 29592 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 29655 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 30940 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 31802 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 30047 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 29665 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 30409 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 27749 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 27223 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 26642 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 679 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 528 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 429 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 404 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 269 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 245 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 277 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 218 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 278 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 215 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 238 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 204 # What write queue length does an incoming req see
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.physmem.wrQLenPdf::45 176 # What write queue length does an incoming req see
stats: update references
2016-07-21 18:19:18 +02:00
system.physmem.wrQLenPdf::46 211 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 222 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 193 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 206 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 189 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 190 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 178 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 177 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 115 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 107 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 116 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 102 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 75 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 72 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 74 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 18 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 279155 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 212.371879 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 133.666378 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 251.561006 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 134237 48.09% 48.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 73368 26.28% 74.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 25102 8.99% 83.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 12608 4.52% 87.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 8433 3.02% 90.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 5025 1.80% 92.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 3984 1.43% 94.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 2939 1.05% 95.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 13459 4.82% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 279155 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 26191 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 16.746211 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 10.447790 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-15 9423 35.98% 35.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::16-31 15107 57.68% 93.66% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::32-47 1332 5.09% 98.74% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::48-63 231 0.88% 99.63% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::64-79 66 0.25% 99.88% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::80-95 23 0.09% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::96-111 3 0.01% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::112-127 2 0.01% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::128-143 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::144-159 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::256-271 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::384-399 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 26191 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 26191 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 18.620404 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.778521 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 9.884507 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-7 23 0.09% 0.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-15 48 0.18% 0.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23 24431 93.28% 93.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31 637 2.43% 95.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39 499 1.91% 97.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47 119 0.45% 98.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55 74 0.28% 98.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63 52 0.20% 98.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71 187 0.71% 99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79 21 0.08% 99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87 13 0.05% 99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95 5 0.02% 99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103 5 0.02% 99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111 20 0.08% 99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119 7 0.03% 99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127 6 0.02% 99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135 18 0.07% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143 7 0.03% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151 1 0.00% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159 4 0.02% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167 2 0.01% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183 4 0.02% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191 1 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::232-239 1 0.00% 99.98% # Writes before turning the bus around for reads
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.physmem.wrPerTurnAround::240-247 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::248-255 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263 2 0.01% 99.99% # Writes before turning the bus around for reads
stats: update references
2016-07-21 18:19:18 +02:00
system.physmem.wrPerTurnAround::304-311 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::488-495 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 26191 # Writes before turning the bus around for reads
system.physmem.totQLat 8271276046 # Total ticks spent queuing
system.physmem.totMemAccLat 16495869796 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2193225000 # Total ticks spent in databus transfers
system.physmem.avgQLat 18856.42 # Average queueing delay per DRAM burst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: update references
2016-07-21 18:19:18 +02:00
system.physmem.avgMemAccLat 37606.42 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 0.55 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.61 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 0.55 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.61 # Average system write bandwidth in MiByte/s
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.physmem.busUtil 0.01 # Data bus utilization in percentage
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.physmem.busUtilRead 0.00 # Data bus utilization in percentage for reads
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
stats: update references
2016-07-21 18:19:18 +02:00
system.physmem.avgWrQLen 7.58 # Average write queue length when enqueuing
system.physmem.readRowHits 320460 # Number of row buffer hits during reads
system.physmem.writeRowHits 326715 # Number of row buffer hits during writes
system.physmem.readRowHitRate 73.06 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 66.99 # Row buffer hit rate for writes
system.physmem.avgGap 55377774.45 # Average gap between requests
system.physmem.pageHitRate 69.86 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 1063933920 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 578980875 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1709237400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 1568801520 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3313030902480 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1175120467920 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 30458927805750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 34952000129865 # Total energy per rank (pJ)
system.physmem_0.averagePower 665.969400 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 48914934224726 # Time in different power states
system.physmem_0.memoryStateTime::REF 1693778580000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: update references
2016-07-21 18:19:18 +02:00
system.physmem_0.memoryStateTime::ACT 115598736274 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: update references
2016-07-21 18:19:18 +02:00
system.physmem_1.actEnergy 1046477880 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 569311875 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1712123400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 1591410240 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3313030902480 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1175283684855 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 29689572406500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 34182806317230 # Total energy per rank (pJ)
system.physmem_1.averagePower 667.621570 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 48914700007992 # Time in different power states
system.physmem_1.memoryStateTime::REF 1693778580000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: update references
2016-07-21 18:19:18 +02:00
system.physmem_1.memoryStateTime::ACT 115815403258 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: update references
2016-07-21 18:19:18 +02:00
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
stats: update references
2016-07-21 18:19:18 +02:00
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks 91599 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 91599 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walkWaitTime::samples 91599 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0 91599 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 91599 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walksPending::samples 396804151420 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 1.489246 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 -194134706080 -48.92% -48.92% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1 590938857500 148.92% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 396804151420 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 67399 85.01% 85.01% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M 11889 14.99% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 79288 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 91599 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 91599 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 79288 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 79288 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 170887 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu0.dtb.read_hits 64302418 # DTB read hits
system.cpu0.dtb.read_misses 69160 # DTB read misses
system.cpu0.dtb.write_hits 58215557 # DTB write hits
system.cpu0.dtb.write_misses 22439 # DTB write misses
system.cpu0.dtb.flush_tlb 1189 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu0.dtb.flush_tlb_mva_asid 16108 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 410 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 41969 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu0.dtb.prefetch_faults 2769 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu0.dtb.perms_faults 7637 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 64371578 # DTB read accesses
system.cpu0.dtb.write_accesses 58237996 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu0.dtb.hits 122517975 # DTB hits
system.cpu0.dtb.misses 91599 # DTB misses
system.cpu0.dtb.accesses 122609574 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks 53904 # Table walker walks requested
system.cpu0.itb.walker.walksLong 53904 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walkWaitTime::samples 53904 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0 53904 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 53904 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walksPending::samples 396804151420 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 1.489341 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 -194172707080 -48.93% -48.93% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 590976858500 148.93% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 396804151420 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 47053 95.04% 95.04% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M 2454 4.96% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 49507 # Table walker page sizes translated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 53904 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 53904 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 49507 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 49507 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 103411 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 341562377 # ITB inst hits
system.cpu0.itb.inst_misses 53904 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu0.itb.flush_tlb 1189 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu0.itb.flush_tlb_mva_asid 16108 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 410 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 29855 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu0.itb.inst_accesses 341616281 # ITB inst accesses
system.cpu0.itb.hits 341562377 # DTB hits
system.cpu0.itb.misses 53904 # DTB misses
system.cpu0.itb.accesses 341616281 # DTB accesses
system.cpu0.numPwrStateTransitions 12142 # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples 6071 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean 8248096077.910065 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev 210376306672.099670 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows 2573 42.38% 42.38% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10 3474 57.22% 99.60% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5e+10-1e+11 5 0.08% 99.69% # Distribution of time spent in the clock gated state
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.70% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 4 0.07% 99.77% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.03% 99.80% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.02% 99.82% # Distribution of time spent in the clock gated state
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.84% # Distribution of time spent in the clock gated state
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.cpu0.pwrStateClkGateDist::8.5e+11-9e+11 1 0.02% 99.85% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::overflows 9 0.15% 100.00% # Distribution of time spent in the clock gated state
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 7947193303500 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total 6071 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON 1242069912008 # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 50074191288992 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 412426852 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update for UDelayEvent quiesce change
2015-10-10 23:45:41 +02:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu0.kern.inst.quiesce 16568 # number of quiesce instructions executed
system.cpu0.committedInsts 341412971 # Number of instructions committed
system.cpu0.committedOps 401608369 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 368837990 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 362244 # Number of float alu accesses
system.cpu0.num_func_calls 20461819 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 51941822 # number of instructions that are conditional controls
system.cpu0.num_int_insts 368837990 # number of integer instructions
system.cpu0.num_fp_insts 362244 # number of float instructions
system.cpu0.num_int_register_reads 539535569 # number of times the integer registers were read
system.cpu0.num_int_register_writes 292940682 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 578749 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 318148 # number of times the floating registers were written
system.cpu0.num_cc_register_reads 89683557 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 89472336 # number of times the CC registers were written
system.cpu0.num_mem_refs 122593410 # number of memory refs
system.cpu0.num_load_insts 64360945 # Number of load instructions
system.cpu0.num_store_insts 58232465 # Number of store instructions
system.cpu0.num_idle_cycles 402405334.403935 # Number of idle cycles
system.cpu0.num_busy_cycles 10021517.596065 # Number of busy cycles
system.cpu0.not_idle_fraction 0.024299 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.975701 # Percentage of idle cycles
system.cpu0.Branches 76142746 # Number of branches fetched
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu0.op_class::IntAlu 278290201 69.25% 69.25% # Class of executed instruction
system.cpu0.op_class::IntMult 876142 0.22% 69.47% # Class of executed instruction
system.cpu0.op_class::IntDiv 42968 0.01% 69.48% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 47686 0.01% 69.49% # Class of executed instruction
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.op_class::SimdFloatMult 0 0.00% 69.49% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.49% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.49% # Class of executed instruction
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu0.op_class::MemRead 64360945 16.02% 85.51% # Class of executed instruction
system.cpu0.op_class::MemWrite 58232465 14.49% 100.00% # Class of executed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu0.op_class::total 401850407 # Class of executed instruction
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 9785258 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.999715 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 296102427 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 9785770 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 30.258470 # Average number of references to valid blocks.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.924139 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 4.613790 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.156237 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu3.data 5.305549 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970555 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.009011 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.010071 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu3.data 0.010362 # Average percentage of cache occupancy
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu0.dcache.tags.tag_accesses 1254458148 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 1254458148 # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 60043274 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 19451230 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 26515970 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu3.data 46522470 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 152532944 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 55058218 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 17868348 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data 23514922 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu3.data 39147049 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 135588537 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 161685 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 47989 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data 79490 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu3.data 113267 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 402431 # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 128215 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu1.data 43197 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu2.data 56794 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu3.data 101554 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total 329760 # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1440792 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 445911 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 586217 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 965735 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 3438655 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1532117 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 486268 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data 631716 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu3.data 1115803 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 3765904 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 115229707 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 37362775 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data 50087686 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu3.data 85771073 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 288451241 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 115391392 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 37410764 # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data 50167176 # number of overall hits
system.cpu0.dcache.overall_hits::cpu3.data 85884340 # number of overall hits
system.cpu0.dcache.overall_hits::total 288853672 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 2089317 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 638437 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data 880712 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu3.data 3494222 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 7102688 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 831050 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 249767 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data 653536 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu3.data 3486415 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 5220768 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 516569 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 133434 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data 215040 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu3.data 331304 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 1196347 # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 659058 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu1.data 109033 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu2.data 156389 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu3.data 303598 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total 1228078 # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 91970 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 40583 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 45717 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 183696 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 361966 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu3.data 11 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 3579425 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 997237 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data 1690637 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu3.data 7284235 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 13551534 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 4095994 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 1130671 # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data 1905677 # number of overall misses
system.cpu0.dcache.overall_misses::cpu3.data 7615539 # number of overall misses
system.cpu0.dcache.overall_misses::total 14747881 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 9935057500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 14094035000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 51705605000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 75734697500 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 6989560000 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 18192565500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 96246799337 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 121428924837 # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 1815402000 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data 2628863500 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data 5749220797 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total 10193486297 # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 588884000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 647558500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 2284034500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 3520477000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 238500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 238500 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 18740019500 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data 34915464000 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu3.data 153701625134 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 207357108634 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 18740019500 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data 34915464000 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu3.data 153701625134 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 207357108634 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 62132591 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 20089667 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data 27396682 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu3.data 50016692 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 159635632 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 55889268 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 18118115 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 24168458 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu3.data 42633464 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 140809305 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 678254 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 181423 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 294530 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu3.data 444571 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 1598778 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 787273 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 152230 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu2.data 213183 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu3.data 405152 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total 1557838 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1532762 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 486494 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 631934 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data 1149431 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 3800621 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1532117 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 486268 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 631716 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 1115814 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 3765915 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 118809132 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 38360012 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data 51778323 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu3.data 93055308 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 302002775 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 119487386 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 38541435 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 52072853 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu3.data 93499879 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 303601553 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033627 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.031779 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.032147 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.069861 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.044493 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.014870 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.013785 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.027041 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.081776 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.037077 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.761616 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.735486 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.730112 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.745222 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.748288 # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.837140 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.716239 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data 0.733590 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data 0.749343 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.788322 # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060003 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.083419 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.072345 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.159815 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.095239 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000010 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000003 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030128 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025997 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.032651 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu3.data 0.078279 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.044872 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.034280 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.029337 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.036596 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu3.data 0.081450 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.048576 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15561.531522 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16003.000981 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 14797.458490 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 10662.821949 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 27984.321388 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 27837.128330 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 27606.237163 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 23258.824149 # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 16650.023387 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 16809.772426 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 18936.952144 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 8300.357385 # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14510.607890 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14164.501170 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 12433.773735 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9725.988076 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 21681.818182 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21681.818182 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18791.941635 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 20652.253559 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 21100.585735 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 15301.375374 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16574.246178 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 18321.816341 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 20182.632527 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 14060.128952 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 9910258 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 8881 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 889663 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 270 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 11.139339 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 32.892593 # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks 7576706 # number of writebacks
system.cpu0.dcache.writebacks::total 7576706 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 2565 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 39446 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 1918307 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 1960318 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 33 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 288880 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 2890218 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 3179131 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data 17 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data 2227 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total 2244 # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 9010 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 10983 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 113640 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 133633 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 2598 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data 328343 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu3.data 4810752 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 5141693 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 2598 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data 328343 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu3.data 4810752 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 5141693 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 635872 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 841266 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 1575915 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 3053053 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 249734 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 364656 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 596197 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 1210587 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 133434 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 214937 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 326698 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 675069 # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 109033 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data 156372 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data 301371 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total 566776 # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 31573 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 34734 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 70056 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 136363 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 11 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses
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system.cpu0.dcache.demand_mshr_misses::cpu2.data 1362294 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu3.data 2473483 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 4830416 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 1128073 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data 1577231 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu3.data 2800181 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 5505485 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 5165 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 4559 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 4594 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 14318 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 4682 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 4068 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 4289 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 13039 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 9847 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 8627 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 8883 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 27357 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 9259931500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 12493159000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 23820252500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 45573343000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6737865000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 9614650500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 17374860004 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 33727375504 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 2271729000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 3143350500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 4907861500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 10322941000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 1706369000 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data 2472082000 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data 5367328797 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 9545779797 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 413953500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 450661000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 926981000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1791595500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 227500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 227500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 17704165500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 24579891500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 46562441301 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 88846498301 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 19975894500 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 27723242000 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 51470302801 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 99169439301 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 937823500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 818983500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 848897000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2605704000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 937823500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 818983500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 848897000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2605704000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.031652 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.030707 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.031508 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.019125 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013784 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.015088 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.013984 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008597 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.735486 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.729763 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.734861 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.422241 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.716239 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data 0.733511 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data 0.743847 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.363822 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064899 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.054965 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.060948 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.035879 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000010 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000003 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025929 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.026310 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.026581 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.015995 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.029269 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.030289 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.029948 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.018134 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14562.571555 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14850.426619 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15115.188636 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14927.137852 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26980.166898 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26366.357608 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 29142.816894 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27860.348330 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17025.113539 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14624.520208 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15022.624871 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15291.682776 # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 15650.023387 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 15808.981148 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 17809.705635 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 16842.244197 # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13110.996738 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12974.635804 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 13232.000114 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13138.428313 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 20681.818182 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20681.818182 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17799.589097 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18043.015311 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 18824.645773 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18393.135974 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17707.980335 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17577.160226 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 18381.062796 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18012.843428 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 181572.797677 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 179641.039702 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 184783.848498 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 181987.987149 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95239.514573 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 94932.595340 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 95564.223798 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95248.163176 # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 15885620 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.975044 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 560402159 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 15886132 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 35.276187 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 9934044500 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 471.724807 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 2.897260 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst 29.967538 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu3.inst 7.385439 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.921338 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.005659 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.058530 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu3.inst 0.014425 # Average percentage of cache occupancy
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.icache.tags.occ_percent::total 0.999951 # Average percentage of cache occupancy
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu0.icache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu0.icache.tags.tag_accesses 592540078 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 592540078 # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 336114841 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 108439877 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 66818852 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu3.inst 49028589 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 560402159 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 336114841 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 108439877 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 66818852 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu3.inst 49028589 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 560402159 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 336114841 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 108439877 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 66818852 # number of overall hits
system.cpu0.icache.overall_hits::cpu3.inst 49028589 # number of overall hits
system.cpu0.icache.overall_hits::total 560402159 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 5497043 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 1722599 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 3878852 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu3.inst 5153185 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 16251679 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 5497043 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 1722599 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst 3878852 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu3.inst 5153185 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 16251679 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 5497043 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 1722599 # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst 3878852 # number of overall misses
system.cpu0.icache.overall_misses::cpu3.inst 5153185 # number of overall misses
system.cpu0.icache.overall_misses::total 16251679 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 23158585000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 52412047500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu3.inst 67562221360 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 143132853860 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 23158585000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst 52412047500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu3.inst 67562221360 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 143132853860 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 23158585000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst 52412047500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu3.inst 67562221360 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 143132853860 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 341611884 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 110162476 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 70697704 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu3.inst 54181774 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 576653838 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 341611884 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 110162476 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 70697704 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu3.inst 54181774 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 576653838 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 341611884 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 110162476 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 70697704 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu3.inst 54181774 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 576653838 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016091 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015637 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.054865 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu3.inst 0.095109 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.028183 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016091 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015637 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.054865 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu3.inst 0.095109 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.028183 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016091 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015637 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.054865 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu3.inst 0.095109 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.028183 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13443.979127 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13512.257622 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13110.769623 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 8807.265628 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13443.979127 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13512.257622 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13110.769623 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 8807.265628 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13443.979127 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13512.257622 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13110.769623 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 8807.265628 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 37944 # number of cycles access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu0.icache.blocked::no_mshrs 3053 # number of cycles access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.428431 # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu0.icache.writebacks::writebacks 15885620 # number of writebacks
system.cpu0.icache.writebacks::total 15885620 # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 365439 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 365439 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu3.inst 365439 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 365439 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu3.inst 365439 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 365439 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 1722599 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 3878852 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst 4787746 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 10389197 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 1722599 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst 3878852 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu3.inst 4787746 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 10389197 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 1722599 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst 3878852 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu3.inst 4787746 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 10389197 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 21435986000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 48533195500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 59905132390 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 129874313890 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 21435986000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 48533195500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 59905132390 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 129874313890 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 21435986000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 48533195500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 59905132390 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 129874313890 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015637 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.054865 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.088365 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.018016 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015637 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.054865 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.088365 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.018016 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015637 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.054865 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.088365 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.018016 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12443.979127 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12512.257622 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12512.178464 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12500.900107 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12443.979127 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12512.257622 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12512.178464 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12500.900107 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12443.979127 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12512.257622 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12512.178464 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12500.900107 # average overall mshr miss latency
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks 31142 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 31142 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4562 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 22714 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore 4 # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples 31138 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0 31138 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 31138 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 27280 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 24555.205279 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 21409.224401 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 12983.742991 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-32767 17842 65.40% 65.40% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-65535 9287 34.04% 99.45% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-98303 82 0.30% 99.75% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-131071 48 0.18% 99.92% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-163839 1 0.00% 99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::163840-196607 6 0.02% 99.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-229375 4 0.01% 99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::229376-262143 4 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-294911 3 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-360447 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::360448-393215 2 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 27280 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 2381232620 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean 0.574632 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev 0.494399 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 1012901000 42.54% 42.54% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1 1368331620 57.46% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 2381232620 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 22714 83.27% 83.27% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M 4562 16.73% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 27276 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 31142 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 31142 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 27276 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 27276 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 58418 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu1.dtb.read_hits 20762749 # DTB read hits
system.cpu1.dtb.read_misses 23873 # DTB read misses
system.cpu1.dtb.write_hits 18763804 # DTB write hits
system.cpu1.dtb.write_misses 7269 # DTB write misses
system.cpu1.dtb.flush_tlb 1182 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu1.dtb.flush_tlb_mva_asid 5192 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 138 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 17777 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu1.dtb.prefetch_faults 955 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu1.dtb.perms_faults 2493 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 20786622 # DTB read accesses
system.cpu1.dtb.write_accesses 18771073 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu1.dtb.hits 39526553 # DTB hits
system.cpu1.dtb.misses 31142 # DTB misses
system.cpu1.dtb.accesses 39557695 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks 19936 # Table walker walks requested
system.cpu1.itb.walker.walksLong 19936 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 932 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3 17656 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples 19936 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0 19936 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 19936 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 18588 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 27393.103077 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 24671.512984 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 13247.215063 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-32767 10003 53.81% 53.81% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-65535 8429 45.35% 99.16% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-98303 57 0.31% 99.47% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::98304-131071 80 0.43% 99.90% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-163839 2 0.01% 99.91% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::163840-196607 6 0.03% 99.94% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-229375 2 0.01% 99.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::229376-262143 4 0.02% 99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-294911 3 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::294912-327679 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.itb.walker.walkCompletionTime::360448-393215 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu1.itb.walker.walkCompletionTime::total 18588 # Table walker service (enqueue to completion) latency
stats: Update switcheroo reference stats The Minor draining fixes affect perturb the timing slightly since it affects how the simulator is drained. Update reference statistics to reflect this expected change.
2015-07-31 18:04:59 +02:00
system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu1.itb.walker.walkPageSizes::4K 17656 94.99% 94.99% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M 932 5.01% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 18588 # Table walker page sizes translated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 19936 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 19936 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 18588 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 18588 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 38524 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 110162476 # ITB inst hits
system.cpu1.itb.inst_misses 19936 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu1.itb.flush_tlb 1182 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu1.itb.flush_tlb_mva_asid 5192 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 138 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 13192 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu1.itb.inst_accesses 110182412 # ITB inst accesses
system.cpu1.itb.hits 110162476 # DTB hits
system.cpu1.itb.misses 19936 # DTB misses
system.cpu1.itb.accesses 110182412 # DTB accesses
system.cpu1.numPwrStateTransitions 6038 # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples 3019 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean 4031562886.362703 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev 205285027256.597076 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows 926 30.67% 30.67% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10 2090 69.23% 99.90% # Distribution of time spent in the clock gated state
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.03% 99.93% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 1 0.03% 99.97% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::overflows 1 0.03% 100.00% # Distribution of time spent in the clock gated state
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 11261576634501 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total 3019 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON 39144972847071 # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 12171288353929 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 1182097366 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update for UDelayEvent quiesce change
2015-10-10 23:45:41 +02:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu1.committedInsts 110088686 # Number of instructions committed
system.cpu1.committedOps 129237809 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 118887794 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 113577 # Number of float alu accesses
system.cpu1.num_func_calls 6597658 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 16662523 # number of instructions that are conditional controls
system.cpu1.num_int_insts 118887794 # number of integer instructions
system.cpu1.num_fp_insts 113577 # number of float instructions
system.cpu1.num_int_register_reads 170702989 # number of times the integer registers were read
system.cpu1.num_int_register_writes 94155610 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 183331 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 96228 # number of times the floating registers were written
system.cpu1.num_cc_register_reads 28150227 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 28060459 # number of times the CC registers were written
system.cpu1.num_mem_refs 39523640 # number of memory refs
system.cpu1.num_load_insts 20761578 # Number of load instructions
system.cpu1.num_store_insts 18762062 # Number of store instructions
system.cpu1.num_idle_cycles 1155305857.273267 # Number of idle cycles
system.cpu1.num_busy_cycles 26791508.726733 # Number of busy cycles
system.cpu1.not_idle_fraction 0.022664 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.977336 # Percentage of idle cycles
system.cpu1.Branches 24572277 # Number of branches fetched
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu1.op_class::IntAlu 89498355 69.21% 69.21% # Class of executed instruction
system.cpu1.op_class::IntMult 266792 0.21% 69.42% # Class of executed instruction
system.cpu1.op_class::IntDiv 10604 0.01% 69.43% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 69.43% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 69.43% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 69.43% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 69.43% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 69.43% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 69.43% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 69.43% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 69.43% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 69.43% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 69.43% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 69.43% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 69.43% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 69.43% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 69.43% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 69.43% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.43% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 69.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 12166 0.01% 69.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 69.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.44% # Class of executed instruction
system.cpu1.op_class::MemRead 20761578 16.06% 85.49% # Class of executed instruction
system.cpu1.op_class::MemWrite 18762062 14.51% 100.00% # Class of executed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu1.op_class::total 129311599 # Class of executed instruction
system.cpu2.branchPred.lookups 40882537 # Number of BP lookups
system.cpu2.branchPred.condPredicted 28404958 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 2018640 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 29949697 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 20329283 # Number of BTB hits
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu2.branchPred.BTBHitPct 67.878092 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 4945381 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 329320 # Number of incorrect RAS predictions.
system.cpu2.branchPred.indirectLookups 1144842 # Number of indirect predictor lookups.
system.cpu2.branchPred.indirectHits 797183 # Number of indirect target hits.
system.cpu2.branchPred.indirectMisses 347659 # Number of indirect misses.
system.cpu2.branchPredindirectMispredicted 143486 # Number of mispredicted indirect branches.
system.cpu2.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu2.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu2.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu2.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu2.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu2.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu2.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.cpu2.dtb.walker.walks 93219 # Table walker walks requested
system.cpu2.dtb.walker.walksLong 93219 # Table walker walks initiated with long descriptors
system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 7034 # Level at which table walker walks with long descriptors terminate
system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 30340 # Level at which table walker walks with long descriptors terminate
system.cpu2.dtb.walker.walkWaitTime::samples 93219 # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::0 93219 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::total 93219 # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkCompletionTime::samples 37374 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::mean 25165.904104 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::gmean 22274.336205 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::stdev 12675.748220 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::0-32767 24476 65.49% 65.49% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::32768-65535 12701 33.98% 99.47% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::65536-98303 113 0.30% 99.78% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::98304-131071 53 0.14% 99.92% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::131072-163839 2 0.01% 99.92% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::163840-196607 11 0.03% 99.95% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::196608-229375 2 0.01% 99.96% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::229376-262143 5 0.01% 99.97% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::262144-294911 6 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::294912-327679 2 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::327680-360447 2 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::total 37374 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walksPending::samples 2000359000 # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::0 2000359000 100.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::total 2000359000 # Table walker pending requests distribution
system.cpu2.dtb.walker.walkPageSizes::4K 30340 81.18% 81.18% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::2M 7034 18.82% 100.00% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::total 37374 # Table walker page sizes translated
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 93219 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 93219 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 37374 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 37374 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin::total 130593 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu2.dtb.read_hits 28583495 # DTB read hits
system.cpu2.dtb.read_misses 77825 # DTB read misses
system.cpu2.dtb.write_hits 25112772 # DTB write hits
system.cpu2.dtb.write_misses 15394 # DTB write misses
system.cpu2.dtb.flush_tlb 1182 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu2.dtb.flush_tlb_mva_asid 7038 # Number of times TLB was flushed by MVA & ASID
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu2.dtb.flush_tlb_asid 188 # Number of times TLB was flushed by ASID
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu2.dtb.flush_entries 22760 # Number of entries that have been flushed from TLB
system.cpu2.dtb.align_faults 83 # Number of TLB faults due to alignment restrictions
system.cpu2.dtb.prefetch_faults 2252 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu2.dtb.perms_faults 3984 # Number of TLB faults due to permissions restrictions
system.cpu2.dtb.read_accesses 28661320 # DTB read accesses
system.cpu2.dtb.write_accesses 25128166 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu2.dtb.hits 53696267 # DTB hits
system.cpu2.dtb.misses 93219 # DTB misses
system.cpu2.dtb.accesses 53789486 # DTB accesses
system.cpu2.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu2.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu2.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu2.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu2.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu2.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu2.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.cpu2.itb.walker.walks 27359 # Table walker walks requested
system.cpu2.itb.walker.walksLong 27359 # Table walker walks initiated with long descriptors
system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1819 # Level at which table walker walks with long descriptors terminate
system.cpu2.itb.walker.walksLongTerminationLevel::Level3 22616 # Level at which table walker walks with long descriptors terminate
system.cpu2.itb.walker.walkWaitTime::samples 27359 # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::0 27359 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::total 27359 # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkCompletionTime::samples 24435 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::mean 28370.002046 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::gmean 25752.666599 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::stdev 13391.544423 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::0-32767 12572 51.45% 51.45% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::32768-65535 11615 47.53% 98.99% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::65536-98303 92 0.38% 99.36% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::98304-131071 132 0.54% 99.90% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::131072-163839 2 0.01% 99.91% # Table walker service (enqueue to completion) latency
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu2.itb.walker.walkCompletionTime::163840-196607 9 0.04% 99.95% # Table walker service (enqueue to completion) latency
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu2.itb.walker.walkCompletionTime::196608-229375 5 0.02% 99.97% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::229376-262143 2 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::262144-294911 1 0.00% 99.98% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::294912-327679 2 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::327680-360447 2 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::total 24435 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walksPending::samples 2000327000 # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::0 2000327000 100.00% 100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::total 2000327000 # Table walker pending requests distribution
system.cpu2.itb.walker.walkPageSizes::4K 22616 92.56% 92.56% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::2M 1819 7.44% 100.00% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::total 24435 # Table walker page sizes translated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 27359 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Requested::total 27359 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 24435 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::total 24435 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin::total 51794 # Table walker requests started/completed, data/inst
system.cpu2.itb.inst_hits 70751081 # ITB inst hits
system.cpu2.itb.inst_misses 27359 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu2.itb.flush_tlb 1182 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu2.itb.flush_tlb_mva_asid 7038 # Number of times TLB was flushed by MVA & ASID
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu2.itb.flush_tlb_asid 188 # Number of times TLB was flushed by ASID
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu2.itb.flush_entries 17251 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu2.itb.perms_faults 50621 # Number of TLB faults due to permissions restrictions
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_accesses 0 # DTB write accesses
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu2.itb.inst_accesses 70778440 # ITB inst accesses
system.cpu2.itb.hits 70751081 # DTB hits
system.cpu2.itb.misses 27359 # DTB misses
system.cpu2.itb.accesses 70778440 # DTB accesses
system.cpu2.numPwrStateTransitions 7068 # Number of power state transitions
system.cpu2.pwrStateClkGateDist::samples 3534 # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::mean 14278760224.142614 # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::stdev 128952650694.550415 # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::underflows 1173 33.19% 33.19% # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::1000-5e+10 2324 65.76% 98.95% # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::5e+10-1e+11 6 0.17% 99.12% # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::1e+11-1.5e+11 3 0.08% 99.21% # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::1.5e+11-2e+11 2 0.06% 99.26% # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::2e+11-2.5e+11 2 0.06% 99.32% # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::2.5e+11-3e+11 2 0.06% 99.38% # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::3e+11-3.5e+11 1 0.03% 99.41% # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::4.5e+11-5e+11 1 0.03% 99.43% # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::5e+11-5.5e+11 1 0.03% 99.46% # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::7e+11-7.5e+11 1 0.03% 99.49% # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::overflows 18 0.51% 100.00% # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::max_value 1988791938500 # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::total 3534 # Distribution of time spent in the clock gated state
system.cpu2.pwrStateResidencyTicks::ON 855122568880 # Cumulative time (in ticks) in various power states
system.cpu2.pwrStateResidencyTicks::CLK_GATED 50461138632120 # Cumulative time (in ticks) in various power states
system.cpu2.numCycles 1176514820 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu2.committedInsts 148015275 # Number of instructions committed
system.cpu2.committedOps 173576253 # Number of ops (including micro ops) committed
system.cpu2.discardedOps 15019689 # Number of ops (including micro ops) which were discarded before commit
system.cpu2.numFetchSuspends 1599 # Number of times Execute suspended instruction fetching
system.cpu2.quiesceCycles 5679254 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.cpi 7.948604 # CPI: cycles per instruction
system.cpu2.ipc 0.125808 # IPC: instructions per cycle
stats: Match current behaviour Small changes to the branch predictor and BTB caused stats changes throughout.
2016-04-09 18:13:40 +02:00
system.cpu2.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu2.op_class_0::IntAlu 120466035 69.40% 69.40% # Class of committed instruction
system.cpu2.op_class_0::IntMult 363809 0.21% 69.61% # Class of committed instruction
system.cpu2.op_class_0::IntDiv 14931 0.01% 69.62% # Class of committed instruction
system.cpu2.op_class_0::FloatAdd 0 0.00% 69.62% # Class of committed instruction
system.cpu2.op_class_0::FloatCmp 0 0.00% 69.62% # Class of committed instruction
system.cpu2.op_class_0::FloatCvt 0 0.00% 69.62% # Class of committed instruction
system.cpu2.op_class_0::FloatMult 0 0.00% 69.62% # Class of committed instruction
system.cpu2.op_class_0::FloatDiv 0 0.00% 69.62% # Class of committed instruction
system.cpu2.op_class_0::FloatSqrt 0 0.00% 69.62% # Class of committed instruction
system.cpu2.op_class_0::SimdAdd 0 0.00% 69.62% # Class of committed instruction
system.cpu2.op_class_0::SimdAddAcc 0 0.00% 69.62% # Class of committed instruction
system.cpu2.op_class_0::SimdAlu 0 0.00% 69.62% # Class of committed instruction
system.cpu2.op_class_0::SimdCmp 0 0.00% 69.62% # Class of committed instruction
system.cpu2.op_class_0::SimdCvt 0 0.00% 69.62% # Class of committed instruction
system.cpu2.op_class_0::SimdMisc 0 0.00% 69.62% # Class of committed instruction
system.cpu2.op_class_0::SimdMult 0 0.00% 69.62% # Class of committed instruction
system.cpu2.op_class_0::SimdMultAcc 0 0.00% 69.62% # Class of committed instruction
system.cpu2.op_class_0::SimdShift 0 0.00% 69.62% # Class of committed instruction
system.cpu2.op_class_0::SimdShiftAcc 0 0.00% 69.62% # Class of committed instruction
system.cpu2.op_class_0::SimdSqrt 0 0.00% 69.62% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatAdd 0 0.00% 69.62% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatAlu 0 0.00% 69.62% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatCmp 0 0.00% 69.62% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatCvt 0 0.00% 69.62% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatDiv 0 0.00% 69.62% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatMisc 14962 0.01% 69.63% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatMult 0 0.00% 69.63% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatMultAcc 0 0.00% 69.63% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatSqrt 0 0.00% 69.63% # Class of committed instruction
system.cpu2.op_class_0::MemRead 27697831 15.96% 85.59% # Class of committed instruction
system.cpu2.op_class_0::MemWrite 25018685 14.41% 100.00% # Class of committed instruction
stats: Match current behaviour Small changes to the branch predictor and BTB caused stats changes throughout.
2016-04-09 18:13:40 +02:00
system.cpu2.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu2.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu2.op_class_0::total 173576253 # Class of committed instruction
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu2.tickCycles 278505998 # Number of cycles that the object actually ticked
system.cpu2.idleCycles 898008822 # Total number of cycles that the object has spent stopped
system.cpu3.branchPred.lookups 76056401 # Number of BP lookups
system.cpu3.branchPred.condPredicted 50755289 # Number of conditional branches predicted
system.cpu3.branchPred.condIncorrect 3415271 # Number of conditional branches incorrect
system.cpu3.branchPred.BTBLookups 50793125 # Number of BTB lookups
system.cpu3.branchPred.BTBHits 34573256 # Number of BTB hits
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.branchPred.BTBHitPct 68.066802 # BTB Hit Percentage
system.cpu3.branchPred.usedRAS 9840520 # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect 107050 # Number of incorrect RAS predictions.
system.cpu3.branchPred.indirectLookups 3054055 # Number of indirect predictor lookups.
system.cpu3.branchPred.indirectHits 1548215 # Number of indirect target hits.
system.cpu3.branchPred.indirectMisses 1505840 # Number of indirect misses.
system.cpu3.branchPredindirectMispredicted 248236 # Number of mispredicted indirect branches.
system.cpu3.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu3.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu3.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu3.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu3.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu3.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu3.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu3.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu3.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu3.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu3.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu3.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu3.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.cpu3.dtb.walker.walks 519832 # Table walker walks requested
system.cpu3.dtb.walker.walksLong 519832 # Table walker walks initiated with long descriptors
system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8563 # Level at which table walker walks with long descriptors terminate
system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 50762 # Level at which table walker walks with long descriptors terminate
system.cpu3.dtb.walker.walksSquashedBefore 324579 # Table walks squashed before starting
system.cpu3.dtb.walker.walkWaitTime::samples 195253 # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::mean 2247.443061 # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::stdev 12961.897479 # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::0-32767 191171 97.91% 97.91% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::32768-65535 2882 1.48% 99.39% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::65536-98303 501 0.26% 99.64% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::98304-131071 350 0.18% 99.82% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::131072-163839 155 0.08% 99.90% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::163840-196607 49 0.03% 99.93% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::196608-229375 39 0.02% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::229376-262143 21 0.01% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::262144-294911 33 0.02% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::294912-327679 19 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::327680-360447 2 0.00% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::360448-393215 6 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::393216-425983 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::425984-458751 14 0.01% 100.00% # Table walker wait (enqueue to first request) latency
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu3.dtb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.dtb.walker.walkWaitTime::total 195253 # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkCompletionTime::samples 240674 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::mean 22283.310619 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::gmean 18185.362858 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::stdev 16504.392629 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::0-65535 236088 98.09% 98.09% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::65536-131071 4155 1.73% 99.82% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::131072-196607 185 0.08% 99.90% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::196608-262143 125 0.05% 99.95% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::262144-327679 40 0.02% 99.97% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::327680-393215 50 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::393216-458751 22 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::458752-524287 7 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::total 240674 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walksPending::samples -21483315588 # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::mean 0.617433 # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::0-3 -22069775588 102.73% 102.73% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::4-7 326975000 -1.52% 101.21% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::8-11 109953500 -0.51% 100.70% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::12-15 66787000 -0.31% 100.39% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::16-19 27414500 -0.13% 100.26% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::20-23 14643500 -0.07% 100.19% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::24-27 14038500 -0.07% 100.12% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::28-31 22874000 -0.11% 100.02% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::32-35 3351000 -0.02% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::36-39 112000 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::40-43 25000 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::44-47 22000 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::48-51 17000 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::52-55 205500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::56-59 41500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::total -21483315588 # Table walker pending requests distribution
system.cpu3.dtb.walker.walkPageSizes::4K 50762 85.57% 85.57% # Table walker page sizes translated
system.cpu3.dtb.walker.walkPageSizes::2M 8563 14.43% 100.00% # Table walker page sizes translated
system.cpu3.dtb.walker.walkPageSizes::total 59325 # Table walker page sizes translated
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 519832 # Table walker requests started/completed, data/inst
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 519832 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 59325 # Table walker requests started/completed, data/inst
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 59325 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin::total 579157 # Table walker requests started/completed, data/inst
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.inst_hits 0 # ITB inst hits
system.cpu3.dtb.inst_misses 0 # ITB inst misses
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.dtb.read_hits 59705170 # DTB read hits
system.cpu3.dtb.read_misses 356680 # DTB read misses
system.cpu3.dtb.write_hits 46676545 # DTB write hits
system.cpu3.dtb.write_misses 163152 # DTB write misses
system.cpu3.dtb.flush_tlb 1183 # Number of times complete TLB was flushed
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.dtb.flush_tlb_mva_asid 11749 # Number of times TLB was flushed by MVA & ASID
system.cpu3.dtb.flush_tlb_asid 293 # Number of times TLB was flushed by ASID
system.cpu3.dtb.flush_entries 29163 # Number of entries that have been flushed from TLB
system.cpu3.dtb.align_faults 78 # Number of TLB faults due to alignment restrictions
system.cpu3.dtb.prefetch_faults 4872 # Number of TLB faults due to prefetch
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.dtb.perms_faults 30504 # Number of TLB faults due to permissions restrictions
system.cpu3.dtb.read_accesses 60061850 # DTB read accesses
system.cpu3.dtb.write_accesses 46839697 # DTB write accesses
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.inst_accesses 0 # ITB inst accesses
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.dtb.hits 106381715 # DTB hits
system.cpu3.dtb.misses 519832 # DTB misses
system.cpu3.dtb.accesses 106901547 # DTB accesses
system.cpu3.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu3.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu3.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu3.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu3.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu3.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu3.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu3.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu3.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu3.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu3.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu3.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu3.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.cpu3.itb.walker.walks 58984 # Table walker walks requested
system.cpu3.itb.walker.walksLong 58984 # Table walker walks initiated with long descriptors
system.cpu3.itb.walker.walksLongTerminationLevel::Level2 2019 # Level at which table walker walks with long descriptors terminate
system.cpu3.itb.walker.walksLongTerminationLevel::Level3 40730 # Level at which table walker walks with long descriptors terminate
system.cpu3.itb.walker.walksSquashedBefore 8213 # Table walks squashed before starting
system.cpu3.itb.walker.walkWaitTime::samples 50771 # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::mean 1255.214591 # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::stdev 7667.557499 # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::0-32767 50302 99.08% 99.08% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::32768-65535 327 0.64% 99.72% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::65536-98303 93 0.18% 99.90% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::98304-131071 33 0.06% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::131072-163839 8 0.02% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::163840-196607 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu3.itb.walker.walkWaitTime::196608-229375 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::229376-262143 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::total 50771 # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkCompletionTime::samples 50962 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::mean 27876.584514 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::gmean 23887.788397 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::stdev 16739.526598 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::0-65535 49958 98.03% 98.03% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::65536-131071 889 1.74% 99.77% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::131072-196607 72 0.14% 99.92% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::196608-262143 26 0.05% 99.97% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::262144-327679 9 0.02% 99.98% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::327680-393215 7 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::total 50962 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walksPending::samples -21485924088 # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::mean 1.063775 # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::0 1402683284 -6.53% -6.53% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::1 -22917683872 106.66% 100.14% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::2 26044500 -0.12% 100.01% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::3 2758500 -0.01% 100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::4 237000 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::5 36500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::total -21485924088 # Table walker pending requests distribution
system.cpu3.itb.walker.walkPageSizes::4K 40730 95.28% 95.28% # Table walker page sizes translated
system.cpu3.itb.walker.walkPageSizes::2M 2019 4.72% 100.00% # Table walker page sizes translated
system.cpu3.itb.walker.walkPageSizes::total 42749 # Table walker page sizes translated
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 58984 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Requested::total 58984 # Table walker requests started/completed, data/inst
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 42749 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::total 42749 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin::total 101733 # Table walker requests started/completed, data/inst
system.cpu3.itb.inst_hits 54309249 # ITB inst hits
system.cpu3.itb.inst_misses 58984 # ITB inst misses
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.itb.read_hits 0 # DTB read hits
system.cpu3.itb.read_misses 0 # DTB read misses
system.cpu3.itb.write_hits 0 # DTB write hits
system.cpu3.itb.write_misses 0 # DTB write misses
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.itb.flush_tlb 1183 # Number of times complete TLB was flushed
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.itb.flush_tlb_mva_asid 11749 # Number of times TLB was flushed by MVA & ASID
system.cpu3.itb.flush_tlb_asid 293 # Number of times TLB was flushed by ASID
system.cpu3.itb.flush_entries 22226 # Number of entries that have been flushed from TLB
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.itb.perms_faults 110359 # Number of TLB faults due to permissions restrictions
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.itb.read_accesses 0 # DTB read accesses
system.cpu3.itb.write_accesses 0 # DTB write accesses
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.itb.inst_accesses 54368233 # ITB inst accesses
system.cpu3.itb.hits 54309249 # DTB hits
system.cpu3.itb.misses 58984 # DTB misses
system.cpu3.itb.accesses 54368233 # DTB accesses
system.cpu3.numPwrStateTransitions 7050 # Number of power state transitions
system.cpu3.pwrStateClkGateDist::samples 3525 # Distribution of time spent in the clock gated state
system.cpu3.pwrStateClkGateDist::mean 48150318.502695 # Distribution of time spent in the clock gated state
system.cpu3.pwrStateClkGateDist::stdev 1097902153.303432 # Distribution of time spent in the clock gated state
system.cpu3.pwrStateClkGateDist::underflows 2138 60.65% 60.65% # Distribution of time spent in the clock gated state
system.cpu3.pwrStateClkGateDist::1000-5e+10 1387 39.35% 100.00% # Distribution of time spent in the clock gated state
system.cpu3.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
system.cpu3.pwrStateClkGateDist::max_value 36013437604 # Distribution of time spent in the clock gated state
system.cpu3.pwrStateClkGateDist::total 3525 # Distribution of time spent in the clock gated state
system.cpu3.pwrStateResidencyTicks::ON 51146531328278 # Cumulative time (in ticks) in various power states
system.cpu3.pwrStateResidencyTicks::CLK_GATED 169729872722 # Cumulative time (in ticks) in various power states
system.cpu3.numCycles 361675800 # number of cpu cycles simulated
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.fetch.icacheStallCycles 142734990 # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts 337553362 # Number of instructions fetch has processed
system.cpu3.fetch.Branches 76056401 # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches 45961991 # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles 197659540 # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles 7720824 # Number of cycles fetch has spent squashing
system.cpu3.fetch.TlbCycles 1399327 # Number of cycles fetch has spent waiting for tlb
system.cpu3.fetch.MiscStallCycles 5628 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.PendingDrainCycles 1517 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu3.fetch.PendingTrapStallCycles 2684967 # Number of stall cycles due to pending traps
system.cpu3.fetch.PendingQuiesceStallCycles 90171 # Number of stall cycles due to pending quiesce instructions
system.cpu3.fetch.IcacheWaitRetryStallCycles 3829 # Number of stall cycles due to full MSHR
system.cpu3.fetch.CacheLines 54181818 # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes 2125134 # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.ItlbSquashes 22298 # Number of outstanding ITLB misses that were squashed
system.cpu3.fetch.rateDist::samples 348440253 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean 1.132379 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev 2.378502 # Number of instructions fetched each cycle (Total)
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.fetch.rateDist::0 265738138 76.27% 76.27% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1 10408686 2.99% 79.25% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2 10350946 2.97% 82.22% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3 7718330 2.22% 84.44% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4 15611358 4.48% 88.92% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5 5061575 1.45% 90.37% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6 5537323 1.59% 91.96% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7 4787480 1.37% 93.33% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8 23226417 6.67% 100.00% # Number of instructions fetched each cycle (Total)
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.fetch.rateDist::total 348440253 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate 0.210289 # Number of branch fetches per cycle
system.cpu3.fetch.rate 0.933304 # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles 116402482 # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles 160353660 # Number of cycles decode is blocked
system.cpu3.decode.RunCycles 61341979 # Number of cycles decode is running
system.cpu3.decode.UnblockCycles 7283918 # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles 3056510 # Number of cycles decode is squashing
system.cpu3.decode.BranchResolved 11212857 # Number of times decode resolved a branch
system.cpu3.decode.BranchMispred 815162 # Number of times decode detected a branch misprediction
system.cpu3.decode.DecodedInsts 368532981 # Number of instructions handled by decode
system.cpu3.decode.SquashedInsts 2520228 # Number of squashed instructions handled by decode
system.cpu3.rename.SquashCycles 3056510 # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles 120624207 # Number of cycles rename is idle
system.cpu3.rename.BlockCycles 11509026 # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles 131064171 # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles 64320905 # Number of cycles rename is running
system.cpu3.rename.UnblockCycles 17863677 # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts 359702121 # Number of instructions processed by rename
system.cpu3.rename.ROBFullEvents 43833 # Number of times rename has blocked due to ROB full
system.cpu3.rename.IQFullEvents 968665 # Number of times rename has blocked due to IQ full
system.cpu3.rename.LQFullEvents 780315 # Number of times rename has blocked due to LQ full
system.cpu3.rename.SQFullEvents 7689356 # Number of times rename has blocked due to SQ full
system.cpu3.rename.FullRegisterEvents 2098 # Number of times there has been no free registers
system.cpu3.rename.RenamedOperands 342552995 # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups 547002223 # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups 423527131 # Number of integer rename lookups
system.cpu3.rename.fp_rename_lookups 526597 # Number of floating rename lookups
system.cpu3.rename.CommittedMaps 286388562 # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps 56164428 # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts 8049002 # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts 6906783 # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts 40039981 # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads 58078564 # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores 48988354 # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads 7585006 # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores 8037000 # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded 341408601 # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded 8081994 # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued 340240717 # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued 497823 # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined 47426361 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined 29768333 # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved 191877 # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples 348440253 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean 0.976468 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev 1.690233 # Number of insts issued each cycle
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.iq.issued_per_cycle::0 216890475 62.25% 62.25% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1 53877096 15.46% 77.71% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2 24807816 7.12% 84.83% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3 17922235 5.14% 89.97% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4 13075143 3.75% 93.72% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5 9287871 2.67% 96.39% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6 6359964 1.83% 98.22% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7 3675651 1.05% 99.27% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8 2544002 0.73% 100.00% # Number of insts issued each cycle
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.iq.issued_per_cycle::total 348440253 # Number of insts issued each cycle
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.iq.fu_full::IntAlu 1734447 26.04% 26.04% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult 17043 0.26% 26.30% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv 1093 0.02% 26.31% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.31% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.31% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.31% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.31% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.31% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.31% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.31% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.31% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.31% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.31% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.31% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.31% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.31% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.31% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.31% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.31% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.31% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.31% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.31% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.31% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.31% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.31% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.31% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.31% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.31% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.31% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead 2643216 39.68% 66.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite 2264697 34.00% 100.00% # attempts to use FU when none available
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.iq.FU_type_0::No_OpClass 10 0.00% 0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu 231030792 67.90% 67.90% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult 845869 0.25% 68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv 38944 0.01% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd 198 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc 42651 0.01% 68.17% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.17% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.17% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.17% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead 61002567 17.93% 86.10% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite 47279686 13.90% 100.00% # Type of FU issued
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.iq.FU_type_0::total 340240717 # Type of FU issued
system.cpu3.iq.rate 0.940734 # Inst issue rate
system.cpu3.iq.fu_busy_cnt 6660496 # FU busy when requested
system.cpu3.iq.fu_busy_rate 0.019576 # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads 1035420885 # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes 396967626 # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses 327898797 # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads 659121 # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes 337856 # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses 293479 # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses 346548979 # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses 352224 # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads 2687529 # Number of loads that had data forwarded from stores
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.iew.lsq.thread0.squashedLoads 9720232 # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses 11871 # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation 394856 # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores 4837016 # Number of stores squashed
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.iew.lsq.thread0.rescheduledLoads 2125891 # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked 3923806 # Number of times an access to memory failed due to the cache being blocked
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.iew.iewSquashCycles 3056510 # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles 7986555 # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles 2673304 # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts 349575098 # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts 1017291 # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts 58078564 # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts 48988354 # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts 6756692 # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents 121038 # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents 2506923 # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents 394856 # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect 1446513 # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect 1609649 # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts 3056162 # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts 336167665 # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts 59696171 # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts 3560031 # Number of squashed instructions skipped in execute
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iew.exec_swp 0 # number of swp insts executed
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.iew.exec_nop 84503 # number of nop insts executed
system.cpu3.iew.exec_refs 106371515 # number of memory reference insts executed
system.cpu3.iew.exec_branches 62288679 # Number of branches executed
system.cpu3.iew.exec_stores 46675344 # Number of stores executed
system.cpu3.iew.exec_rate 0.929472 # Inst execution rate
system.cpu3.iew.wb_sent 329005088 # cumulative count of insts sent to commit
system.cpu3.iew.wb_count 328192276 # cumulative count of insts written-back
system.cpu3.iew.wb_producers 162018804 # num instructions producing a value
system.cpu3.iew.wb_consumers 281033502 # num instructions consuming a value
system.cpu3.iew.wb_rate 0.907421 # insts written-back per cycle
system.cpu3.iew.wb_fanout 0.576511 # average fanout of values written-back
system.cpu3.commit.commitSquashedInsts 47454465 # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls 7890117 # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts 2611241 # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples 340404707 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean 0.887368 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev 1.879512 # Number of insts commited each cycle
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.commit.committed_per_cycle::0 230935782 67.84% 67.84% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1 52807469 15.51% 83.35% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2 18991951 5.58% 88.93% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3 8773061 2.58% 91.51% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4 6429800 1.89% 93.40% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5 3748451 1.10% 94.50% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6 3528982 1.04% 95.54% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7 2195360 0.64% 96.18% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8 12993851 3.82% 100.00% # Number of insts commited each cycle
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.commit.committed_per_cycle::total 340404707 # Number of insts commited each cycle
system.cpu3.commit.committedInsts 257000704 # Number of instructions committed
system.cpu3.commit.committedOps 302064229 # Number of ops (including micro ops) committed
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.commit.refs 92509669 # Number of memory references committed
system.cpu3.commit.loads 48358331 # Number of loads committed
system.cpu3.commit.membars 2078465 # Number of memory barriers committed
system.cpu3.commit.branches 57378073 # Number of branches committed
system.cpu3.commit.fp_insts 281556 # Number of committed floating point instructions.
system.cpu3.commit.int_insts 277690269 # Number of committed integer instructions.
system.cpu3.commit.function_calls 7642177 # Number of function calls committed.
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.commit.op_class_0::IntAlu 208831181 69.13% 69.13% # Class of committed instruction
system.cpu3.commit.op_class_0::IntMult 657786 0.22% 69.35% # Class of committed instruction
system.cpu3.commit.op_class_0::IntDiv 28932 0.01% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMisc 36661 0.01% 69.37% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.37% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.37% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.37% # Class of committed instruction
system.cpu3.commit.op_class_0::MemRead 48358331 16.01% 85.38% # Class of committed instruction
system.cpu3.commit.op_class_0::MemWrite 44151338 14.62% 100.00% # Class of committed instruction
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.commit.op_class_0::total 302064229 # Class of committed instruction
system.cpu3.commit.bw_lim_events 12993851 # number cycles where commit BW limit reached
system.cpu3.rob.rob_reads 674816220 # The number of ROB reads
system.cpu3.rob.rob_writes 707084678 # The number of ROB writes
system.cpu3.timesIdled 2433054 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles 13235547 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles 98724531811 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts 257000704 # Number of Instructions Simulated
system.cpu3.committedOps 302064229 # Number of Ops (including micro ops) Simulated
system.cpu3.cpi 1.407295 # CPI: Cycles Per Instruction
system.cpu3.cpi_total 1.407295 # CPI: Total CPI of All Threads
system.cpu3.ipc 0.710583 # IPC: Instructions Per Cycle
system.cpu3.ipc_total 0.710583 # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads 395540710 # number of integer regfile reads
system.cpu3.int_regfile_writes 235084371 # number of integer regfile writes
system.cpu3.fp_regfile_reads 573493 # number of floating regfile reads
system.cpu3.fp_regfile_writes 349924 # number of floating regfile writes
system.cpu3.cc_regfile_reads 70842645 # number of cc regfile reads
system.cpu3.cc_regfile_writes 71511543 # number of cc regfile writes
stats: update references
2016-08-02 12:34:32 +02:00
system.cpu3.misc_regfile_reads 658562640 # number of misc regfile reads
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu3.misc_regfile_writes 7924534 # number of misc regfile writes
system.iobus.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 40262 # Transaction distribution
system.iobus.trans_dist::ReadResp 40262 # Transaction distribution
stats: Match current behaviour Small changes to the branch predictor and BTB caused stats changes throughout.
2016-04-09 18:13:40 +02:00
system.iobus.trans_dist::WriteReq 136539 # Transaction distribution
system.iobus.trans_dist::WriteResp 136539 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47694 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
stats: Match current behaviour Small changes to the branch predictor and BTB caused stats changes throughout.
2016-04-09 18:13:40 +02:00
system.iobus.pkt_count_system.bridge.master::total 122576 # Packet count per connected master and slave (bytes)
stats: update references
2016-07-21 18:19:18 +02:00
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230946 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 230946 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
stats: update references
2016-07-21 18:19:18 +02:00
system.iobus.pkt_count::total 353602 # Packet count per connected master and slave (bytes)
stats: Match current behaviour Small changes to the branch predictor and BTB caused stats changes throughout.
2016-04-09 18:13:40 +02:00
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47714 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
stats: Match current behaviour Small changes to the branch predictor and BTB caused stats changes throughout.
2016-04-09 18:13:40 +02:00
system.iobus.pkt_size_system.bridge.master::total 155706 # Cumulative packet size per connected master and slave (bytes)
stats: update references
2016-07-21 18:19:18 +02:00
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334216 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7334216 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
stats: update references
2016-07-21 18:19:18 +02:00
system.iobus.pkt_size::total 7492008 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 13479500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: update references
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: update references
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer2.occupancy 17000 # Layer occupancy (ticks)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: update references
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
stats: update references
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks)
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks)
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks)
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
stats: Match current behaviour Small changes to the branch predictor and BTB caused stats changes throughout.
2016-04-09 18:13:40 +02:00
system.iobus.reqLayer16.occupancy 5000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks)
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
stats: update references
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer23.occupancy 10717000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
stats: update references
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer24.occupancy 21643000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
stats: update references
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer25.occupancy 229106103 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
stats: update references
2016-07-21 18:19:18 +02:00
system.iobus.respLayer0.occupancy 40091000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: update references
2016-07-21 18:19:18 +02:00
system.iobus.respLayer3.occupancy 47420000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: update references
2016-07-21 18:19:18 +02:00
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 115455 # number of replacements
system.iocache.tags.tagsinuse 10.425438 # Cycle average of tags in use
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
stats: update references
2016-07-21 18:19:18 +02:00
system.iocache.tags.sampled_refs 115471 # Sample count of references to valid blocks.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
stats: update references
2016-07-21 18:19:18 +02:00
system.iocache.tags.warmup_cycle 13087296764009 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.544648 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 6.880790 # Average occupied blocks per requestor
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iocache.tags.occ_percent::realview.ethernet 0.221541 # Average percentage of cache occupancy
stats: update references
2016-07-21 18:19:18 +02:00
system.iocache.tags.occ_percent::realview.ide 0.430049 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.651590 # Average percentage of cache occupancy
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
stats: update references
2016-07-21 18:19:18 +02:00
system.iocache.tags.tag_accesses 1039614 # Number of tag accesses
system.iocache.tags.data_accesses 1039614 # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
stats: update references
2016-07-21 18:19:18 +02:00
system.iocache.ReadReq_misses::realview.ide 8809 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8846 # number of ReadReq misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
stats: update references
2016-07-21 18:19:18 +02:00
system.iocache.demand_misses::realview.ide 115473 # number of demand (read+write) misses
system.iocache.demand_misses::total 115513 # number of demand (read+write) misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
stats: update references
2016-07-21 18:19:18 +02:00
system.iocache.overall_misses::realview.ide 115473 # number of overall misses
system.iocache.overall_misses::total 115513 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide 148237434 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 148237434 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 5184314669 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 5184314669 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide 5332552103 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 5332552103 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 5332552103 # number of overall miss cycles
system.iocache.overall_miss_latency::total 5332552103 # number of overall miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
stats: update references
2016-07-21 18:19:18 +02:00
system.iocache.ReadReq_accesses::realview.ide 8809 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8846 # number of ReadReq accesses(hits+misses)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
stats: update references
2016-07-21 18:19:18 +02:00
system.iocache.demand_accesses::realview.ide 115473 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 115513 # number of demand (read+write) accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
stats: update references
2016-07-21 18:19:18 +02:00
system.iocache.overall_accesses::realview.ide 115473 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 115513 # number of overall (read+write) accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: update references
2016-07-21 18:19:18 +02:00
system.iocache.ReadReq_avg_miss_latency::realview.ide 16827.952549 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 16757.566584 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 48604.165126 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 48604.165126 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 46180.077620 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 46164.086319 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 46180.077620 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 46164.086319 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 2296 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: update references
2016-07-21 18:19:18 +02:00
system.iocache.blocked::no_mshrs 267 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: update references
2016-07-21 18:19:18 +02:00
system.iocache.avg_blocked_cycles::no_mshrs 8.599251 # average number of cycles each access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.iocache.writebacks::writebacks 106631 # number of writebacks
system.iocache.writebacks::total 106631 # number of writebacks
stats: update references
2016-07-21 18:19:18 +02:00
system.iocache.ReadReq_mshr_misses::realview.ide 910 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 43872 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 43872 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide 44782 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 44782 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 44782 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 44782 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide 102737434 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 102737434 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2987814984 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 2987814984 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 3090552418 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 3090552418 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 3090552418 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 3090552418 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.103303 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.102871 # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.411310 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 0.411310 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide 0.387814 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 0.387679 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 0.387814 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 0.387679 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112898.279121 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 112898.279121 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68103.003829 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68103.003829 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 69013.273592 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 69013.273592 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 69013.273592 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 69013.273592 # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 1178177 # number of replacements
system.l2c.tags.tagsinuse 65299.544871 # Cycle average of tags in use
system.l2c.tags.total_refs 47783107 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1240954 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 38.505140 # Average number of references to valid blocks.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit.
stats: update references
2016-07-21 18:19:18 +02:00
system.l2c.tags.occ_blocks::writebacks 36300.809857 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 130.329243 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 195.620388 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 3095.266131 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 10240.571353 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 40.874592 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 51.867132 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 1035.336911 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 2451.400254 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker 46.677403 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.itb.walker 75.693349 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 2509.241112 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 3335.896210 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.dtb.walker 90.056966 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.itb.walker 140.583636 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.inst 1763.583672 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.data 3795.736663 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.553906 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001989 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.002985 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.047230 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.156259 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000624 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.000791 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.015798 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.037405 # Average percentage of cache occupancy
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000712 # Average percentage of cache occupancy
stats: update references
2016-07-21 18:19:18 +02:00
system.l2c.tags.occ_percent::cpu2.itb.walker 0.001155 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.038288 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.050902 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.dtb.walker 0.001374 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.itb.walker 0.002145 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst 0.026910 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data 0.057918 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.996392 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 349 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 62428 # Occupied blocks per task id
stats: Match current behaviour Small changes to the branch predictor and BTB caused stats changes throughout.
2016-04-09 18:13:40 +02:00
system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
stats: update references
2016-07-21 18:19:18 +02:00
system.l2c.tags.age_task_id_blocks_1023::4 348 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 625 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 2851 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 5174 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 53676 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.005325 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.952576 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 423034153 # Number of tag accesses
system.l2c.tags.data_accesses 423034153 # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.l2c.ReadReq_hits::cpu0.dtb.walker 166077 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 112464 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 54587 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 40813 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker 152672 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker 58108 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.dtb.walker 295679 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.itb.walker 104923 # number of ReadReq hits
system.l2c.ReadReq_hits::total 985323 # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks 7576706 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 7576706 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 15883082 # number of WritebackClean hits
system.l2c.WritebackClean_hits::total 15883082 # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data 3816 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 1201 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data 1641 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3.data 2839 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 9497 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu3.data 9 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 631099 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 192720 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data 285985 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3.data 475632 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 1585436 # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst 5464021 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst 1712423 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst 3852354 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu3.inst 4762402 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total 15791200 # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 2579009 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 769324 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data 1050953 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu3.data 1900864 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 6300150 # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data 286592 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data 87209 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu2.data 126708 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu3.data 229462 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total 729971 # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker 166077 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 112464 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 5464021 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 3210108 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 54587 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 40813 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 1712423 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 962044 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker 152672 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker 58108 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 3852354 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 1336938 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.dtb.walker 295679 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.itb.walker 104923 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst 4762402 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data 2376496 # number of demand (read+write) hits
system.l2c.demand_hits::total 24662109 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 166077 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 112464 # number of overall hits
system.l2c.overall_hits::cpu0.inst 5464021 # number of overall hits
system.l2c.overall_hits::cpu0.data 3210108 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 54587 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 40813 # number of overall hits
system.l2c.overall_hits::cpu1.inst 1712423 # number of overall hits
system.l2c.overall_hits::cpu1.data 962044 # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker 152672 # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker 58108 # number of overall hits
system.l2c.overall_hits::cpu2.inst 3852354 # number of overall hits
system.l2c.overall_hits::cpu2.data 1336938 # number of overall hits
system.l2c.overall_hits::cpu3.dtb.walker 295679 # number of overall hits
system.l2c.overall_hits::cpu3.itb.walker 104923 # number of overall hits
system.l2c.overall_hits::cpu3.inst 4762402 # number of overall hits
system.l2c.overall_hits::cpu3.data 2376496 # number of overall hits
system.l2c.overall_hits::total 24662109 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 1397 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 1376 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 307 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker 291 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker 530 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.itb.walker 481 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.dtb.walker 1161 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.itb.walker 997 # number of ReadReq misses
system.l2c.ReadReq_misses::total 6540 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 13913 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 4659 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 5652 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data 10300 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 34524 # number of UpgradeReq misses
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.l2c.SCUpgradeReq_misses::cpu3.data 2 # number of SCUpgradeReq misses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
stats: update references
2016-07-21 18:19:18 +02:00
system.l2c.ReadExReq_misses::cpu0.data 182222 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 51154 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 71437 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data 110233 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 415046 # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst 33022 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst 10176 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu2.inst 26498 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu3.inst 25154 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total 94850 # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 118847 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 31555 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2.data 39925 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu3.data 68999 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 259326 # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data 372466 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data 21824 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu2.data 29664 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu3.data 71909 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total 495863 # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker 1397 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 1376 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 33022 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 301069 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 307 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 291 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 10176 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 82709 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker 530 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.itb.walker 481 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst 26498 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 111362 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.dtb.walker 1161 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.itb.walker 997 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst 25154 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data 179232 # number of demand (read+write) misses
system.l2c.demand_misses::total 775762 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 1397 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 1376 # number of overall misses
system.l2c.overall_misses::cpu0.inst 33022 # number of overall misses
system.l2c.overall_misses::cpu0.data 301069 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 307 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 291 # number of overall misses
system.l2c.overall_misses::cpu1.inst 10176 # number of overall misses
system.l2c.overall_misses::cpu1.data 82709 # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker 530 # number of overall misses
system.l2c.overall_misses::cpu2.itb.walker 481 # number of overall misses
system.l2c.overall_misses::cpu2.inst 26498 # number of overall misses
system.l2c.overall_misses::cpu2.data 111362 # number of overall misses
system.l2c.overall_misses::cpu3.dtb.walker 1161 # number of overall misses
system.l2c.overall_misses::cpu3.itb.walker 997 # number of overall misses
system.l2c.overall_misses::cpu3.inst 25154 # number of overall misses
system.l2c.overall_misses::cpu3.data 179232 # number of overall misses
system.l2c.overall_misses::total 775762 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 26478000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker 25172000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 46384500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.itb.walker 43234500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.dtb.walker 105741000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.itb.walker 88236000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 335246000 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 69679500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data 85116000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3.data 155511500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 310307000 # number of UpgradeReq miss cycles
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.l2c.SCUpgradeReq_miss_latency::cpu3.data 82000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 82000 # number of SCUpgradeReq miss cycles
stats: update references
2016-07-21 18:19:18 +02:00
system.l2c.ReadExReq_miss_latency::cpu1.data 4186019500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data 5878341000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data 10990816000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 21055176500 # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 836780000 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu2.inst 2229220500 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu3.inst 2175672500 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total 5241673000 # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 2656686500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2.data 3377903000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu3.data 6243441000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 12278030500 # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu2.data 260500 # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu3.data 1010500 # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total 1271000 # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 26478000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 25172000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 836780000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 6842706000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker 46384500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.itb.walker 43234500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst 2229220500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data 9256244000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.dtb.walker 105741000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.itb.walker 88236000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst 2175672500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data 17234257000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 38910126000 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 26478000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 25172000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 836780000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 6842706000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker 46384500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.itb.walker 43234500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst 2229220500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data 9256244000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.dtb.walker 105741000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.itb.walker 88236000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst 2175672500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data 17234257000 # number of overall miss cycles
system.l2c.overall_miss_latency::total 38910126000 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 167474 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 113840 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 54894 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 41104 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker 153202 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker 58589 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.dtb.walker 296840 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.itb.walker 105920 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 991863 # number of ReadReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks 7576706 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 7576706 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks 15883082 # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total 15883082 # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 17729 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 5860 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data 7293 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data 13139 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 44021 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu3.data 11 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 11 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 813321 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 243874 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data 357422 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data 585865 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 2000482 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst 5497043 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst 1722599 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu2.inst 3878852 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu3.inst 4787556 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total 15886050 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 2697856 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 800879 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2.data 1090878 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu3.data 1969863 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 6559476 # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data 659058 # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data 109033 # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu2.data 156372 # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu3.data 301371 # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total 1225834 # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 167474 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 113840 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 5497043 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 3511177 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 54894 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 41104 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 1722599 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 1044753 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.dtb.walker 153202 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.itb.walker 58589 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst 3878852 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data 1448300 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.dtb.walker 296840 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.itb.walker 105920 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst 4787556 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data 2555728 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 25437871 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 167474 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 113840 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 5497043 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 3511177 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 54894 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 41104 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 1722599 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 1044753 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.dtb.walker 153202 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.itb.walker 58589 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst 3878852 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data 1448300 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.dtb.walker 296840 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.itb.walker 105920 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst 4787556 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data 2555728 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 25437871 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.008342 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.012087 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.005593 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.007080 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.003459 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.008210 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.dtb.walker 0.003911 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.itb.walker 0.009413 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.006594 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.784759 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.795051 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data 0.774990 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data 0.783926 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.784262 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu3.data 0.181818 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.181818 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.224047 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.209756 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 0.199867 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data 0.188154 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.207473 # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.006007 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.005907 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.006831 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.005254 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total 0.005971 # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.044052 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.039400 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.036599 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.035027 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.039535 # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data 0.565149 # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data 0.200160 # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu2.data 0.189701 # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu3.data 0.238606 # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total 0.404511 # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.008342 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.012087 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.006007 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.085746 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.005593 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.007080 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.005907 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.079166 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker 0.003459 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.itb.walker 0.008210 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst 0.006831 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data 0.076892 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.dtb.walker 0.003911 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.itb.walker 0.009413 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst 0.005254 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data 0.070130 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.030496 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.008342 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.012087 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.006007 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.085746 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.005593 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.007080 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.005907 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.079166 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker 0.003459 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.itb.walker 0.008210 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst 0.006831 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data 0.076892 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.dtb.walker 0.003911 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.itb.walker 0.009413 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst 0.005254 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data 0.070130 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.030496 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 86247.557003 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 86501.718213 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 87517.924528 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 89884.615385 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 91077.519380 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.itb.walker 88501.504514 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 51260.856269 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 14955.891822 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 15059.447983 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 15098.203883 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 8988.153169 # average UpgradeReq miss latency
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.l2c.SCUpgradeReq_avg_miss_latency::cpu3.data 41000 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 41000 # average SCUpgradeReq miss latency
stats: update references
2016-07-21 18:19:18 +02:00
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81831.714040 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 82287.064126 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 99705.315105 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 50729.742005 # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 82230.738994 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 84127.877576 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 86494.096366 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 55262.762256 # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 84192.251624 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 84606.211647 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 90485.963565 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 47345.929448 # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu2.data 8.781688 # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu3.data 14.052483 # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total 2.563208 # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 86247.557003 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 86501.718213 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 82230.738994 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 82732.302410 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 87517.924528 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.itb.walker 89884.615385 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 84127.877576 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 83118.514394 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 91077.519380 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.itb.walker 88501.504514 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst 86494.096366 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 96156.138413 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 50157.298244 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 86247.557003 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 86501.718213 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 82230.738994 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 82732.302410 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 87517.924528 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.itb.walker 89884.615385 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 84127.877576 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 83118.514394 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 91077.519380 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.itb.walker 88501.504514 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst 86494.096366 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 96156.138413 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 50157.298244 # average overall miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: update references
2016-07-21 18:19:18 +02:00
system.l2c.writebacks::writebacks 985217 # number of writebacks
system.l2c.writebacks::total 985217 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu3.dtb.walker 1 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3.itb.walker 10 # number of ReadReq MSHR hits
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 1 # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
stats: update references
2016-07-21 18:19:18 +02:00
system.l2c.ReadSharedReq_mshr_hits::cpu2.data 3 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu3.data 3 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.l2c.demand_mshr_hits::cpu2.inst 1 # number of demand (read+write) MSHR hits
stats: update references
2016-07-21 18:19:18 +02:00
system.l2c.demand_mshr_hits::cpu2.data 3 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.dtb.walker 1 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.itb.walker 10 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.data 3 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.l2c.overall_mshr_hits::cpu2.inst 1 # number of overall MSHR hits
stats: update references
2016-07-21 18:19:18 +02:00
system.l2c.overall_mshr_hits::cpu2.data 3 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.dtb.walker 1 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.itb.walker 10 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.data 3 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 307 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 291 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 530 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 481 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.dtb.walker 1160 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.itb.walker 987 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 3756 # number of ReadReq MSHR misses
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.l2c.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses
stats: update references
2016-07-21 18:19:18 +02:00
system.l2c.UpgradeReq_mshr_misses::cpu1.data 4659 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data 5652 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data 10300 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 20611 # number of UpgradeReq MSHR misses
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.l2c.SCUpgradeReq_mshr_misses::cpu3.data 2 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
stats: update references
2016-07-21 18:19:18 +02:00
system.l2c.ReadExReq_mshr_misses::cpu1.data 51154 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data 71437 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data 110233 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 232824 # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 10176 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 26497 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 25154 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total 61827 # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 31555 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2.data 39922 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu3.data 68996 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total 140473 # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data 21824 # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu2.data 29664 # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu3.data 71909 # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total 123397 # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 307 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker 291 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 10176 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 82709 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker 530 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.itb.walker 481 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst 26497 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data 111359 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.dtb.walker 1160 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.itb.walker 987 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst 25154 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data 179229 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 438880 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 307 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker 291 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 10176 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 82709 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker 530 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.itb.walker 481 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst 26497 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data 111359 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.dtb.walker 1160 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.itb.walker 987 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst 25154 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data 179229 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 438880 # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5165 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu2.data 4559 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu3.data 4594 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total 14318 # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 4682 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu2.data 4068 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu3.data 4289 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total 13039 # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 9847 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu2.data 8627 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu3.data 8883 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total 27357 # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 23408000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 22262000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 41084500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 38424500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.dtb.walker 94050502 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.itb.walker 77546001 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 296775503 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 88118500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 107329000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 195688500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 391136000 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu3.data 92500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 92500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3674479500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 5163970501 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 9888483007 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 18726933008 # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 735020000 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 1964182000 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 1924124516 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total 4623326516 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 2341129514 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 2978526506 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 5553259555 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 10872915575 # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 408885000 # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu2.data 577376500 # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu3.data 1457263250 # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total 2443524750 # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 23408000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 22262000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 735020000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 6015609014 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 41084500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 38424500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 1964182000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 8142497007 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker 94050502 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.itb.walker 77546001 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst 1924124516 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data 15441742562 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 34519950602 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 23408000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 22262000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 735020000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 6015609014 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 41084500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 38424500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst 1964182000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data 8142497007 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker 94050502 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.itb.walker 77546001 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst 1924124516 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data 15441742562 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 34519950602 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 873185500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 761989000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data 791442500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 2426617000 # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 873185500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 761989000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3.data 791442500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 2426617000 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.005593 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.007080 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.003459 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.008210 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker 0.003908 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker 0.009318 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.003787 # mshr miss rate for ReadReq accesses
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
stats: update references
2016-07-21 18:19:18 +02:00
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.795051 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.774990 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.783926 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.468208 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data 0.181818 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.181818 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.209756 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.199867 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.188154 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.116384 # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005907 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.006831 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.005254 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.003892 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.039400 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.036596 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.035026 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.021415 # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.200160 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data 0.189701 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data 0.238606 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total 0.100664 # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.005593 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.007080 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005907 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.079166 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003459 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.008210 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006831 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.076889 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003908 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.itb.walker 0.009318 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst 0.005254 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data 0.070128 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.017253 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.005593 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.007080 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005907 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.079166 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003459 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.008210 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.006831 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.076889 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003908 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.itb.walker 0.009318 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.005254 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data 0.070128 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.017253 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76247.557003 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76501.718213 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 77517.924528 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 79884.615385 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 81078.018966 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 78567.376900 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 79013.712194 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18913.608070 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 18989.561217 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 18998.883495 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18977.051089 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 46250 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 46250 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71831.714040 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 72287.057141 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 89705.287954 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 80433.859946 # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72230.738994 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 74128.467374 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 76493.778962 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 74778.438482 # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74192.030233 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 74608.649517 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 80486.688431 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 77402.173905 # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 18735.566349 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 19463.878776 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 20265.380550 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19802.140652 # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76247.557003 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76501.718213 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72230.738994 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72732.217945 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 77517.924528 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 79884.615385 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 74128.467374 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73119.343807 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 81078.018966 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 78567.376900 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 76493.778962 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 86156.495668 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 78654.645010 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76247.557003 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76501.718213 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72230.738994 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72732.217945 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 77517.924528 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 79884.615385 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 74128.467374 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73119.343807 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 81078.018966 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 78567.376900 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 76493.778962 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 86156.495668 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 78654.645010 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169058.180058 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 167139.504277 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 172277.427079 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 169480.164827 # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 88675.281812 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 88326.069317 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 89096.307554 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 88701.867895 # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests 2714288 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 1358609 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 3170 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
stats: update references
2016-07-21 18:19:18 +02:00
system.membus.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 76739 # Transaction distribution
system.membus.trans_dist::ReadResp 446283 # Transaction distribution
stats: Match current behaviour Small changes to the branch predictor and BTB caused stats changes throughout.
2016-04-09 18:13:40 +02:00
system.membus.trans_dist::WriteReq 33648 # Transaction distribution
system.membus.trans_dist::WriteResp 33648 # Transaction distribution
stats: update references
2016-07-21 18:19:18 +02:00
system.membus.trans_dist::WritebackDirty 1091848 # Transaction distribution
system.membus.trans_dist::CleanEvict 200785 # Transaction distribution
system.membus.trans_dist::UpgradeReq 35184 # Transaction distribution
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
stats: update references
2016-07-21 18:19:18 +02:00
system.membus.trans_dist::UpgradeResp 14271 # Transaction distribution
system.membus.trans_dist::ReadExReq 414448 # Transaction distribution
system.membus.trans_dist::ReadExResp 414448 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 369544 # Transaction distribution
system.membus.trans_dist::InvalidateReq 602468 # Transaction distribution
system.membus.trans_dist::InvalidateResp 435243 # Transaction distribution
stats: Match current behaviour Small changes to the branch predictor and BTB caused stats changes throughout.
2016-04-09 18:13:40 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122576 # Packet count per connected master and slave (bytes)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
stats: update references
2016-07-21 18:19:18 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6762 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3736384 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 3865780 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 302176 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 302176 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4167956 # Packet count per connected master and slave (bytes)
stats: Match current behaviour Small changes to the branch predictor and BTB caused stats changes throughout.
2016-04-09 18:13:40 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155706 # Cumulative packet size per connected master and slave (bytes)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
stats: update references
2016-07-21 18:19:18 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13524 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 112845536 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 113014898 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7362816 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7362816 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 120377714 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 603 # Total snoops (count)
system.membus.snoopTraffic 38528 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 2230474 # Request fanout histogram
system.membus.snoop_fanout::mean 0.016353 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.126827 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
stats: update references
2016-07-21 18:19:18 +02:00
system.membus.snoop_fanout::0 2194000 98.36% 98.36% # Request fanout histogram
system.membus.snoop_fanout::1 36474 1.64% 100.00% # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
stats: update references
2016-07-21 18:19:18 +02:00
system.membus.snoop_fanout::total 2230474 # Request fanout histogram
system.membus.reqLayer0.occupancy 45941500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: update references
2016-07-21 18:19:18 +02:00
system.membus.reqLayer2.occupancy 1601000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: update references
2016-07-21 18:19:18 +02:00
system.membus.reqLayer5.occupancy 3279160105 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
stats: update references
2016-07-21 18:19:18 +02:00
system.membus.respLayer2.occupancy 2368546008 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: update references
2016-07-21 18:19:18 +02:00
system.membus.respLayer3.occupancy 4606769 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: update references
2016-07-21 18:19:18 +02:00
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
stats: Update to reflect changes to RealView platform code
2015-12-04 01:19:05 +01:00
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
stats: update references
2016-07-21 18:19:18 +02:00
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
stats: update references
2016-07-21 18:19:18 +02:00
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
stats: Update to reflect changes to RealView platform code
2015-12-04 01:19:05 +01:00
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
stats: update references
2016-07-21 18:19:18 +02:00
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 52014816 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 26342736 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 3149 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 2216 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 2216 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
stats: update references
2016-07-21 18:19:18 +02:00
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 1497604 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 23943591 # Transaction distribution
stats: Match current behaviour Small changes to the branch predictor and BTB caused stats changes throughout.
2016-04-09 18:13:40 +02:00
system.toL2Bus.trans_dist::WriteReq 33648 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 33648 # Transaction distribution
stats: update references
2016-07-21 18:19:18 +02:00
system.toL2Bus.trans_dist::WritebackDirty 8020601 # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean 15885620 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 2314166 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 44021 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 44032 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 2000482 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 2000482 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 15886240 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 6559913 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 1231249 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp 1225834 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47744160 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29579701 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 811490 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1741524 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 79876875 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2033559380 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1032953822 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2918064 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6139128 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 3075570394 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 1503666 # Total snoops (count)
system.toL2Bus.snoopTraffic 65422752 # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples 38127714 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.016625 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.127861 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
stats: update references
2016-07-21 18:19:18 +02:00
system.toL2Bus.snoop_fanout::0 37493845 98.34% 98.34% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 633869 1.66% 100.00% # Request fanout histogram
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
stats: update references
2016-07-21 18:19:18 +02:00
system.toL2Bus.snoop_fanout::total 38127714 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 31242309916 # Layer occupancy (ticks)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
stats: update references
2016-07-21 18:19:18 +02:00
system.toL2Bus.snoopLayer0.occupancy 523765 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
stats: update references
2016-07-21 18:19:18 +02:00
system.toL2Bus.respLayer0.occupancy 15589083360 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: update references
2016-07-21 18:19:18 +02:00
system.toL2Bus.respLayer1.occupancy 7892971168 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: update references
2016-07-21 18:19:18 +02:00
system.toL2Bus.respLayer2.occupancy 287709740 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: update references
2016-07-21 18:19:18 +02:00
system.toL2Bus.respLayer3.occupancy 712482327 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.kern.inst.arm 0 # number of arm instructions executed
system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
---------- End Simulation Statistics ----------
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