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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt

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arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
---------- Begin Simulation Statistics ----------
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
sim_seconds 51.276903 # Number of seconds simulated
sim_ticks 51276903265000 # Number of ticks simulated
final_tick 51276903265000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
host_inst_rate 195122 # Simulator instruction rate (inst/s)
host_op_rate 229284 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 11700811305 # Simulator tick rate (ticks/s)
host_mem_usage 723460 # Number of bytes of host memory used
host_seconds 4382.34 # Real time elapsed on the host
sim_insts 855091424 # Number of instructions simulated
sim_ops 1004800608 # Number of ops (including micro ops) simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem.bytes_read::cpu0.dtb.walker 83904 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 91648 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 2486836 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 43860424 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 20800 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 20224 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 650944 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 6302784 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker 33152 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.itb.walker 28032 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 1597440 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 8824832 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.dtb.walker 64832 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.itb.walker 59456 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst 1836416 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data 15839168 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 414400 # Number of bytes read from this memory
system.physmem.bytes_read::total 82215292 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 2486836 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 650944 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 1597440 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst 1836416 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 6571636 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 69835456 # Number of bytes written to this memory
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem.bytes_written::total 69856036 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 1311 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1432 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 79264 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 685332 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 325 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 316 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 10171 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 98481 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker 518 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.itb.walker 438 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 24960 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 137888 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.dtb.walker 1013 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.itb.walker 929 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst 28694 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 247487 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6475 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1325034 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1091179 # Number of write requests responded to by this memory
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem.num_writes::total 1093752 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 1636 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 1787 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 48498 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 855364 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 406 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 394 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 12695 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 122917 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker 647 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.itb.walker 547 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 31153 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 172102 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.dtb.walker 1264 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.itb.walker 1160 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst 35814 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data 308895 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 8082 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1603359 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 48498 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 12695 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 31153 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst 35814 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 128160 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1361928 # Write bandwidth from this memory (bytes/s)
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem.bw_write::total 1362329 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1361928 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 1636 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 1787 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 48498 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 855765 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 406 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 394 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 12695 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 122917 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker 647 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.itb.walker 547 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 31153 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 172102 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.dtb.walker 1264 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.itb.walker 1160 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst 35814 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data 308895 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 8082 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2965689 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 552891 # Number of read requests accepted
system.physmem.writeReqs 477788 # Number of write requests accepted
system.physmem.readBursts 552891 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 477788 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 35353984 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 31040 # Total number of bytes read from write queue
system.physmem.bytesWritten 30577024 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 35385024 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 30578432 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 485 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 65706 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 34049 # Per bank write bursts
system.physmem.perBankRdBursts::1 38611 # Per bank write bursts
system.physmem.perBankRdBursts::2 36089 # Per bank write bursts
system.physmem.perBankRdBursts::3 33688 # Per bank write bursts
system.physmem.perBankRdBursts::4 32444 # Per bank write bursts
system.physmem.perBankRdBursts::5 38213 # Per bank write bursts
system.physmem.perBankRdBursts::6 33143 # Per bank write bursts
system.physmem.perBankRdBursts::7 35180 # Per bank write bursts
system.physmem.perBankRdBursts::8 30999 # Per bank write bursts
system.physmem.perBankRdBursts::9 38487 # Per bank write bursts
system.physmem.perBankRdBursts::10 32534 # Per bank write bursts
system.physmem.perBankRdBursts::11 34124 # Per bank write bursts
system.physmem.perBankRdBursts::12 34391 # Per bank write bursts
system.physmem.perBankRdBursts::13 36689 # Per bank write bursts
system.physmem.perBankRdBursts::14 30748 # Per bank write bursts
system.physmem.perBankRdBursts::15 33017 # Per bank write bursts
system.physmem.perBankWrBursts::0 28228 # Per bank write bursts
system.physmem.perBankWrBursts::1 31813 # Per bank write bursts
system.physmem.perBankWrBursts::2 30334 # Per bank write bursts
system.physmem.perBankWrBursts::3 30276 # Per bank write bursts
system.physmem.perBankWrBursts::4 29074 # Per bank write bursts
system.physmem.perBankWrBursts::5 32329 # Per bank write bursts
system.physmem.perBankWrBursts::6 29378 # Per bank write bursts
system.physmem.perBankWrBursts::7 31367 # Per bank write bursts
system.physmem.perBankWrBursts::8 28134 # Per bank write bursts
system.physmem.perBankWrBursts::9 32950 # Per bank write bursts
system.physmem.perBankWrBursts::10 28173 # Per bank write bursts
system.physmem.perBankWrBursts::11 29809 # Per bank write bursts
system.physmem.perBankWrBursts::12 29393 # Per bank write bursts
system.physmem.perBankWrBursts::13 31102 # Per bank write bursts
system.physmem.perBankWrBursts::14 26687 # Per bank write bursts
system.physmem.perBankWrBursts::15 28719 # Per bank write bursts
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem.numWrRetry 6 # Number of times write queue was full causing retry
system.physmem.totGap 51275902957500 # Total gap between requests
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem.readPktSize::6 552891 # Read request sizes (log2)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem.writePktSize::6 477788 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 390834 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 101245 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 36261 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 22580 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 241 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 135 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 124 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 154 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 226 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 255 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 116 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 39 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 34 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 29 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 28 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 28 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 25 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 25 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 16 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 11 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem.wrQLenPdf::0 584 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 569 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 569 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 570 # What write queue length does an incoming req see
stats: Update switcheroo reference stats The Minor draining fixes affect perturb the timing slightly since it affects how the simulator is drained. Update reference statistics to reflect this expected change.
2015-07-31 18:04:59 +02:00
system.physmem.wrQLenPdf::4 568 # What write queue length does an incoming req see
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem.wrQLenPdf::5 567 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 567 # What write queue length does an incoming req see
stats: Update switcheroo reference stats The Minor draining fixes affect perturb the timing slightly since it affects how the simulator is drained. Update reference statistics to reflect this expected change.
2015-07-31 18:04:59 +02:00
system.physmem.wrQLenPdf::7 563 # What write queue length does an incoming req see
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem.wrQLenPdf::8 560 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 559 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 558 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 561 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 554 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 552 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 550 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 7763 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 8554 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 19132 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 23245 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 26278 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 27645 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 27593 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 28722 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 29357 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 30518 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 30179 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 30394 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 29233 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 29969 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 32125 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 28250 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 28349 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 27090 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 471 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 311 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 390 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 265 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 248 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 234 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 249 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 221 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 196 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 156 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 165 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 174 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 154 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 201 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 164 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 136 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 174 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 107 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 192 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 123 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 93 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 93 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 74 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 64 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 50 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 26 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 23 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 274210 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 240.439605 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 144.938897 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 282.109659 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 125716 45.85% 45.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 68438 24.96% 70.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 25021 9.12% 79.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 12508 4.56% 84.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 9258 3.38% 87.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 5639 2.06% 89.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 4828 1.76% 91.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 3908 1.43% 93.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 18894 6.89% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 274210 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 26911 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 20.526067 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 11.794562 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-31 24375 90.58% 90.58% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::32-63 2332 8.67% 99.24% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::64-95 174 0.65% 99.89% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::96-127 18 0.07% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::128-159 4 0.01% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::160-191 2 0.01% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::192-223 2 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::224-255 1 0.00% 99.99% # Reads before turning the bus around for writes
stats: Update switcheroo reference stats The Minor draining fixes affect perturb the timing slightly since it affects how the simulator is drained. Update reference statistics to reflect this expected change.
2015-07-31 18:04:59 +02:00
system.physmem.rdPerTurnAround::256-287 1 0.00% 99.99% # Reads before turning the bus around for writes
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem.rdPerTurnAround::544-575 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::768-799 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 26911 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 26911 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.753558 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.172751 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 7.257743 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3 17 0.06% 0.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7 9 0.03% 0.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11 13 0.05% 0.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15 46 0.17% 0.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 25176 93.55% 93.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 431 1.60% 95.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 320 1.19% 96.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 165 0.61% 97.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 117 0.43% 97.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 198 0.74% 98.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 59 0.22% 98.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 19 0.07% 98.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 21 0.08% 98.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 16 0.06% 98.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 22 0.08% 98.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 10 0.04% 98.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 188 0.70% 99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 14 0.05% 99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 18 0.07% 99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 10 0.04% 99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 3 0.01% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 4 0.01% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 4 0.01% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 2 0.01% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 3 0.01% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 2 0.01% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.00% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 13 0.05% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 1 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151 2 0.01% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 2 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-227 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 26911 # Writes before turning the bus around for reads
system.physmem.totQLat 11450608424 # Total ticks spent queuing
system.physmem.totMemAccLat 21808220924 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2762030000 # Total ticks spent in databus transfers
system.physmem.avgQLat 20728.61 # Average queueing delay per DRAM burst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem.avgMemAccLat 39478.61 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 0.69 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.60 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 0.69 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.60 # Average system write bandwidth in MiByte/s
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.01 # Data bus utilization in percentage
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem.avgWrQLen 9.42 # Average write queue length when enqueuing
system.physmem.readRowHits 422970 # Number of row buffer hits during reads
system.physmem.writeRowHits 332991 # Number of row buffer hits during writes
system.physmem.readRowHitRate 76.57 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 69.69 # Row buffer hit rate for writes
system.physmem.avgGap 49749633.94 # Average gap between requests
system.physmem.pageHitRate 73.38 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 1067305680 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 580820625 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 2194982400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 1573337520 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3310526753040 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1179597405240 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 30106177853250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 34601718457755 # Total energy per rank (pJ)
system.physmem_0.averagePower 666.680244 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 48870107005920 # Time in different power states
system.physmem_0.memoryStateTime::REF 1692498340000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem_0.memoryStateTime::ACT 123346652830 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem_1.actEnergy 1005699240 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 547226625 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 2113714200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 1522586160 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3310526753040 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1176042513600 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 29757652392000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 34249410884865 # Total energy per rank (pJ)
system.physmem_1.averagePower 667.428862 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 48875263841452 # Time in different power states
system.physmem_1.memoryStateTime::REF 1692498340000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem_1.memoryStateTime::ACT 118168635298 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.realview.nvmem.bytes_read::cpu2.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 196 # Number of bytes read from this memory
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.realview.nvmem.bytes_inst_read::cpu2.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.realview.nvmem.num_reads::cpu2.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.realview.nvmem.bw_read::cpu2.inst 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.realview.nvmem.bw_inst_read::cpu2.inst 1 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.realview.nvmem.bw_total::cpu2.inst 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dtb.walker.walks 90619 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 90619 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walkWaitTime::samples 90619 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0 90619 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 90619 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walksPending::samples 391820506288 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 1.505623 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 -198113446712 -50.56% -50.56% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1 589933953000 150.56% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 391820506288 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 66457 84.78% 84.78% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M 11934 15.22% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 78391 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 90619 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 90619 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 78391 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 78391 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 169010 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dtb.read_hits 64357240 # DTB read hits
system.cpu0.dtb.read_misses 68494 # DTB read misses
system.cpu0.dtb.write_hits 58282336 # DTB write hits
system.cpu0.dtb.write_misses 22125 # DTB write misses
system.cpu0.dtb.flush_tlb 1188 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dtb.flush_tlb_mva_asid 16028 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 418 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 42200 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dtb.prefetch_faults 2748 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dtb.perms_faults 7647 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 64425734 # DTB read accesses
system.cpu0.dtb.write_accesses 58304461 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dtb.hits 122639576 # DTB hits
system.cpu0.dtb.misses 90619 # DTB misses
system.cpu0.dtb.accesses 122730195 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.itb.walker.walks 53743 # Table walker walks requested
system.cpu0.itb.walker.walksLong 53743 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walkWaitTime::samples 53743 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0 53743 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 53743 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walksPending::samples 391820506288 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 1.505732 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 -198156351712 -50.57% -50.57% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 589976858000 150.57% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 391820506288 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 46842 94.98% 94.98% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M 2476 5.02% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 49318 # Table walker page sizes translated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 53743 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 53743 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 49318 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 49318 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 103061 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 342266306 # ITB inst hits
system.cpu0.itb.inst_misses 53743 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.itb.flush_tlb 1188 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.itb.flush_tlb_mva_asid 16028 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 418 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 29888 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.itb.inst_accesses 342320049 # ITB inst accesses
system.cpu0.itb.hits 342266306 # DTB hits
system.cpu0.itb.misses 53743 # DTB misses
system.cpu0.itb.accesses 342320049 # DTB accesses
system.cpu0.numCycles 413032183 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.committedInsts 342117440 # Number of instructions committed
system.cpu0.committedOps 402438329 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 369654139 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 360090 # Number of float alu accesses
system.cpu0.num_func_calls 20604842 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 52004192 # number of instructions that are conditional controls
system.cpu0.num_int_insts 369654139 # number of integer instructions
system.cpu0.num_fp_insts 360090 # number of float instructions
system.cpu0.num_int_register_reads 540778381 # number of times the integer registers were read
system.cpu0.num_int_register_writes 293614649 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 575012 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 316800 # number of times the floating registers were written
system.cpu0.num_cc_register_reads 89609832 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 89403726 # number of times the CC registers were written
system.cpu0.num_mem_refs 122714331 # number of memory refs
system.cpu0.num_load_insts 64415463 # Number of load instructions
system.cpu0.num_store_insts 58298868 # Number of store instructions
system.cpu0.num_idle_cycles 403076556.915137 # Number of idle cycles
system.cpu0.num_busy_cycles 9955626.084863 # Number of busy cycles
system.cpu0.not_idle_fraction 0.024104 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.975896 # Percentage of idle cycles
system.cpu0.Branches 76323262 # Number of branches fetched
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.op_class::IntAlu 278992555 69.28% 69.28% # Class of executed instruction
system.cpu0.op_class::IntMult 883395 0.22% 69.50% # Class of executed instruction
system.cpu0.op_class::IntDiv 42520 0.01% 69.51% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 1 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 46836 0.01% 69.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 69.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.53% # Class of executed instruction
system.cpu0.op_class::MemRead 64415463 16.00% 85.52% # Class of executed instruction
system.cpu0.op_class::MemWrite 58298868 14.48% 100.00% # Class of executed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.op_class::total 402679638 # Class of executed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.kern.inst.quiesce 19432 # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements 9760108 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.999717 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 295125268 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 9760620 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 30.236324 # Average number of references to valid blocks.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 495.144128 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 6.012482 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data 7.237282 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu3.data 3.605825 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.967078 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.011743 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.014135 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu3.data 0.007043 # Average percentage of cache occupancy
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update switcheroo reference stats The Minor draining fixes affect perturb the timing slightly since it affects how the simulator is drained. Update reference statistics to reflect this expected change.
2015-07-31 18:04:59 +02:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dcache.tags.tag_accesses 1250683612 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 1250683612 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 60097226 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 19336059 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 26622949 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu3.data 45749144 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 151805378 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 55100568 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 17719150 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data 23754745 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu3.data 38783251 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 135357714 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 162930 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 47086 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data 80309 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu3.data 113101 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 403426 # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 133083 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu1.data 44114 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu2.data 53448 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu3.data 99458 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total 330103 # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1446448 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 433739 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 576979 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 973119 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 3430285 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1540849 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 470550 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data 624581 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu3.data 1118875 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 3754855 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 115197794 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 37055209 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data 50377694 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu3.data 84532395 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 287163092 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 115360724 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 37102295 # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data 50458003 # number of overall hits
system.cpu0.dcache.overall_hits::cpu3.data 84645496 # number of overall hits
system.cpu0.dcache.overall_hits::total 287566518 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 2087825 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 630392 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data 947372 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu3.data 3467801 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 7133390 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 834937 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 250601 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data 634589 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu3.data 3517753 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 5237880 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 509202 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 138531 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data 204192 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu3.data 336844 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 1188769 # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 666802 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu1.data 108292 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu2.data 153513 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu3.data 298278 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total 1226885 # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 95086 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 37006 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 47829 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 182134 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 362055 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu3.data 3 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 2922762 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 880993 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data 1581961 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu3.data 6985554 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 12371270 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 3431964 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 1019524 # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data 1786153 # number of overall misses
system.cpu0.dcache.overall_misses::cpu3.data 7322398 # number of overall misses
system.cpu0.dcache.overall_misses::total 13560039 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 9653717000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 15011038000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 51609854500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 76274609500 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 6907191500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 17274882500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 96691175707 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 120873249707 # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 2640856500 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data 4379642000 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data 10567870242 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total 17588368742 # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 538982000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 669036000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 2261145500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 3469163500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 130000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 130000 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 16560908500 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data 32285920500 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu3.data 148301030207 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 197147859207 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 16560908500 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data 32285920500 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu3.data 148301030207 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 197147859207 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 62185051 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 19966451 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data 27570321 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu3.data 49216945 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 158938768 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 55935505 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 17969751 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 24389334 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu3.data 42301004 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 140595594 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 672132 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 185617 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 284501 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu3.data 449945 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 1592195 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 799885 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 152406 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu2.data 206961 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu3.data 397736 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total 1556988 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1541534 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 470745 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 624808 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data 1155253 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 3792340 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1540849 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 470550 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 624581 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 1118878 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 3754858 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 118120556 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 37936202 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data 51959655 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu3.data 91517949 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 299534362 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 118792688 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 38121819 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 52244156 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu3.data 91967894 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 301126557 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033574 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.031573 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.034362 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.070459 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.044881 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.014927 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.013946 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.026019 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.083160 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.037255 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.757592 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.746327 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.717720 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.748634 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.746623 # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.833622 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.710549 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data 0.741748 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data 0.749940 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.787986 # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.061683 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078612 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.076550 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.157657 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.095470 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000003 # miss rate for StoreCondReq accesses
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024744 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.023223 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.030446 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu3.data 0.076330 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.041302 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028890 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.026744 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.034189 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu3.data 0.079619 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.045031 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15313.831711 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15844.924697 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 14882.588274 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 10692.617325 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 27562.505736 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 27222.158752 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 27486.630161 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 23076.750461 # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24386.441288 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 28529.453532 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 35429.600044 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 14335.792468 # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14564.719235 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13988.082544 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 12414.735854 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9581.868777 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 43333.333333 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 43333.333333 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18798.002368 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 20408.796740 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 21229.673438 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 15935.943457 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16243.765228 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 18075.674648 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 20253.068763 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 14538.885855 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 12171442 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 9970 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 893773 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 243 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.618046 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 41.028807 # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dcache.writebacks::writebacks 7547308 # number of writebacks
system.cpu0.dcache.writebacks::total 7547308 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3607 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 105383 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 1896936 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 2005926 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 2163 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 278391 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 2919937 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 3200491 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data 20 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data 2253 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total 2273 # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 8701 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 10746 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 111791 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 131238 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 5770 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data 383774 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu3.data 4816873 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 5206417 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 5770 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data 383774 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu3.data 4816873 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 5206417 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 626785 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 841989 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 1570865 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 3039639 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 248438 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 356198 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 597816 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 1202452 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 138310 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 204087 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 332211 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 674608 # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 108292 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data 153493 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data 296025 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total 557810 # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 28305 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 37083 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 70343 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 135731 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 3 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 875223 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data 1198187 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu3.data 2168681 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 4242091 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 1013533 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data 1402274 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu3.data 2500892 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 4916699 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 5947 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 4621 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 4770 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 15338 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 5383 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 4193 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 4437 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 14013 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 11330 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 8814 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 9207 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 29351 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 8948924500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 12450643000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 23749051500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 45148619000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6583355500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 9198762000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 17328942473 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 33111059973 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 2410482500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 3025654000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 5045013000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 10481149500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 2532564500 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data 4225854500 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data 10181517242 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 16939936242 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 374149000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 474867500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 928593000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1777609500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 127000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 127000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 15532280000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 21649405000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 41077993973 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 78259678973 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 17942762500 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 24675059000 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 46123006973 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 88740828473 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1021104000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 786468000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 830220000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2637792000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 943050500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 717793000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 802384000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2463227500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1964154500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 1504261000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 1632604000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5101019500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.031392 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.030540 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.031917 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.019125 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013825 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.014605 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.014132 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008553 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.745136 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.717351 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.738337 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.423697 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.710549 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data 0.741652 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data 0.744275 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.358262 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060128 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.059351 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.060890 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.035791 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000003 # mshr miss rate for StoreCondReq accesses
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.023071 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023060 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.023697 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.014162 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026587 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.026841 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.027193 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.016328 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14277.502652 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14787.180118 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15118.454800 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14853.283235 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26498.987675 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25824.855839 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 28987.083773 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27536.284170 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17428.114381 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14825.314694 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15186.170837 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15536.651655 # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23386.441288 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 27531.252240 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 34394.112801 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 30368.649257 # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13218.477301 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12805.530836 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 13200.929730 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13096.562318 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 42333.333333 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 42333.333333 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17746.654281 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18068.469279 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 18941.464408 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18448.373449 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17703.185293 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17596.460464 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 18442.622462 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18048.863368 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171700.689423 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 170194.330232 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 174050.314465 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171977.572043 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 175190.507152 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 171188.409254 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 180839.305837 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 175781.595661 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 173358.737864 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 170667.233946 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 177322.037580 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 173793.720827 # average overall mshr uncacheable latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.icache.tags.replacements 15787116 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.974790 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 559161583 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 15787628 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 35.417707 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 10320304500 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 471.137124 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 3.371284 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst 26.901455 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu3.inst 10.564927 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.920190 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.006585 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.052542 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu3.inst 0.020635 # Average percentage of cache occupancy
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu0.icache.tags.occ_percent::total 0.999951 # Average percentage of cache occupancy
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.icache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id
stats: Update switcheroo reference stats The Minor draining fixes affect perturb the timing slightly since it affects how the simulator is drained. Update reference statistics to reflect this expected change.
2015-07-31 18:04:59 +02:00
system.cpu0.icache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.icache.tags.tag_accesses 591095135 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 591095135 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 336798799 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 107446320 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 66160424 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu3.inst 48756040 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 559161583 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 336798799 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 107446320 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 66160424 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu3.inst 48756040 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 559161583 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 336798799 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 107446320 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 66160424 # number of overall hits
system.cpu0.icache.overall_hits::cpu3.inst 48756040 # number of overall hits
system.cpu0.icache.overall_hits::total 559161583 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 5516825 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 1724189 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 3891179 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu3.inst 5013652 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 16145845 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 5516825 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 1724189 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst 3891179 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu3.inst 5013652 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 16145845 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 5516825 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 1724189 # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst 3891179 # number of overall misses
system.cpu0.icache.overall_misses::cpu3.inst 5013652 # number of overall misses
system.cpu0.icache.overall_misses::total 16145845 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 23134479500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 52416586500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu3.inst 65622518853 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 141173584853 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 23134479500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst 52416586500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu3.inst 65622518853 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 141173584853 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 23134479500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst 52416586500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu3.inst 65622518853 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 141173584853 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 342315624 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 109170509 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 70051603 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu3.inst 53769692 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 575307428 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 342315624 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 109170509 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 70051603 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu3.inst 53769692 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 575307428 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 342315624 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 109170509 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 70051603 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu3.inst 53769692 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 575307428 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016116 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015794 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.055547 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu3.inst 0.093243 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.028065 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016116 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015794 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.055547 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu3.inst 0.093243 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.028065 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016116 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015794 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.055547 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu3.inst 0.093243 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.028065 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13417.600681 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13470.618160 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13088.766203 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 8743.647970 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13417.600681 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13470.618160 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13088.766203 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 8743.647970 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13417.600681 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13470.618160 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13088.766203 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 8743.647970 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 43982 # number of cycles access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.icache.blocked::no_mshrs 3227 # number of cycles access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.629377 # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 358138 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 358138 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu3.inst 358138 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 358138 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu3.inst 358138 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 358138 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 1724189 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 3891179 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst 4655514 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 10270882 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 1724189 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst 3891179 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu3.inst 4655514 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 10270882 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 1724189 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst 3891179 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu3.inst 4655514 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 10270882 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 21410290500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 48525407500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 58117116880 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 128052814880 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 21410290500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 48525407500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 58117116880 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 128052814880 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 21410290500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 48525407500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 58117116880 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 128052814880 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015794 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.055547 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.086582 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017853 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015794 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.055547 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.086582 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.017853 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015794 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.055547 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.086582 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.017853 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12417.600681 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12470.618160 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12483.501689 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12467.557789 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12417.600681 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12470.618160 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12483.501689 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12467.557789 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12417.600681 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12470.618160 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12483.501689 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12467.557789 # average overall mshr miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.dtb.walker.walks 32157 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 32157 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4670 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 23647 # Level at which table walker walks with long descriptors terminate
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu1.dtb.walker.walksSquashedBefore 5 # Table walks squashed before starting
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.dtb.walker.walkWaitTime::samples 32152 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0 32152 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 32152 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 28322 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 24465.680390 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 21462.893478 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 12624.124225 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-32767 18193 64.24% 64.24% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-65535 9967 35.19% 99.43% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-98303 97 0.34% 99.77% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-131071 42 0.15% 99.92% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-163839 3 0.01% 99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::163840-196607 9 0.03% 99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-229375 2 0.01% 99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::229376-262143 3 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-294911 2 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::294912-327679 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::360448-393215 2 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 28322 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples -3003382012 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean 1.339073 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 1018364500 -33.91% -33.91% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1 -4021746512 133.91% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total -3003382012 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 23647 83.51% 83.51% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M 4670 16.49% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 28317 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 32157 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 32157 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 28317 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 28317 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 60474 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.dtb.read_hits 20628760 # DTB read hits
system.cpu1.dtb.read_misses 24754 # DTB read misses
system.cpu1.dtb.write_hits 18600606 # DTB write hits
system.cpu1.dtb.write_misses 7403 # DTB write misses
system.cpu1.dtb.flush_tlb 1180 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.dtb.flush_tlb_mva_asid 5222 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 123 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 17774 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.dtb.prefetch_faults 948 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.dtb.perms_faults 2501 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 20653514 # DTB read accesses
system.cpu1.dtb.write_accesses 18608009 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.dtb.hits 39229366 # DTB hits
system.cpu1.dtb.misses 32157 # DTB misses
system.cpu1.dtb.accesses 39261523 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.itb.walker.walks 20715 # Table walker walks requested
system.cpu1.itb.walker.walksLong 20715 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 930 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3 18416 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples 20715 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0 20715 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 20715 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 19346 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 27414.659361 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 24764.281979 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 13419.535342 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-32767 9905 51.20% 51.20% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-65535 9256 47.84% 99.04% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-98303 65 0.34% 99.38% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::98304-131071 99 0.51% 99.89% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-163839 1 0.01% 99.90% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::163840-196607 7 0.04% 99.93% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-229375 2 0.01% 99.94% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::229376-262143 4 0.02% 99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-294911 4 0.02% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::294912-327679 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-360447 2 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 19346 # Table walker service (enqueue to completion) latency
stats: Update switcheroo reference stats The Minor draining fixes affect perturb the timing slightly since it affects how the simulator is drained. Update reference statistics to reflect this expected change.
2015-07-31 18:04:59 +02:00
system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.itb.walker.walkPageSizes::4K 18416 95.19% 95.19% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M 930 4.81% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 19346 # Table walker page sizes translated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 20715 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 20715 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 19346 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 19346 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 40061 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 109170509 # ITB inst hits
system.cpu1.itb.inst_misses 20715 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.itb.flush_tlb 1180 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.itb.flush_tlb_mva_asid 5222 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 123 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 13293 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.itb.inst_accesses 109191224 # ITB inst accesses
system.cpu1.itb.hits 109170509 # DTB hits
system.cpu1.itb.misses 20715 # DTB misses
system.cpu1.itb.accesses 109191224 # DTB accesses
system.cpu1.numCycles 1180099422 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.committedInsts 109095321 # Number of instructions committed
system.cpu1.committedOps 128047126 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 117680197 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 117915 # Number of float alu accesses
system.cpu1.num_func_calls 6450893 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 16554916 # number of instructions that are conditional controls
system.cpu1.num_int_insts 117680197 # number of integer instructions
system.cpu1.num_fp_insts 117915 # number of float instructions
system.cpu1.num_int_register_reads 169047923 # number of times the integer registers were read
system.cpu1.num_int_register_writes 93200008 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 191658 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 96888 # number of times the floating registers were written
system.cpu1.num_cc_register_reads 28194465 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 28098874 # number of times the CC registers were written
system.cpu1.num_mem_refs 39226015 # number of memory refs
system.cpu1.num_load_insts 20627300 # Number of load instructions
system.cpu1.num_store_insts 18598715 # Number of store instructions
system.cpu1.num_idle_cycles 1154150302.947621 # Number of idle cycles
system.cpu1.num_busy_cycles 25949119.052379 # Number of busy cycles
system.cpu1.not_idle_fraction 0.021989 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.978011 # Percentage of idle cycles
system.cpu1.Branches 24363890 # Number of branches fetched
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.op_class::IntAlu 88601672 69.15% 69.15% # Class of executed instruction
system.cpu1.op_class::IntMult 269277 0.21% 69.36% # Class of executed instruction
system.cpu1.op_class::IntDiv 11730 0.01% 69.37% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 69.37% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 69.37% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 69.37% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 69.37% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 69.37% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 69.37% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 69.37% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 69.37% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 69.37% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 69.37% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 69.37% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 69.37% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 69.37% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 69.37% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 69.37% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.37% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 69.37% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.37% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.37% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.37% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 20 0.00% 69.37% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.37% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 13579 0.01% 69.38% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 69.38% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.38% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.38% # Class of executed instruction
system.cpu1.op_class::MemRead 20627300 16.10% 85.48% # Class of executed instruction
system.cpu1.op_class::MemWrite 18598715 14.52% 100.00% # Class of executed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.op_class::total 128122314 # Class of executed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu2.branchPred.lookups 40464780 # Number of BP lookups
system.cpu2.branchPred.condPredicted 28154198 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 1978898 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 29418306 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 20974527 # Number of BTB hits
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu2.branchPred.BTBHitPct 71.297535 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 4946229 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 331686 # Number of incorrect RAS predictions.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu2.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu2.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu2.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu2.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu2.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu2.dtb.walker.walks 93767 # Table walker walks requested
system.cpu2.dtb.walker.walksLong 93767 # Table walker walks initiated with long descriptors
system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 6983 # Level at which table walker walks with long descriptors terminate
system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 29518 # Level at which table walker walks with long descriptors terminate
system.cpu2.dtb.walker.walkWaitTime::samples 93767 # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::0 93767 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::total 93767 # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkCompletionTime::samples 36501 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::mean 24922.262404 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::gmean 22135.996220 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::stdev 12304.178118 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::0-32767 23409 64.13% 64.13% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::32768-65535 12906 35.36% 99.49% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::65536-98303 87 0.24% 99.73% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::98304-131071 74 0.20% 99.93% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::131072-163839 1 0.00% 99.93% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::163840-196607 7 0.02% 99.95% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::196608-229375 3 0.01% 99.96% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::229376-262143 4 0.01% 99.97% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::262144-294911 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::294912-327679 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::327680-360447 2 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::360448-393215 2 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::total 36501 # Table walker service (enqueue to completion) latency
stats: Update switcheroo reference stats The Minor draining fixes affect perturb the timing slightly since it affects how the simulator is drained. Update reference statistics to reflect this expected change.
2015-07-31 18:04:59 +02:00
system.cpu2.dtb.walker.walksPending::samples 2000228500 # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::0 2000228500 100.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::total 2000228500 # Table walker pending requests distribution
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu2.dtb.walker.walkPageSizes::4K 29518 80.87% 80.87% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::2M 6983 19.13% 100.00% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::total 36501 # Table walker page sizes translated
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 93767 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 93767 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 36501 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 36501 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin::total 130268 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu2.dtb.read_hits 28765084 # DTB read hits
system.cpu2.dtb.read_misses 78268 # DTB read misses
system.cpu2.dtb.write_hits 25322239 # DTB write hits
system.cpu2.dtb.write_misses 15499 # DTB write misses
system.cpu2.dtb.flush_tlb 1180 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu2.dtb.flush_tlb_mva_asid 6709 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid 189 # Number of times TLB was flushed by ASID
system.cpu2.dtb.flush_entries 22277 # Number of entries that have been flushed from TLB
system.cpu2.dtb.align_faults 76 # Number of TLB faults due to alignment restrictions
system.cpu2.dtb.prefetch_faults 2199 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu2.dtb.perms_faults 3811 # Number of TLB faults due to permissions restrictions
system.cpu2.dtb.read_accesses 28843352 # DTB read accesses
system.cpu2.dtb.write_accesses 25337738 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu2.dtb.hits 54087323 # DTB hits
system.cpu2.dtb.misses 93767 # DTB misses
system.cpu2.dtb.accesses 54181090 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu2.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu2.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu2.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu2.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu2.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu2.itb.walker.walks 27119 # Table walker walks requested
system.cpu2.itb.walker.walksLong 27119 # Table walker walks initiated with long descriptors
system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1817 # Level at which table walker walks with long descriptors terminate
system.cpu2.itb.walker.walksLongTerminationLevel::Level3 22640 # Level at which table walker walks with long descriptors terminate
system.cpu2.itb.walker.walkWaitTime::samples 27119 # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::0 27119 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::total 27119 # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkCompletionTime::samples 24457 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::mean 28043.607147 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::gmean 25574.105463 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::stdev 12475.611214 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::0-32767 11681 47.76% 47.76% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::32768-65535 12550 51.31% 99.08% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::65536-98303 85 0.35% 99.42% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::98304-131071 123 0.50% 99.93% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::131072-163839 1 0.00% 99.93% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::163840-196607 7 0.03% 99.96% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::196608-229375 6 0.02% 99.98% # Table walker service (enqueue to completion) latency
stats: Update switcheroo reference stats The Minor draining fixes affect perturb the timing slightly since it affects how the simulator is drained. Update reference statistics to reflect this expected change.
2015-07-31 18:04:59 +02:00
system.cpu2.itb.walker.walkCompletionTime::262144-294911 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::294912-327679 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu2.itb.walker.walkCompletionTime::327680-360447 2 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::total 24457 # Table walker service (enqueue to completion) latency
stats: Update switcheroo reference stats The Minor draining fixes affect perturb the timing slightly since it affects how the simulator is drained. Update reference statistics to reflect this expected change.
2015-07-31 18:04:59 +02:00
system.cpu2.itb.walker.walksPending::samples 2000202500 # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::0 2000202500 100.00% 100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::total 2000202500 # Table walker pending requests distribution
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu2.itb.walker.walkPageSizes::4K 22640 92.57% 92.57% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::2M 1817 7.43% 100.00% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::total 24457 # Table walker page sizes translated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 27119 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Requested::total 27119 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 24457 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::total 24457 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin::total 51576 # Table walker requests started/completed, data/inst
system.cpu2.itb.inst_hits 70111472 # ITB inst hits
system.cpu2.itb.inst_misses 27119 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu2.itb.flush_tlb 1180 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu2.itb.flush_tlb_mva_asid 6709 # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid 189 # Number of times TLB was flushed by ASID
system.cpu2.itb.flush_entries 16886 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu2.itb.perms_faults 56888 # Number of TLB faults due to permissions restrictions
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_accesses 0 # DTB write accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu2.itb.inst_accesses 70138591 # ITB inst accesses
system.cpu2.itb.hits 70111472 # DTB hits
system.cpu2.itb.misses 27119 # DTB misses
system.cpu2.itb.accesses 70138591 # DTB accesses
system.cpu2.numCycles 6662793368 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu2.committedInsts 148437005 # Number of instructions committed
system.cpu2.committedOps 174093973 # Number of ops (including micro ops) committed
system.cpu2.discardedOps 14341019 # Number of ops (including micro ops) which were discarded before commit
system.cpu2.numFetchSuspends 1575 # Number of times Execute suspended instruction fetching
system.cpu2.quiesceCycles 95890004718 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.cpi 44.886337 # CPI: cycles per instruction
system.cpu2.ipc 0.022278 # IPC: instructions per cycle
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu2.tickCycles 276177864 # Number of cycles that the object actually ticked
system.cpu2.idleCycles 6386615504 # Total number of cycles that the object has spent stopped
system.cpu3.branchPred.lookups 74718826 # Number of BP lookups
system.cpu3.branchPred.condPredicted 50589890 # Number of conditional branches predicted
system.cpu3.branchPred.condIncorrect 3325419 # Number of conditional branches incorrect
system.cpu3.branchPred.BTBLookups 50396966 # Number of BTB lookups
system.cpu3.branchPred.BTBHits 36328478 # Number of BTB hits
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.branchPred.BTBHitPct 72.084653 # BTB Hit Percentage
system.cpu3.branchPred.usedRAS 9777895 # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect 104949 # Number of incorrect RAS predictions.
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu3.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu3.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu3.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu3.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu3.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu3.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu3.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu3.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu3.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu3.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu3.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu3.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.dtb.walker.walks 514773 # Table walker walks requested
system.cpu3.dtb.walker.walksLong 514773 # Table walker walks initiated with long descriptors
system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8632 # Level at which table walker walks with long descriptors terminate
system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 50765 # Level at which table walker walks with long descriptors terminate
system.cpu3.dtb.walker.walksSquashedBefore 320483 # Table walks squashed before starting
system.cpu3.dtb.walker.walkWaitTime::samples 194290 # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::mean 2154.802100 # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::stdev 11919.135471 # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::0-32767 190271 97.93% 97.93% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::32768-65535 2868 1.48% 99.41% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::65536-98303 495 0.25% 99.66% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::98304-131071 352 0.18% 99.84% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::131072-163839 145 0.07% 99.92% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::163840-196607 61 0.03% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::196608-229375 39 0.02% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::229376-262143 16 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::262144-294911 21 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::294912-327679 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::327680-360447 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::360448-393215 8 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::393216-425983 9 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::total 194290 # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkCompletionTime::samples 239173 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::mean 21856.421921 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::gmean 17938.758794 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::stdev 15122.793116 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::0-65535 234615 98.09% 98.09% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::65536-131071 4213 1.76% 99.86% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::131072-196607 180 0.08% 99.93% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::196608-262143 137 0.06% 99.99% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::262144-327679 10 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::327680-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::393216-458751 11 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::total 239173 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walksPending::samples -26483974220 # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::mean 0.370007 # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::0-3 -27038933220 102.10% 102.10% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::4-7 309842500 -1.17% 100.93% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::8-11 102710000 -0.39% 100.54% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::12-15 66075500 -0.25% 100.29% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::16-19 25941500 -0.10% 100.19% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::20-23 14268000 -0.05% 100.14% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::24-27 12970500 -0.05% 100.09% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::28-31 19273500 -0.07% 100.01% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::32-35 3639000 -0.01% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::36-39 190500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::40-43 29000 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::44-47 8000 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::48-51 11000 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::total -26483974220 # Table walker pending requests distribution
system.cpu3.dtb.walker.walkPageSizes::4K 50765 85.47% 85.47% # Table walker page sizes translated
system.cpu3.dtb.walker.walkPageSizes::2M 8632 14.53% 100.00% # Table walker page sizes translated
system.cpu3.dtb.walker.walkPageSizes::total 59397 # Table walker page sizes translated
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 514773 # Table walker requests started/completed, data/inst
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 514773 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 59397 # Table walker requests started/completed, data/inst
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 59397 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin::total 574170 # Table walker requests started/completed, data/inst
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.inst_hits 0 # ITB inst hits
system.cpu3.dtb.inst_misses 0 # ITB inst misses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.dtb.read_hits 58948022 # DTB read hits
system.cpu3.dtb.read_misses 349619 # DTB read misses
system.cpu3.dtb.write_hits 46411302 # DTB write hits
system.cpu3.dtb.write_misses 165154 # DTB write misses
system.cpu3.dtb.flush_tlb 1180 # Number of times complete TLB was flushed
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.dtb.flush_tlb_mva_asid 11984 # Number of times TLB was flushed by MVA & ASID
system.cpu3.dtb.flush_tlb_asid 297 # Number of times TLB was flushed by ASID
system.cpu3.dtb.flush_entries 29239 # Number of entries that have been flushed from TLB
system.cpu3.dtb.align_faults 79 # Number of TLB faults due to alignment restrictions
system.cpu3.dtb.prefetch_faults 5206 # Number of TLB faults due to prefetch
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.dtb.perms_faults 31663 # Number of TLB faults due to permissions restrictions
system.cpu3.dtb.read_accesses 59297641 # DTB read accesses
system.cpu3.dtb.write_accesses 46576456 # DTB write accesses
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.inst_accesses 0 # ITB inst accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.dtb.hits 105359324 # DTB hits
system.cpu3.dtb.misses 514773 # DTB misses
system.cpu3.dtb.accesses 105874097 # DTB accesses
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu3.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu3.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu3.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu3.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu3.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu3.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu3.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu3.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu3.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu3.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu3.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu3.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.itb.walker.walks 60795 # Table walker walks requested
system.cpu3.itb.walker.walksLong 60795 # Table walker walks initiated with long descriptors
system.cpu3.itb.walker.walksLongTerminationLevel::Level2 1936 # Level at which table walker walks with long descriptors terminate
system.cpu3.itb.walker.walksLongTerminationLevel::Level3 41390 # Level at which table walker walks with long descriptors terminate
system.cpu3.itb.walker.walksSquashedBefore 8352 # Table walks squashed before starting
system.cpu3.itb.walker.walkWaitTime::samples 52443 # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::mean 1489.417081 # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::stdev 8610.325599 # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::0-32767 51982 99.12% 99.12% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::32768-65535 282 0.54% 99.66% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::65536-98303 109 0.21% 99.87% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::98304-131071 37 0.07% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::131072-163839 7 0.01% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::163840-196607 13 0.02% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::196608-229375 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::total 52443 # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkCompletionTime::samples 51678 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::mean 27642.962189 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::gmean 23739.857132 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::stdev 16715.530485 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::0-65535 50770 98.24% 98.24% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::65536-131071 774 1.50% 99.74% # Table walker service (enqueue to completion) latency
stats: Update switcheroo reference stats The Minor draining fixes affect perturb the timing slightly since it affects how the simulator is drained. Update reference statistics to reflect this expected change.
2015-07-31 18:04:59 +02:00
system.cpu3.itb.walker.walkCompletionTime::131072-196607 83 0.16% 99.90% # Table walker service (enqueue to completion) latency
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.itb.walker.walkCompletionTime::196608-262143 35 0.07% 99.97% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::262144-327679 5 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::327680-393215 9 0.02% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::total 51678 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walksPending::samples -30778988516 # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::mean 0.762645 # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::stdev 0.421863 # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::0 -7265808116 23.61% 23.61% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::1 -23547141900 76.50% 100.11% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::2 29216500 -0.09% 100.02% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::3 4017500 -0.01% 100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::4 490000 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::5 170000 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::6 67500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::total -30778988516 # Table walker pending requests distribution
system.cpu3.itb.walker.walkPageSizes::4K 41390 95.53% 95.53% # Table walker page sizes translated
system.cpu3.itb.walker.walkPageSizes::2M 1936 4.47% 100.00% # Table walker page sizes translated
system.cpu3.itb.walker.walkPageSizes::total 43326 # Table walker page sizes translated
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 60795 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Requested::total 60795 # Table walker requests started/completed, data/inst
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 43326 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::total 43326 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin::total 104121 # Table walker requests started/completed, data/inst
system.cpu3.itb.inst_hits 53907663 # ITB inst hits
system.cpu3.itb.inst_misses 60795 # ITB inst misses
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.itb.read_hits 0 # DTB read hits
system.cpu3.itb.read_misses 0 # DTB read misses
system.cpu3.itb.write_hits 0 # DTB write hits
system.cpu3.itb.write_misses 0 # DTB write misses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.itb.flush_tlb 1180 # Number of times complete TLB was flushed
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.itb.flush_tlb_mva_asid 11984 # Number of times TLB was flushed by MVA & ASID
system.cpu3.itb.flush_tlb_asid 297 # Number of times TLB was flushed by ASID
system.cpu3.itb.flush_entries 22179 # Number of entries that have been flushed from TLB
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.itb.perms_faults 120136 # Number of TLB faults due to permissions restrictions
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.itb.read_accesses 0 # DTB read accesses
system.cpu3.itb.write_accesses 0 # DTB write accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.itb.inst_accesses 53968458 # ITB inst accesses
system.cpu3.itb.hits 53907663 # DTB hits
system.cpu3.itb.misses 60795 # DTB misses
system.cpu3.itb.accesses 53968458 # DTB accesses
system.cpu3.numCycles 361864421 # number of cpu cycles simulated
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.fetch.icacheStallCycles 140139481 # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts 332397649 # Number of instructions fetch has processed
system.cpu3.fetch.Branches 74718826 # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches 46106373 # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles 200741121 # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles 7544543 # Number of cycles fetch has spent squashing
system.cpu3.fetch.TlbCycles 1439697 # Number of cycles fetch has spent waiting for tlb
system.cpu3.fetch.MiscStallCycles 5770 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.PendingDrainCycles 2171 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu3.fetch.PendingTrapStallCycles 3065576 # Number of stall cycles due to pending traps
system.cpu3.fetch.PendingQuiesceStallCycles 88539 # Number of stall cycles due to pending quiesce instructions
system.cpu3.fetch.IcacheWaitRetryStallCycles 4142 # Number of stall cycles due to full MSHR
system.cpu3.fetch.CacheLines 53769751 # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes 2045312 # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.ItlbSquashes 24414 # Number of outstanding ITLB misses that were squashed
system.cpu3.fetch.rateDist::samples 349258578 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean 1.114486 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev 2.357052 # Number of instructions fetched each cycle (Total)
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.fetch.rateDist::0 267245928 76.52% 76.52% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1 10321823 2.96% 79.47% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2 10331128 2.96% 82.43% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3 7716473 2.21% 84.64% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4 15764851 4.51% 89.15% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5 5041778 1.44% 90.60% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6 5511234 1.58% 92.18% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7 4828224 1.38% 93.56% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8 22497139 6.44% 100.00% # Number of instructions fetched each cycle (Total)
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.fetch.rateDist::total 349258578 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate 0.206483 # Number of branch fetches per cycle
system.cpu3.fetch.rate 0.918570 # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles 114369930 # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles 164038042 # Number of cycles decode is blocked
system.cpu3.decode.RunCycles 60584469 # Number of cycles decode is running
system.cpu3.decode.UnblockCycles 7298385 # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles 2965812 # Number of cycles decode is squashing
system.cpu3.decode.BranchResolved 11163267 # Number of times decode resolved a branch
system.cpu3.decode.BranchMispred 817702 # Number of times decode detected a branch misprediction
system.cpu3.decode.DecodedInsts 363461294 # Number of instructions handled by decode
system.cpu3.decode.SquashedInsts 2524053 # Number of squashed instructions handled by decode
system.cpu3.rename.SquashCycles 2965812 # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles 118569176 # Number of cycles rename is idle
system.cpu3.rename.BlockCycles 12281642 # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles 132557510 # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles 63592874 # Number of cycles rename is running
system.cpu3.rename.UnblockCycles 19289346 # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts 354946625 # Number of instructions processed by rename
system.cpu3.rename.ROBFullEvents 42029 # Number of times rename has blocked due to ROB full
system.cpu3.rename.IQFullEvents 1018488 # Number of times rename has blocked due to IQ full
system.cpu3.rename.LQFullEvents 787978 # Number of times rename has blocked due to LQ full
system.cpu3.rename.SQFullEvents 8985547 # Number of times rename has blocked due to SQ full
system.cpu3.rename.FullRegisterEvents 1997 # Number of times there has been no free registers
system.cpu3.rename.RenamedOperands 338843996 # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups 543179256 # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups 419420785 # Number of integer rename lookups
system.cpu3.rename.fp_rename_lookups 479701 # Number of floating rename lookups
system.cpu3.rename.CommittedMaps 284856001 # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps 53987990 # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts 8148289 # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts 7010381 # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts 40518568 # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads 57083242 # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores 48761213 # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads 7628593 # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores 8153720 # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded 337135094 # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded 8186679 # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued 336664947 # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued 479828 # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined 45100588 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined 28943367 # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved 197497 # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples 349258578 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean 0.963942 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev 1.678060 # Number of insts issued each cycle
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.iq.issued_per_cycle::0 218381855 62.53% 62.53% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1 54040442 15.47% 78.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2 24694063 7.07% 85.07% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3 17645756 5.05% 90.12% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4 13020798 3.73% 93.85% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5 9160873 2.62% 96.47% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6 6234653 1.79% 98.26% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7 3637468 1.04% 99.30% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8 2442670 0.70% 100.00% # Number of insts issued each cycle
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.iq.issued_per_cycle::total 349258578 # Number of insts issued each cycle
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.iq.fu_full::IntAlu 1713190 25.96% 25.96% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult 16354 0.25% 26.20% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv 1162 0.02% 26.22% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.22% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.22% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.22% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.22% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.22% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.22% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.22% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.22% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.22% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.22% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.22% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.22% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.22% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.22% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.22% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.22% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.22% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.22% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.22% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.22% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.22% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.22% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.22% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.22% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.22% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.22% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead 2637813 39.97% 66.19% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite 2231741 33.81% 100.00% # attempts to use FU when none available
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu 228589817 67.90% 67.90% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult 839294 0.25% 68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv 38427 0.01% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd 187 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc 41560 0.01% 68.17% # Type of FU issued
stats: Update switcheroo reference stats The Minor draining fixes affect perturb the timing slightly since it affects how the simulator is drained. Update reference statistics to reflect this expected change.
2015-07-31 18:04:59 +02:00
system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.17% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.17% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.17% # Type of FU issued
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.iq.FU_type_0::MemRead 60136646 17.86% 86.03% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite 47019015 13.97% 100.00% # Type of FU issued
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.iq.FU_type_0::total 336664947 # Type of FU issued
system.cpu3.iq.rate 0.930362 # Inst issue rate
system.cpu3.iq.fu_busy_cnt 6600260 # FU busy when requested
system.cpu3.iq.fu_busy_rate 0.019605 # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads 1029031717 # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes 390494788 # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses 324869188 # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads 636843 # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes 315952 # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses 284328 # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses 342924564 # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses 340642 # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads 2686629 # Number of loads that had data forwarded from stores
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.iew.lsq.thread0.squashedLoads 9062852 # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses 11957 # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation 394369 # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores 4946237 # Number of stores squashed
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.iew.lsq.thread0.rescheduledLoads 2102231 # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked 3983237 # Number of times an access to memory failed due to the cache being blocked
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.iew.iewSquashCycles 2965812 # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles 8240311 # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles 3183987 # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts 345400316 # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts 1015101 # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts 57083242 # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts 48761213 # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts 6857312 # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents 127001 # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents 3008020 # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents 394369 # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect 1508943 # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect 1318655 # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts 2827598 # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts 332842425 # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts 58939894 # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts 3314806 # Number of squashed instructions skipped in execute
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iew.exec_swp 0 # number of swp insts executed
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.iew.exec_nop 78543 # number of nop insts executed
system.cpu3.iew.exec_refs 105350305 # number of memory reference insts executed
system.cpu3.iew.exec_branches 61793426 # Number of branches executed
system.cpu3.iew.exec_stores 46410411 # Number of stores executed
system.cpu3.iew.exec_rate 0.919799 # Inst execution rate
system.cpu3.iew.wb_sent 325835982 # cumulative count of insts sent to commit
system.cpu3.iew.wb_count 325153516 # cumulative count of insts written-back
system.cpu3.iew.wb_producers 160610684 # num instructions producing a value
system.cpu3.iew.wb_consumers 278606679 # num instructions consuming a value
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.iew.wb_rate 0.898551 # insts written-back per cycle
system.cpu3.iew.wb_fanout 0.576478 # average fanout of values written-back
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.commit.commitSquashedInsts 45121096 # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls 7989182 # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts 2518769 # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples 341571330 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean 0.878941 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev 1.873545 # Number of insts commited each cycle
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.commit.committed_per_cycle::0 232593389 68.10% 68.10% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1 52799684 15.46% 83.55% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2 18973015 5.55% 89.11% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3 8542771 2.50% 91.61% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4 6283805 1.84% 93.45% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5 3713979 1.09% 94.54% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6 3487678 1.02% 95.56% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7 2200102 0.64% 96.20% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8 12976907 3.80% 100.00% # Number of insts commited each cycle
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.commit.committed_per_cycle::total 341571330 # Number of insts commited each cycle
system.cpu3.commit.committedInsts 255441658 # Number of instructions committed
system.cpu3.commit.committedOps 300221180 # Number of ops (including micro ops) committed
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.commit.refs 91835365 # Number of memory references committed
system.cpu3.commit.loads 48020389 # Number of loads committed
system.cpu3.commit.membars 2080926 # Number of memory barriers committed
system.cpu3.commit.branches 57030615 # Number of branches committed
system.cpu3.commit.fp_insts 272912 # Number of committed floating point instructions.
system.cpu3.commit.int_insts 275960484 # Number of committed integer instructions.
system.cpu3.commit.function_calls 7595427 # Number of function calls committed.
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.commit.op_class_0::IntAlu 207669074 69.17% 69.17% # Class of committed instruction
system.cpu3.commit.op_class_0::IntMult 652533 0.22% 69.39% # Class of committed instruction
system.cpu3.commit.op_class_0::IntDiv 28496 0.01% 69.40% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.40% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.40% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.40% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.40% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.40% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.40% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.40% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.40% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.40% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.40% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.40% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.40% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.40% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.40% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.40% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.40% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.40% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.40% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.40% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.40% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.40% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.40% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMisc 35712 0.01% 69.41% # Class of committed instruction
stats: Update switcheroo reference stats The Minor draining fixes affect perturb the timing slightly since it affects how the simulator is drained. Update reference statistics to reflect this expected change.
2015-07-31 18:04:59 +02:00
system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.41% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.41% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.41% # Class of committed instruction
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.commit.op_class_0::MemRead 48020389 16.00% 85.41% # Class of committed instruction
system.cpu3.commit.op_class_0::MemWrite 43814976 14.59% 100.00% # Class of committed instruction
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu3.commit.op_class_0::total 300221180 # Class of committed instruction
system.cpu3.commit.bw_lim_events 12976907 # number cycles where commit BW limit reached
system.cpu3.rob.rob_reads 671801943 # The number of ROB reads
system.cpu3.rob.rob_writes 698382232 # The number of ROB writes
system.cpu3.timesIdled 2359266 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles 12605843 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles 98651627369 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts 255441658 # Number of Instructions Simulated
system.cpu3.committedOps 300221180 # Number of Ops (including micro ops) Simulated
system.cpu3.cpi 1.416623 # CPI: Cycles Per Instruction
system.cpu3.cpi_total 1.416623 # CPI: Total CPI of All Threads
system.cpu3.ipc 0.705904 # IPC: Instructions Per Cycle
system.cpu3.ipc_total 0.705904 # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads 392429814 # number of integer regfile reads
system.cpu3.int_regfile_writes 232475172 # number of integer regfile writes
system.cpu3.fp_regfile_reads 557185 # number of floating regfile reads
system.cpu3.fp_regfile_writes 341168 # number of floating regfile writes
system.cpu3.cc_regfile_reads 70618800 # number of cc regfile reads
system.cpu3.cc_regfile_writes 71286741 # number of cc regfile writes
system.cpu3.misc_regfile_reads 655702130 # number of misc regfile reads
system.cpu3.misc_regfile_writes 8023774 # number of misc regfile writes
system.iobus.trans_dist::ReadReq 40266 # Transaction distribution
system.iobus.trans_dist::ReadResp 40266 # Transaction distribution
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.iobus.trans_dist::WriteReq 136539 # Transaction distribution
system.iobus.trans_dist::WriteResp 136539 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47694 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.iobus.pkt_count_system.bridge.master::total 122576 # Packet count per connected master and slave (bytes)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iobus.pkt_count::total 353610 # Packet count per connected master and slave (bytes)
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47714 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.iobus.pkt_size_system.bridge.master::total 155706 # Cumulative packet size per connected master and slave (bytes)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iobus.pkt_size::total 7492040 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 13439000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 4000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iobus.reqLayer23.occupancy 9713000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.iobus.reqLayer24.occupancy 45000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iobus.reqLayer25.occupancy 18683000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iobus.reqLayer26.occupancy 1000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iobus.reqLayer27.occupancy 237657786 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iobus.respLayer0.occupancy 43053000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iobus.respLayer3.occupancy 55076000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.tags.replacements 115459 # number of replacements
system.iocache.tags.tagsinuse 10.421040 # Cycle average of tags in use
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.tags.warmup_cycle 13087689445509 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.547391 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 6.873649 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.221712 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.429603 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.651315 # Average percentage of cache occupancy
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.tags.tag_accesses 1039650 # Number of tag accesses
system.iocache.tags.data_accesses 1039650 # Number of data accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses
system.iocache.demand_misses::total 8853 # number of demand (read+write) misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.overall_misses::realview.ide 8813 # number of overall misses
system.iocache.overall_misses::total 8853 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide 399236664 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 399236664 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 5327578122 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 5327578122 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide 399236664 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 399236664 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 399236664 # number of overall miss cycles
system.iocache.overall_miss_latency::total 399236664 # number of overall miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.ReadReq_avg_miss_latency::realview.ide 45300.880971 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 45111.487458 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 49947.293576 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 49947.293576 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 45300.880971 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 45096.200610 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 45300.880971 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 45096.200610 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 7536 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.blocked::no_mshrs 866 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.avg_blocked_cycles::no_mshrs 8.702079 # average number of cycles each access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.iocache.writebacks::writebacks 106631 # number of writebacks
system.iocache.writebacks::total 106631 # number of writebacks
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.ReadReq_mshr_misses::realview.ide 2210 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 2210 # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 45088 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 45088 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide 2210 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 2210 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 2210 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 2210 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide 288736664 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 288736664 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 3073178122 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 3073178122 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 288736664 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 288736664 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 288736664 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 288736664 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.250766 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.249718 # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.422711 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 0.422711 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide 0.250766 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 0.249633 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 0.250766 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 0.249633 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130650.074208 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 130650.074208 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68159.557355 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68159.557355 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 130650.074208 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 130650.074208 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 130650.074208 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 130650.074208 # average overall mshr miss latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.tags.replacements 1184273 # number of replacements
system.l2c.tags.tagsinuse 65309.557565 # Cycle average of tags in use
system.l2c.tags.total_refs 47546139 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1247279 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 38.119891 # Average number of references to valid blocks.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit.
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.tags.occ_blocks::writebacks 36497.090356 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 128.195847 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 207.365343 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 3477.103411 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 10892.259737 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 41.622029 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 64.439339 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 663.388118 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 2525.804190 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker 38.130985 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.itb.walker 52.876796 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 2102.725425 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 2793.262675 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.dtb.walker 102.733184 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.itb.walker 141.240216 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.inst 2056.053767 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.data 3525.266147 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.556901 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001956 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.003164 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.053056 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.166203 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000635 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.000983 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.010122 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.038541 # Average percentage of cache occupancy
stats: Update switcheroo reference stats The Minor draining fixes affect perturb the timing slightly since it affects how the simulator is drained. Update reference statistics to reflect this expected change.
2015-07-31 18:04:59 +02:00
system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000582 # Average percentage of cache occupancy
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.tags.occ_percent::cpu2.itb.walker 0.000807 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.032085 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.042622 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.dtb.walker 0.001568 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.itb.walker 0.002155 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst 0.031373 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data 0.053791 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.996545 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 327 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 62679 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 327 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 606 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 2840 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 5162 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 53967 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.004990 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.956406 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 421248793 # Number of tag accesses
system.l2c.tags.data_accesses 421248793 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 162889 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 111955 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 57699 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 43341 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker 155107 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker 59126 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.dtb.walker 295251 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.itb.walker 109680 # number of ReadReq hits
system.l2c.ReadReq_hits::total 995048 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 7547308 # number of Writeback hits
system.l2c.Writeback_hits::total 7547308 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 3780 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 1173 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data 1572 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3.data 2840 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 9365 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu3.data 1 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 632256 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 192717 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data 281149 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3.data 476183 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 1582305 # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst 5480649 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst 1714018 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst 3866218 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu3.inst 4626735 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total 15687620 # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 2570779 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 762751 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data 1043289 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu3.data 1899052 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 6275871 # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data 287062 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data 90395 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu2.data 123163 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu3.data 231327 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total 731947 # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker 162889 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 111955 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 5480649 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 3203035 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 57699 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 43341 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 1714018 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 955468 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker 155107 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker 59126 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 3866218 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 1324438 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.dtb.walker 295251 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.itb.walker 109680 # number of demand (read+write) hits
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system.l2c.overall_hits::cpu3.data 2375235 # number of overall hits
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system.l2c.UpgradeReq_misses::cpu0.data 13809 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 4442 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 5676 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data 10160 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 34087 # number of UpgradeReq misses
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.l2c.SCUpgradeReq_misses::cpu3.data 2 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
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system.l2c.ReadCleanReq_misses::cpu1.inst 10171 # number of ReadCleanReq misses
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system.l2c.ReadCleanReq_misses::cpu3.inst 28695 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total 100003 # number of ReadCleanReq misses
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system.l2c.ReadReq_miss_latency::total 310137000 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 67216500 # number of UpgradeReq miss cycles
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system.l2c.UpgradeReq_miss_latency::cpu3.data 160025000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 318025000 # number of UpgradeReq miss cycles
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.l2c.SCUpgradeReq_miss_latency::cpu3.data 81000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 81000 # number of SCUpgradeReq miss cycles
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
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system.l2c.InvalidateReq_miss_latency::total 11070411500 # number of InvalidateReq miss cycles
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system.l2c.Writeback_accesses::writebacks 7547308 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 7547308 # number of Writeback accesses(hits+misses)
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system.l2c.ReadCleanReq_accesses::cpu3.inst 4655430 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total 15787623 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 2692113 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 793400 # number of ReadSharedReq accesses(hits+misses)
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system.l2c.ReadSharedReq_accesses::cpu3.data 1970586 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 6539198 # number of ReadSharedReq accesses(hits+misses)
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system.l2c.InvalidateReq_accesses::cpu1.data 108292 # number of InvalidateReq accesses(hits+misses)
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system.l2c.InvalidateReq_accesses::cpu3.data 296025 # number of InvalidateReq accesses(hits+misses)
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system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.007353 # miss rate for ReadReq accesses
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system.l2c.UpgradeReq_miss_rate::cpu1.data 0.791095 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data 0.783113 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data 0.781538 # miss rate for UpgradeReq accesses
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system.l2c.ReadExReq_miss_rate::cpu2.data 0.194439 # miss rate for ReadExReq accesses
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system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.005899 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.006415 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.006164 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total 0.006334 # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.045070 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.038630 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.036756 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.036301 # miss rate for ReadSharedReq accesses
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system.l2c.InvalidateReq_miss_rate::total 0.402303 # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.007984 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.012629 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.006557 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.087314 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.005601 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.007238 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.005899 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.077932 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker 0.003329 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.itb.walker 0.007353 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst 0.006415 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data 0.075184 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.dtb.walker 0.003423 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.itb.walker 0.008480 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst 0.006164 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data 0.071534 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.030963 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.007984 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.012629 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.006557 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.087314 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.005601 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.007238 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.005899 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.077932 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker 0.003329 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.itb.walker 0.007353 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst 0.006415 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data 0.075184 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.dtb.walker 0.003423 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.itb.walker 0.008480 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst 0.006164 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data 0.071534 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.030963 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 84289.230769 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 85376.582278 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 89315.637066 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 87270.547945 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 87119.329389 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.itb.walker 88416.844350 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 49290.686586 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15132.035119 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 15994.274137 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 15750.492126 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 9329.803151 # average UpgradeReq miss latency
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.l2c.SCUpgradeReq_avg_miss_latency::cpu3.data 40500 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 40500 # average SCUpgradeReq miss latency
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 80601.953858 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 81311.158103 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 98007.118763 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 49408.261263 # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80749.631305 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 83179.079364 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 85312.266945 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 53454.126376 # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 82693.790988 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 83641.559910 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 88774.128387 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 46385.752316 # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 79397.608538 # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu2.data 88042.152984 # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu3.data 107872.175338 # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total 22470.464717 # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 84289.230769 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 85376.582278 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 80749.631305 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 81395.870225 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 89315.637066 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.itb.walker 87270.547945 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 83179.079364 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 82172.794903 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 87119.329389 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.itb.walker 88416.844350 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst 85312.266945 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 94397.978142 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 48908.292068 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 84289.230769 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 85376.582278 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 80749.631305 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 81395.870225 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 89315.637066 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.itb.walker 87270.547945 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 83179.079364 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 82172.794903 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 87119.329389 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.itb.walker 88416.844350 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst 85312.266945 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 94397.978142 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 48908.292068 # average overall miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.writebacks::writebacks 984548 # number of writebacks
system.l2c.writebacks::total 984548 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu3.dtb.walker 1 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3.itb.walker 9 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 1 # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.ReadSharedReq_mshr_hits::cpu2.data 2 # number of ReadSharedReq MSHR hits
stats: Update switcheroo reference stats The Minor draining fixes affect perturb the timing slightly since it affects how the simulator is drained. Update reference statistics to reflect this expected change.
2015-07-31 18:04:59 +02:00
system.l2c.ReadSharedReq_mshr_hits::cpu3.data 3 # number of ReadSharedReq MSHR hits
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu2.data 2 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.dtb.walker 1 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.itb.walker 9 # number of demand (read+write) MSHR hits
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.l2c.demand_mshr_hits::cpu3.inst 1 # number of demand (read+write) MSHR hits
stats: Update switcheroo reference stats The Minor draining fixes affect perturb the timing slightly since it affects how the simulator is drained. Update reference statistics to reflect this expected change.
2015-07-31 18:04:59 +02:00
system.l2c.demand_mshr_hits::cpu3.data 3 # number of demand (read+write) MSHR hits
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu2.data 2 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.dtb.walker 1 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.itb.walker 9 # number of overall MSHR hits
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.l2c.overall_mshr_hits::cpu3.inst 1 # number of overall MSHR hits
stats: Update switcheroo reference stats The Minor draining fixes affect perturb the timing slightly since it affects how the simulator is drained. Update reference statistics to reflect this expected change.
2015-07-31 18:04:59 +02:00
system.l2c.overall_mshr_hits::cpu3.data 3 # number of overall MSHR hits
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.overall_mshr_hits::total 16 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 325 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 316 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 518 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 438 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.dtb.walker 1013 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.itb.walker 929 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 3539 # number of ReadReq MSHR misses
system.l2c.CleanEvict_mshr_misses::writebacks 453 # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total 453 # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 4442 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data 5676 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data 10160 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 20278 # number of UpgradeReq MSHR misses
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.l2c.SCUpgradeReq_mshr_misses::cpu3.data 2 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.ReadExReq_mshr_misses::cpu1.data 50106 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data 67861 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data 111466 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 229433 # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 10171 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 24961 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 28694 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total 63826 # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 30649 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2.data 39808 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu3.data 71531 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total 141988 # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data 17897 # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu2.data 30330 # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu3.data 64698 # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total 112925 # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 325 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker 316 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 10171 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 80755 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker 518 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.itb.walker 438 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst 24961 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data 107669 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.dtb.walker 1013 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.itb.walker 929 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst 28694 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data 182997 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 438786 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 325 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker 316 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 10171 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 80755 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker 518 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.itb.walker 438 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst 24961 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data 107669 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.dtb.walker 1013 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.itb.walker 929 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst 28694 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data 182997 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 438786 # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5947 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu2.data 4621 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu3.data 4770 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total 15338 # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 5383 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu2.data 4193 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu3.data 4437 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total 14013 # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 11330 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu2.data 8814 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu3.data 9207 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total 29351 # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 24144000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 23819000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 41085500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 33844500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.dtb.walker 78151000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.itb.walker 72937000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 273981000 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 91747500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 117799500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 210807500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 420354500 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu3.data 92000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 92000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3537581500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 4839246500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 9809801500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 18186629500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 719594500 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 1826623000 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 2161084000 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total 4707301500 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 2227992000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 2931602000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 5634867500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 10794461500 # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1242009000 # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu2.data 2367018500 # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu3.data 6332134000 # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total 9941161500 # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 24144000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 23819000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 719594500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 5765573500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 41085500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 33844500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 1826623000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 7770848500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker 78151000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.itb.walker 72937000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst 2161084000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data 15444669000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 33962373500 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 24144000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 23819000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 719594500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 5765573500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 41085500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 33844500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst 1826623000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data 7770848500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker 78151000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.itb.walker 72937000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst 2161084000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data 15444669000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 33962373500 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 946766500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 728700000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data 770595000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 2446061500 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 881146000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 669497000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data 751355000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 2301998000 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1827912500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 1398197000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3.data 1521950000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 4748059500 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.005601 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.007238 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.003329 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.007353 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker 0.003419 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker 0.008398 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.003534 # mshr miss rate for ReadReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.791095 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.783113 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.781538 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.466676 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data 0.666667 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.666667 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.206348 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.194439 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.189681 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.114899 # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005899 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.006415 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.006164 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.004043 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.038630 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.036754 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.036299 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.021713 # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.165266 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data 0.197599 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data 0.218556 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total 0.092213 # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.005601 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.007238 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005899 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.077932 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003329 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.007353 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006415 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.075182 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003419 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.itb.walker 0.008398 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst 0.006164 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data 0.071533 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.017326 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.005601 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.007238 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005899 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.077932 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003329 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.007353 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.006415 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.075182 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003419 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.itb.walker 0.008398 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.006164 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data 0.071533 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.017326 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74289.230769 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 75376.582278 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 79315.637066 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 77270.547945 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 77148.075025 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 78511.302476 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 77417.632099 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20654.547501 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20753.964059 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 20748.769685 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20729.583785 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 46000 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 46000 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70601.953858 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71311.158103 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 88007.118763 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 79267.714322 # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70749.631305 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73179.079364 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 75314.839339 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73752.099458 # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72693.790988 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 73643.538987 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 78775.181390 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 76023.759050 # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69397.608538 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 78042.152984 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 97872.175338 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 88033.309719 # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74289.230769 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 75376.582278 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70749.631305 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71395.870225 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 79315.637066 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 77270.547945 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73179.079364 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 72173.499336 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 77148.075025 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 78511.302476 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 75314.839339 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 84398.481942 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 77400.768256 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74289.230769 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 75376.582278 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70749.631305 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71395.870225 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 79315.637066 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 77270.547945 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73179.079364 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 72173.499336 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 77148.075025 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 78511.302476 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 75314.839339 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 84398.481942 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 77400.768256 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 159200.689423 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 157693.140013 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 161550.314465 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 159477.213457 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163690.507152 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 159670.164560 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 169338.517016 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 164275.886677 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 161333.848191 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 158633.651010 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 165303.573368 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 161768.236176 # average overall mshr uncacheable latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.membus.trans_dist::ReadReq 76737 # Transaction distribution
system.membus.trans_dist::ReadResp 455193 # Transaction distribution
system.membus.trans_dist::WriteReq 33647 # Transaction distribution
system.membus.trans_dist::WriteResp 33647 # Transaction distribution
system.membus.trans_dist::Writeback 1091179 # Transaction distribution
system.membus.trans_dist::CleanEvict 208864 # Transaction distribution
system.membus.trans_dist::UpgradeReq 34786 # Transaction distribution
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.membus.trans_dist::UpgradeResp 34788 # Transaction distribution
system.membus.trans_dist::ReadExReq 906494 # Transaction distribution
system.membus.trans_dist::ReadExResp 906494 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 378456 # Transaction distribution
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution
system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122576 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 62 # Packet count per connected master and slave (bytes)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6756 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3898162 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 4027556 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 345368 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 345368 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4372924 # Packet count per connected master and slave (bytes)
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155706 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 196 # Cumulative packet size per connected master and slave (bytes)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13512 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 144864864 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 145034278 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7356288 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7356288 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 152390566 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 691 # Total snoops (count)
system.membus.snoop_fanout::samples 2837421 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.membus.snoop_fanout::1 2837421 100.00% 100.00% # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.membus.snoop_fanout::total 2837421 # Request fanout histogram
system.membus.reqLayer0.occupancy 49386500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.membus.reqLayer1.occupancy 2000 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.membus.reqLayer2.occupancy 1639500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.membus.reqLayer5.occupancy 3223716711 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.membus.respLayer2.occupancy 3001422636 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.membus.respLayer3.occupancy 89214499 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
stats: Update ARM stats to include programmable oscillators
2015-08-07 16:39:17 +02:00
system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks
system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks
system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.toL2Bus.trans_dist::ReadReq 1500754 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 23827950 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 33647 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 33647 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 8025102 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 18108882 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 43452 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 43455 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 1996830 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 1996830 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 15787707 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 6541408 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 1269700 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp 1224612 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47446864 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29502710 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 824705 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1741139 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 79515418 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1010580372 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1029542098 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2979800 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6154816 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 2049257086 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 987636 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 53377948 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 1.039876 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.195669 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.toL2Bus.snoop_fanout::1 51249425 96.01% 96.01% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 2128523 3.99% 100.00% # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.toL2Bus.snoop_fanout::total 53377948 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 20681814986 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.toL2Bus.snoopLayer0.occupancy 436500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.toL2Bus.respLayer0.occupancy 15410337923 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.toL2Bus.respLayer1.occupancy 7854888294 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.toL2Bus.respLayer2.occupancy 293722728 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.toL2Bus.respLayer3.occupancy 713107905 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.kern.inst.arm 0 # number of arm instructions executed
system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
---------- End Simulation Statistics ----------
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