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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt

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arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
---------- Begin Simulation Statistics ----------
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
sim_seconds 51.234988 # Number of seconds simulated
sim_ticks 51234988037500 # Number of ticks simulated
final_tick 51234988037500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
host_inst_rate 253332 # Simulator instruction rate (inst/s)
host_op_rate 297695 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 14683650995 # Simulator tick rate (ticks/s)
host_mem_usage 666424 # Number of bytes of host memory used
host_seconds 3489.25 # Real time elapsed on the host
sim_insts 883939374 # Number of instructions simulated
sim_ops 1038732312 # Number of ops (including micro ops) simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.bytes_read::cpu0.dtb.walker 127040 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 124736 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 3010420 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 25072712 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 36992 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 30656 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 716608 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 7359168 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker 93568 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.itb.walker 90944 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 2126784 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 17729152 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 417856 # Number of bytes read from this memory
system.physmem.bytes_read::total 56936636 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 3010420 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 716608 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 2126784 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 5853812 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 77081408 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
system.physmem.bytes_written::total 77101988 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 1985 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1949 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 87445 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 391774 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 578 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 479 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 11197 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 114987 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker 1462 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.itb.walker 1421 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 33231 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 277018 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6529 # Number of read requests responded to by this memory
system.physmem.num_reads::total 930055 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1204397 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1206970 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 2480 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 2435 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 58757 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 489367 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 722 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 598 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 13987 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 143636 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker 1826 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.itb.walker 1775 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 41510 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 346036 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 8156 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1111284 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 58757 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 13987 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 41510 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 114254 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1504468 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 402 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1504870 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1504468 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 2480 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 2435 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 58757 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 489769 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 722 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 598 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 13987 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 143636 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker 1826 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.itb.walker 1775 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 41510 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 346036 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 8156 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2616154 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 440433 # Number of read requests accepted
system.physmem.writeReqs 603232 # Number of write requests accepted
system.physmem.readBursts 440433 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 603232 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 28170752 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 16960 # Total number of bytes read from write queue
system.physmem.bytesWritten 38511488 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 28187712 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 38606848 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 265 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 1490 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 18504 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 25157 # Per bank write bursts
system.physmem.perBankRdBursts::1 28496 # Per bank write bursts
system.physmem.perBankRdBursts::2 28335 # Per bank write bursts
system.physmem.perBankRdBursts::3 27633 # Per bank write bursts
system.physmem.perBankRdBursts::4 27808 # Per bank write bursts
system.physmem.perBankRdBursts::5 30320 # Per bank write bursts
system.physmem.perBankRdBursts::6 26148 # Per bank write bursts
system.physmem.perBankRdBursts::7 26657 # Per bank write bursts
system.physmem.perBankRdBursts::8 26790 # Per bank write bursts
system.physmem.perBankRdBursts::9 29797 # Per bank write bursts
system.physmem.perBankRdBursts::10 28841 # Per bank write bursts
system.physmem.perBankRdBursts::11 30668 # Per bank write bursts
system.physmem.perBankRdBursts::12 26625 # Per bank write bursts
system.physmem.perBankRdBursts::13 26518 # Per bank write bursts
system.physmem.perBankRdBursts::14 25131 # Per bank write bursts
system.physmem.perBankRdBursts::15 25244 # Per bank write bursts
system.physmem.perBankWrBursts::0 36236 # Per bank write bursts
system.physmem.perBankWrBursts::1 36759 # Per bank write bursts
system.physmem.perBankWrBursts::2 37480 # Per bank write bursts
system.physmem.perBankWrBursts::3 39199 # Per bank write bursts
system.physmem.perBankWrBursts::4 39135 # Per bank write bursts
system.physmem.perBankWrBursts::5 41156 # Per bank write bursts
system.physmem.perBankWrBursts::6 37007 # Per bank write bursts
system.physmem.perBankWrBursts::7 36943 # Per bank write bursts
system.physmem.perBankWrBursts::8 37618 # Per bank write bursts
system.physmem.perBankWrBursts::9 39787 # Per bank write bursts
system.physmem.perBankWrBursts::10 38447 # Per bank write bursts
system.physmem.perBankWrBursts::11 38818 # Per bank write bursts
system.physmem.perBankWrBursts::12 34864 # Per bank write bursts
system.physmem.perBankWrBursts::13 36482 # Per bank write bursts
system.physmem.perBankWrBursts::14 35714 # Per bank write bursts
system.physmem.perBankWrBursts::15 36097 # Per bank write bursts
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.numWrRetry 12 # Number of times write queue was full causing retry
system.physmem.totGap 51233791781500 # Total gap between requests
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.readPktSize::6 440433 # Read request sizes (log2)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.writePktSize::6 603232 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 309302 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 89084 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 29255 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 12395 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 102 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.wrQLenPdf::0 479 # What write queue length does an incoming req see
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.wrQLenPdf::1 480 # What write queue length does an incoming req see
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.wrQLenPdf::2 478 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 477 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 475 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 474 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 473 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 468 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 469 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 469 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 463 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 462 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 460 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 461 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 455 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 12525 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 16592 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 24225 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 27652 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 32938 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 35820 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 36604 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 38132 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 38614 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 39680 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 39064 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 37806 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 36835 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 37288 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 32953 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 32715 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 32497 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 31145 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 1482 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 1151 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 1008 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 852 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 777 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 671 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 605 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 516 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 475 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 433 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 389 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 361 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 332 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 293 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 272 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 259 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 251 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 228 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 215 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 182 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 164 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 130 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 115 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 98 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 90 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 80 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 58 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 48 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 34 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 26 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 270943 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 246.111691 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 146.841271 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 289.814348 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 123351 45.53% 45.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 67798 25.02% 70.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 24089 8.89% 79.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 12477 4.61% 84.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 8623 3.18% 87.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 5501 2.03% 89.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 4269 1.58% 90.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 3914 1.44% 92.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 20921 7.72% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 270943 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 29531 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 14.905286 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 10.293446 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-15 12117 41.03% 41.03% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::16-31 16080 54.45% 95.48% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::32-47 1080 3.66% 99.14% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::48-63 183 0.62% 99.76% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::64-79 43 0.15% 99.91% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::80-95 13 0.04% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::96-111 6 0.02% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::112-127 3 0.01% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::128-143 3 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::176-191 2 0.01% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::320-335 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 29531 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 29531 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 20.376621 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.754514 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 13.014003 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3 5 0.02% 0.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7 10 0.03% 0.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11 10 0.03% 0.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15 38 0.13% 0.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 24052 81.45% 81.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 2161 7.32% 88.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 399 1.35% 90.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 574 1.94% 92.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 563 1.91% 94.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 287 0.97% 95.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 195 0.66% 95.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 150 0.51% 96.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 203 0.69% 97.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 86 0.29% 97.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 51 0.17% 97.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 59 0.20% 97.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 110 0.37% 98.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 84 0.28% 98.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 56 0.19% 98.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 59 0.20% 98.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 85 0.29% 99.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 34 0.12% 99.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 26 0.09% 99.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 18 0.06% 99.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 70 0.24% 99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 10 0.03% 99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 9 0.03% 99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 9 0.03% 99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 14 0.05% 99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119 8 0.03% 99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 6 0.02% 99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 7 0.02% 99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 32 0.11% 99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 9 0.03% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 3 0.01% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 7 0.02% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 7 0.02% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151 8 0.03% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 2 0.01% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163 3 0.01% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171 3 0.01% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183 1 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-187 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::196-199 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-211 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-219 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-227 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::228-231 2 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::232-235 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 29531 # Writes before turning the bus around for reads
system.physmem.totQLat 10316676500 # Total ticks spent queuing
system.physmem.totMemAccLat 18569826500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2200840000 # Total ticks spent in databus transfers
system.physmem.avgQLat 23438.04 # Average queueing delay per DRAM burst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.avgMemAccLat 42188.04 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 0.55 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.75 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 0.55 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.75 # Average system write bandwidth in MiByte/s
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.01 # Data bus utilization in percentage
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.busUtilRead 0.00 # Data bus utilization in percentage for reads
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 26.22 # Average write queue length when enqueuing
system.physmem.readRowHits 332271 # Number of row buffer hits during reads
system.physmem.writeRowHits 438696 # Number of row buffer hits during writes
system.physmem.readRowHitRate 75.49 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 72.90 # Row buffer hit rate for writes
system.physmem.avgGap 49090265.35 # Average gap between requests
system.physmem.pageHitRate 74.00 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 49384314860250 # Time in different power states
system.physmem.memoryStateTime::REF 1710848620000 # Time in different power states
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.memoryStateTime::ACT 139817808500 # Time in different power states
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.actEnergy::0 1046447640 # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1 1001881440 # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0 570978375 # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1 546661500 # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0 1720321200 # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1 1712989200 # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0 1969369200 # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1 1929918960 # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0 3346419900720 # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1 3346419900720 # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0 1177540520625 # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1 1174853241090 # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0 29708058483750 # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1 29710415746500 # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0 34237326021510 # Total energy per rank (pJ)
system.physmem.totalEnergy::1 34236880339410 # Total energy per rank (pJ)
system.physmem.averagePower::0 668.241213 # Core power per rank (mW)
system.physmem.averagePower::1 668.232514 # Core power per rank (mW)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.realview.nvmem.bytes_read::cpu2.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 196 # Number of bytes read from this memory
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.realview.nvmem.bytes_inst_read::cpu2.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.realview.nvmem.num_reads::cpu2.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.realview.nvmem.bw_read::cpu2.inst 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.realview.nvmem.bw_inst_read::cpu2.inst 1 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.realview.nvmem.bw_total::cpu2.inst 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dtb.read_hits 78485873 # DTB read hits
system.cpu0.dtb.read_misses 85123 # DTB read misses
system.cpu0.dtb.write_hits 72027961 # DTB write hits
system.cpu0.dtb.write_misses 28205 # DTB write misses
system.cpu0.dtb.flush_tlb 1285 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dtb.flush_tlb_mva_asid 21048 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 509 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 51602 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dtb.prefetch_faults 4002 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dtb.perms_faults 9811 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 78570996 # DTB read accesses
system.cpu0.dtb.write_accesses 72056166 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dtb.hits 150513834 # DTB hits
system.cpu0.dtb.misses 113328 # DTB misses
system.cpu0.dtb.accesses 150627162 # DTB accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.itb.inst_hits 421004293 # ITB inst hits
system.cpu0.itb.inst_misses 63363 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.itb.flush_tlb 1285 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.itb.flush_tlb_mva_asid 21048 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 509 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 36267 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.itb.inst_accesses 421067656 # ITB inst accesses
system.cpu0.itb.hits 421004293 # DTB hits
system.cpu0.itb.misses 63363 # DTB misses
system.cpu0.itb.accesses 421067656 # DTB accesses
system.cpu0.numCycles 506516508 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.committedInsts 420811760 # Number of instructions committed
system.cpu0.committedOps 495213745 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 454628715 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 411957 # Number of float alu accesses
system.cpu0.num_func_calls 25378118 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 63987651 # number of instructions that are conditional controls
system.cpu0.num_int_insts 454628715 # number of integer instructions
system.cpu0.num_fp_insts 411957 # number of float instructions
system.cpu0.num_int_register_reads 670075882 # number of times the integer registers were read
system.cpu0.num_int_register_writes 361231436 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 665979 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 343448 # number of times the floating registers were written
system.cpu0.num_cc_register_reads 110680974 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 110422200 # number of times the CC registers were written
system.cpu0.num_mem_refs 150607491 # number of memory refs
system.cpu0.num_load_insts 78559078 # Number of load instructions
system.cpu0.num_store_insts 72048413 # Number of store instructions
system.cpu0.num_idle_cycles 494422986.191521 # Number of idle cycles
system.cpu0.num_busy_cycles 12093521.808479 # Number of busy cycles
system.cpu0.not_idle_fraction 0.023876 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.976124 # Percentage of idle cycles
system.cpu0.Branches 93934421 # Number of branches fetched
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.op_class::IntAlu 343753597 69.37% 69.37% # Class of executed instruction
system.cpu0.op_class::IntMult 1048568 0.21% 69.59% # Class of executed instruction
system.cpu0.op_class::IntDiv 47671 0.01% 69.60% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 69.60% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 69.60% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 69.60% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 69.60% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 69.60% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 69.60% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 69.60% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 69.60% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 69.60% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 69.60% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 69.60% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 69.60% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 69.60% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 69.60% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 69.60% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.60% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 69.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 1 0.00% 69.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 50027 0.01% 69.61% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 69.61% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.61% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.61% # Class of executed instruction
system.cpu0.op_class::MemRead 78559078 15.85% 85.46% # Class of executed instruction
system.cpu0.op_class::MemWrite 72048413 14.54% 100.00% # Class of executed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.op_class::total 495507356 # Class of executed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.kern.inst.quiesce 16313 # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements 10203749 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.999717 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 304434614 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 10204261 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 29.834068 # Average number of references to valid blocks.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.228127 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 4.974365 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data 10.797225 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.969196 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.009716 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.021088 # Average percentage of cache occupancy
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 210 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.tags.tag_accesses 1294524003 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 1294524003 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 73268923 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 23739594 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 59414779 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 156423296 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 68111490 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 21735522 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data 49847350 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 139694362 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 193034 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 58570 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data 140375 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 391979 # number of SoftPFReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 149338 # number of WriteInvalidateReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 52269 # number of WriteInvalidateReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::cpu2.data 129188 # number of WriteInvalidateReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::total 330795 # number of WriteInvalidateReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1809029 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 564897 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 1231072 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 3604998 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1922189 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 609751 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data 1411604 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 3943544 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 141380413 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 45475116 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data 109262129 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 296117658 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 141573447 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 45533686 # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data 109402504 # number of overall hits
system.cpu0.dcache.overall_hits::total 296509637 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 2527678 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 793028 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data 4769702 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 8090408 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1085359 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 334528 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data 4280292 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 5700179 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 626966 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 195030 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data 455384 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 1277380 # number of SoftPFReq misses
system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 755062 # number of WriteInvalidateReq misses
system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 138919 # number of WriteInvalidateReq misses
system.cpu0.dcache.WriteInvalidateReq_misses::cpu2.data 339873 # number of WriteInvalidateReq misses
system.cpu0.dcache.WriteInvalidateReq_misses::total 1233854 # number of WriteInvalidateReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 114004 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 45120 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 230004 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 389128 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data 2 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu2.data 4 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 3613037 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 1127556 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data 9049994 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 13790587 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 4240003 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 1322586 # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data 9505378 # number of overall misses
system.cpu0.dcache.overall_misses::total 15067967 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 12089122250 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 81775203412 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 93864325662 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 9781004455 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 158074758437 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 167855762892 # number of WriteReq miss cycles
system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu1.data 2453110503 # number of WriteInvalidateReq miss cycles
system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu2.data 10603203705 # number of WriteInvalidateReq miss cycles
system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 13056314208 # number of WriteInvalidateReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 651998250 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 3227061036 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 3879059286 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 150500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 64001 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 214501 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 21870126705 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data 239849961849 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 261720088554 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 21870126705 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data 239849961849 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 261720088554 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 75796601 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 24532622 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data 64184481 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 164513704 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 69196849 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 22070050 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 54127642 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 145394541 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 820000 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 253600 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 595759 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 1669359 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 904400 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data 191188 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::cpu2.data 469061 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::total 1564649 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1923033 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 610017 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 1461076 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 3994126 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1922190 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 609753 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 1411608 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 3943551 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 144993450 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 46602672 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data 118312123 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 309908245 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 145813450 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 46856272 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 118907882 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 311577604 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033348 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.032325 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.074312 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.049178 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015685 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015158 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.079078 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.039205 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.764593 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.769046 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.764376 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.765192 # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.834876 # miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.726609 # miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu2.data 0.724582 # miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.788582 # miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059283 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.073965 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.157421 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.097425 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000001 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000003 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000003 # miss rate for StoreCondReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024919 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024195 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.076493 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.044499 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029078 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028226 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.079939 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.048360 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15244.256508 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17144.719610 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 11601.927327 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 29238.223572 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 36930.835195 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 29447.454701 # average WriteReq miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 17658.567244 # average WriteInvalidateReq miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu2.data 31197.546451 # average WriteInvalidateReq miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 10581.733502 # average WriteInvalidateReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14450.315824 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14030.456149 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9968.594617 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 75250 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16000.250000 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 30643 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19396.044813 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 26502.775786 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 18978.168845 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16535.882510 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25233.079826 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 17369.303275 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 16646814 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 16737 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 1171436 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 381 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.210605 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 43.929134 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.writebacks::writebacks 7869277 # number of writebacks
system.cpu0.dcache.writebacks::total 7869277 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 1021 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 2728886 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 2729907 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 3191 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 3547950 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 3551141 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu2.data 2444 # number of WriteInvalidateReq MSHR hits
system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 2444 # number of WriteInvalidateReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 10468 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 139963 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 150431 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 4212 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data 6276836 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 6281048 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 4212 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data 6276836 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 6281048 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 792007 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 2040816 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 2832823 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 331337 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 732342 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 1063679 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 194976 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 448304 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 643280 # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 138919 # number of WriteInvalidateReq MSHR misses
system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu2.data 337429 # number of WriteInvalidateReq MSHR misses
system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 476348 # number of WriteInvalidateReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 34652 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 90041 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 124693 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 2 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 4 # number of StoreCondReq MSHR misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dcache.StoreCondReq_mshr_misses::total 6 # number of StoreCondReq MSHR misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.demand_mshr_misses::cpu1.data 1123344 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data 2773158 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 3896502 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 1318320 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data 3221462 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 4539782 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 10425295500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 30694668987 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41119964487 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 8981852045 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 24997038072 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 33978890117 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 2907550500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 9282645690 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 12190196190 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 2175272497 # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu2.data 9841405614 # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 12016678111 # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 423668250 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 1137848378 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1561516628 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 146500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 55999 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 202499 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 19407147545 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 55691707059 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 75098854604 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 22314698045 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 64974352749 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 87289050794 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 887936500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1414128501 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2302065001 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 802092250 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1441281461 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2243373711 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1690028750 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2855409962 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4545438712 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032284 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.031796 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017219 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015013 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.013530 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007316 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.768833 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.752492 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.385346 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.726609 # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu2.data 0.719371 # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.304444 # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056805 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.061626 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.031219 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000003 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000003 # mshr miss rate for StoreCondReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024105 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023439 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.012573 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028135 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.027092 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.014570 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13163.135553 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15040.390210 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14515.543148 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27107.905380 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34133.011724 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31944.684550 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14912.350751 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 20706.140677 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18950.062477 # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 15658.567201 # average WriteInvalidateReq mshr miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data 29165.855970 # average WriteInvalidateReq mshr miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25226.679048 # average WriteInvalidateReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12226.372215 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12637.002899 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12522.889240 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 73250 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 13999.750000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 33749.833333 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17276.228426 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20082.414006 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19273.403325 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16926.617244 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20169.212845 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19227.586433 # average overall mshr miss latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.icache.tags.replacements 14506041 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.977027 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 610832898 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 14506553 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 42.107377 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 9058180500 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 497.195368 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 4.341031 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst 10.440628 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.971085 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.008479 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.020392 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999955 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 195 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 73 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 640265260 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 640265260 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 414440150 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 132748322 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 63644426 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 610832898 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 414440150 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 132748322 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 63644426 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 610832898 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 414440150 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 132748322 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 63644426 # number of overall hits
system.cpu0.icache.overall_hits::total 610832898 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 6622096 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 2064308 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 6239288 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 14925692 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 6622096 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 2064308 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst 6239288 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 14925692 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 6622096 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 2064308 # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst 6239288 # number of overall misses
system.cpu0.icache.overall_misses::total 14925692 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 27633797750 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 83140755110 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 110774552860 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 27633797750 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst 83140755110 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 110774552860 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 27633797750 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst 83140755110 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 110774552860 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 421062246 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 134812630 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 69883714 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 625758590 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 421062246 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 134812630 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 69883714 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 625758590 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 421062246 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 134812630 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 69883714 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 625758590 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015727 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015312 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.089281 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.023852 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015727 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015312 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.089281 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.023852 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015727 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015312 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.089281 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.023852 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13386.470309 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13325.359418 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 7421.736484 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13386.470309 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13325.359418 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 7421.736484 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13386.470309 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13325.359418 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 7421.736484 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 42469 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 3518 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.071916 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 419022 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 419022 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst 419022 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 419022 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst 419022 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 419022 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 2064308 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 5820266 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 7884574 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 2064308 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst 5820266 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 7884574 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 2064308 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst 5820266 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 7884574 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 23501092750 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 67935136085 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 91436228835 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 23501092750 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 67935136085 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 91436228835 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 23501092750 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 67935136085 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 91436228835 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015312 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.083285 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012600 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015312 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.083285 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.012600 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015312 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.083285 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.012600 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11384.489500 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11672.170324 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11596.850868 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11384.489500 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11672.170324 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11596.850868 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11384.489500 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11672.170324 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11596.850868 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.dtb.read_hits 25401715 # DTB read hits
system.cpu1.dtb.read_misses 30145 # DTB read misses
system.cpu1.dtb.write_hits 22878884 # DTB write hits
system.cpu1.dtb.write_misses 9290 # DTB write misses
system.cpu1.dtb.flush_tlb 1276 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.dtb.flush_tlb_mva_asid 6765 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 155 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 21663 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.dtb.prefetch_faults 1295 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.dtb.perms_faults 3011 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 25431860 # DTB read accesses
system.cpu1.dtb.write_accesses 22888174 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.dtb.hits 48280599 # DTB hits
system.cpu1.dtb.misses 39435 # DTB misses
system.cpu1.dtb.accesses 48320034 # DTB accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.itb.inst_hits 134812630 # ITB inst hits
system.cpu1.itb.inst_misses 23831 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.itb.flush_tlb 1276 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.itb.flush_tlb_mva_asid 6765 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 155 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 16095 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.itb.inst_accesses 134836461 # ITB inst accesses
system.cpu1.itb.hits 134812630 # DTB hits
system.cpu1.itb.misses 23831 # DTB misses
system.cpu1.itb.accesses 134836461 # DTB accesses
system.cpu1.numCycles 1276129163 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.committedInsts 134717323 # Number of instructions committed
system.cpu1.committedOps 158229449 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 145215192 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 135383 # Number of float alu accesses
system.cpu1.num_func_calls 7898602 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 20639469 # number of instructions that are conditional controls
system.cpu1.num_int_insts 145215192 # number of integer instructions
system.cpu1.num_fp_insts 135383 # number of float instructions
system.cpu1.num_int_register_reads 211626069 # number of times the integer registers were read
system.cpu1.num_int_register_writes 115298933 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 217457 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 117636 # number of times the floating registers were written
system.cpu1.num_cc_register_reads 35416182 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 35358802 # number of times the CC registers were written
system.cpu1.num_mem_refs 48278390 # number of memory refs
system.cpu1.num_load_insts 25401257 # Number of load instructions
system.cpu1.num_store_insts 22877133 # Number of store instructions
system.cpu1.num_idle_cycles 1248602360.762588 # Number of idle cycles
system.cpu1.num_busy_cycles 27526802.237412 # Number of busy cycles
system.cpu1.not_idle_fraction 0.021571 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.978429 # Percentage of idle cycles
system.cpu1.Branches 30073331 # Number of branches fetched
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.op_class::IntAlu 109658909 69.26% 69.26% # Class of executed instruction
system.cpu1.op_class::IntMult 355788 0.22% 69.49% # Class of executed instruction
system.cpu1.op_class::IntDiv 13920 0.01% 69.50% # Class of executed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 69.50% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 69.50% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 69.50% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 69.50% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 69.50% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 69.50% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 69.50% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 69.50% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 69.50% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 69.50% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.50% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 69.50% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.50% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.50% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.50% # Class of executed instruction
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.op_class::SimdFloatCvt 20 0.00% 69.50% # Class of executed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.50% # Class of executed instruction
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.op_class::SimdFloatMisc 17708 0.01% 69.51% # Class of executed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.op_class::MemRead 25401257 16.04% 85.55% # Class of executed instruction
system.cpu1.op_class::MemWrite 22877133 14.45% 100.00% # Class of executed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.op_class::total 158324756 # Class of executed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu2.branchPred.lookups 96972708 # Number of BP lookups
system.cpu2.branchPred.condPredicted 66097998 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 4361259 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 65994487 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 47080178 # Number of BTB hits
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu2.branchPred.BTBHitPct 71.339562 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 12396082 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 131444 # Number of incorrect RAS predictions.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu2.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu2.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu2.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu2.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu2.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu2.dtb.read_hits 77639620 # DTB read hits
system.cpu2.dtb.read_misses 447330 # DTB read misses
system.cpu2.dtb.write_hits 59480935 # DTB write hits
system.cpu2.dtb.write_misses 199454 # DTB write misses
system.cpu2.dtb.flush_tlb 1277 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu2.dtb.flush_tlb_mva_asid 14382 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid 391 # Number of times TLB was flushed by ASID
system.cpu2.dtb.flush_entries 38430 # Number of entries that have been flushed from TLB
system.cpu2.dtb.align_faults 78 # Number of TLB faults due to alignment restrictions
system.cpu2.dtb.prefetch_faults 6154 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu2.dtb.perms_faults 38837 # Number of TLB faults due to permissions restrictions
system.cpu2.dtb.read_accesses 78086950 # DTB read accesses
system.cpu2.dtb.write_accesses 59680389 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu2.dtb.hits 137120555 # DTB hits
system.cpu2.dtb.misses 646784 # DTB misses
system.cpu2.dtb.accesses 137767339 # DTB accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu2.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu2.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu2.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu2.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu2.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu2.itb.inst_hits 70053409 # ITB inst hits
system.cpu2.itb.inst_misses 78615 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu2.itb.flush_tlb 1277 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu2.itb.flush_tlb_mva_asid 14382 # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid 391 # Number of times TLB was flushed by ASID
system.cpu2.itb.flush_entries 29938 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu2.itb.perms_faults 146701 # Number of TLB faults due to permissions restrictions
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_accesses 0 # DTB write accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu2.itb.inst_accesses 70132024 # ITB inst accesses
system.cpu2.itb.hits 70053409 # DTB hits
system.cpu2.itb.misses 78615 # DTB misses
system.cpu2.itb.accesses 70132024 # DTB accesses
system.cpu2.numCycles 464363800 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu2.fetch.icacheStallCycles 179489584 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 430854602 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 96972708 # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches 59476260 # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles 257591256 # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles 9826419 # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles 1844126 # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.MiscStallCycles 7503 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles 2868 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles 3763568 # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles 118840 # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles 3975 # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines 69883749 # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes 2672352 # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.ItlbSquashes 30337 # Number of outstanding ITLB misses that were squashed
system.cpu2.fetch.rateDist::samples 447734787 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean 1.124399 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev 2.366335 # Number of instructions fetched each cycle (Total)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu2.fetch.rateDist::0 341635028 76.30% 76.30% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1 13406310 2.99% 79.30% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2 13636635 3.05% 82.34% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3 9872032 2.20% 84.55% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4 19981367 4.46% 89.01% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5 6599798 1.47% 90.48% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6 7144304 1.60% 92.08% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7 6328128 1.41% 93.49% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8 29131185 6.51% 100.00% # Number of instructions fetched each cycle (Total)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu2.fetch.rateDist::total 447734787 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate 0.208829 # Number of branch fetches per cycle
system.cpu2.fetch.rate 0.927838 # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles 146627317 # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles 209331987 # Number of cycles decode is blocked
system.cpu2.decode.RunCycles 78382912 # Number of cycles decode is running
system.cpu2.decode.UnblockCycles 9473245 # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles 3917341 # Number of cycles decode is squashing
system.cpu2.decode.BranchResolved 14361500 # Number of times decode resolved a branch
system.cpu2.decode.BranchMispred 1009950 # Number of times decode detected a branch misprediction
system.cpu2.decode.DecodedInsts 470418171 # Number of instructions handled by decode
system.cpu2.decode.SquashedInsts 3106090 # Number of squashed instructions handled by decode
system.cpu2.rename.SquashCycles 3917341 # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles 152067726 # Number of cycles rename is idle
system.cpu2.rename.BlockCycles 18239112 # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles 166025180 # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles 82266415 # Number of cycles rename is running
system.cpu2.rename.UnblockCycles 25216691 # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts 459074168 # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents 65027 # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents 1852942 # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents 1258209 # Number of times rename has blocked due to LQ full
system.cpu2.rename.SQFullEvents 11783264 # Number of times rename has blocked due to SQ full
system.cpu2.rename.FullRegisterEvents 3675 # Number of times there has been no free registers
system.cpu2.rename.RenamedOperands 439034296 # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups 699577887 # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups 541505861 # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups 695779 # Number of floating rename lookups
system.cpu2.rename.CommittedMaps 366271083 # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps 72763213 # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts 10011965 # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts 8575733 # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts 52414102 # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads 74518711 # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores 62619461 # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads 9405778 # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores 10283621 # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded 436211457 # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded 9985811 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 434881060 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 606856 # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined 56709441 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 39627449 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 236091 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 447734787 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean 0.971292 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev 1.683506 # Number of insts issued each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu2.iq.issued_per_cycle::0 279611354 62.45% 62.45% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1 68418670 15.28% 77.73% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2 31957007 7.14% 84.87% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3 22824194 5.10% 89.97% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4 17260103 3.85% 93.82% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5 11876528 2.65% 96.47% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6 7949958 1.78% 98.25% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7 4742790 1.06% 99.31% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8 3094183 0.69% 100.00% # Number of insts issued each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu2.iq.issued_per_cycle::total 447734787 # Number of insts issued each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu2.iq.fu_full::IntAlu 2194515 25.29% 25.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult 17472 0.20% 25.49% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv 1369 0.02% 25.50% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 25.50% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 25.50% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 25.50% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult 0 0.00% 25.50% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 25.50% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 25.50% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 25.50% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 25.50% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 25.50% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 25.50% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 25.50% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 25.50% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult 0 0.00% 25.50% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 25.50% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift 0 0.00% 25.50% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 25.50% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 25.50% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 25.50% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 25.50% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 25.50% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 25.50% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 25.50% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc 1 0.00% 25.50% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 25.50% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.50% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 25.50% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead 3568581 41.12% 66.62% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite 2897037 33.38% 100.00% # attempts to use FU when none available
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu2.iq.FU_type_0::IntAlu 294218561 67.65% 67.65% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult 1060208 0.24% 67.90% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv 49487 0.01% 67.91% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd 203 0.00% 67.91% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 67.91% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 67.91% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 67.91% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 67.91% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 67.91% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 67.91% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 67.91% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 67.91% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 67.91% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 67.91% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 67.91% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 67.91% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 67.91% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 67.91% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.91% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 67.91% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.91% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.91% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.91% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.91% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.91% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc 49890 0.01% 67.92% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 67.92% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.92% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.92% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead 79213886 18.22% 86.14% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite 60288825 13.86% 100.00% # Type of FU issued
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu2.iq.FU_type_0::total 434881060 # Type of FU issued
system.cpu2.iq.rate 0.936509 # Inst issue rate
system.cpu2.iq.fu_busy_cnt 8678975 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.019957 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 1325952907 # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes 503003259 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 418204813 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 829831 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 395434 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 359511 # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses 443116084 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 443951 # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads 3398365 # Number of loads that had data forwarded from stores
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu2.iew.lsq.thread0.squashedLoads 12383710 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 15996 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation 500564 # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores 6611339 # Number of stores squashed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu2.iew.lsq.thread0.rescheduledLoads 2691934 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 6258076 # Number of times an access to memory failed due to the cache being blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu2.iew.iewSquashCycles 3917341 # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles 10960428 # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles 5883186 # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts 446296417 # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts 1350381 # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts 74518711 # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts 62619461 # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts 8384922 # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents 176072 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 5630257 # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents 500564 # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect 2018361 # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect 1727301 # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts 3745662 # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts 429773841 # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts 77626990 # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts 4469356 # Number of squashed instructions skipped in execute
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.iew.exec_swp 0 # number of swp insts executed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu2.iew.exec_nop 99149 # number of nop insts executed
system.cpu2.iew.exec_refs 137107534 # number of memory reference insts executed
system.cpu2.iew.exec_branches 79765421 # Number of branches executed
system.cpu2.iew.exec_stores 59480544 # Number of stores executed
system.cpu2.iew.exec_rate 0.925511 # Inst execution rate
system.cpu2.iew.wb_sent 419443427 # cumulative count of insts sent to commit
system.cpu2.iew.wb_count 418564324 # cumulative count of insts written-back
system.cpu2.iew.wb_producers 206922501 # num instructions producing a value
system.cpu2.iew.wb_consumers 359375214 # num instructions consuming a value
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu2.iew.wb_rate 0.901372 # insts written-back per cycle
system.cpu2.iew.wb_fanout 0.575784 # average fanout of values written-back
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu2.commit.commitSquashedInsts 60955622 # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls 9749720 # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts 3365248 # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples 437429844 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean 0.880802 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev 1.877626 # Number of insts commited each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu2.commit.committed_per_cycle::0 298552711 68.25% 68.25% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1 66327454 15.16% 83.41% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2 24603217 5.62% 89.04% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3 11085486 2.53% 91.57% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4 7951378 1.82% 93.39% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5 4924801 1.13% 94.52% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6 4385642 1.00% 95.52% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7 3037837 0.69% 96.21% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8 16561318 3.79% 100.00% # Number of insts commited each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu2.commit.committed_per_cycle::total 437429844 # Number of insts commited each cycle
system.cpu2.commit.committedInsts 328410291 # Number of instructions committed
system.cpu2.commit.committedOps 385289118 # Number of ops (including micro ops) committed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu2.commit.refs 118143123 # Number of memory references committed
system.cpu2.commit.loads 62135001 # Number of loads committed
system.cpu2.commit.membars 2566531 # Number of memory barriers committed
system.cpu2.commit.branches 73369628 # Number of branches committed
system.cpu2.commit.fp_insts 345769 # Number of committed floating point instructions.
system.cpu2.commit.int_insts 353907438 # Number of committed integer instructions.
system.cpu2.commit.function_calls 9528374 # Number of function calls committed.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu2.commit.op_class_0::IntAlu 266264239 69.11% 69.11% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult 801904 0.21% 69.32% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv 36966 0.01% 69.33% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 69.33% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 69.33% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 69.33% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult 0 0.00% 69.33% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 69.33% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 69.33% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 69.33% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 69.33% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 69.33% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 69.33% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 69.33% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 69.33% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult 0 0.00% 69.33% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 69.33% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift 0 0.00% 69.33% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 69.33% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 69.33% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 69.33% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 69.33% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 69.33% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 69.33% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 69.33% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc 42886 0.01% 69.34% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 69.34% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.34% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.34% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead 62135001 16.13% 85.46% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite 56008122 14.54% 100.00% # Class of committed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu2.commit.op_class_0::total 385289118 # Class of committed instruction
system.cpu2.commit.bw_lim_events 16561318 # number cycles where commit BW limit reached
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu2.rob.rob_reads 864512984 # The number of ROB reads
system.cpu2.rob.rob_writes 902807617 # The number of ROB writes
system.cpu2.timesIdled 2960923 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles 16629013 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 99452987332 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts 328410291 # Number of Instructions Simulated
system.cpu2.committedOps 385289118 # Number of Ops (including micro ops) Simulated
system.cpu2.cpi 1.413975 # CPI: Cycles Per Instruction
system.cpu2.cpi_total 1.413975 # CPI: Total CPI of All Threads
system.cpu2.ipc 0.707226 # IPC: Instructions Per Cycle
system.cpu2.ipc_total 0.707226 # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads 505452117 # number of integer regfile reads
system.cpu2.int_regfile_writes 299365113 # number of integer regfile writes
system.cpu2.fp_regfile_reads 681432 # number of floating regfile reads
system.cpu2.fp_regfile_writes 426556 # number of floating regfile writes
system.cpu2.cc_regfile_reads 91860984 # number of cc regfile reads
system.cpu2.cc_regfile_writes 92633679 # number of cc regfile writes
system.cpu2.misc_regfile_reads 1668736685 # number of misc regfile reads
system.cpu2.misc_regfile_writes 9854923 # number of misc regfile writes
system.iobus.trans_dist::ReadReq 40323 # Transaction distribution
system.iobus.trans_dist::ReadResp 40323 # Transaction distribution
system.iobus.trans_dist::WriteReq 136665 # Transaction distribution
system.iobus.trans_dist::WriteResp 30001 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48070 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230944 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 230944 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 353976 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48090 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 156082 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334208 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7334208 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 7492376 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 13663000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 7273000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 33000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 16992000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 330247943 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 38409000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 36054619 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 144000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 115453 # number of replacements
system.iocache.tags.tagsinuse 10.417239 # Cycle average of tags in use
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.tags.sampled_refs 115469 # Sample count of references to valid blocks.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.tags.warmup_cycle 13085938891009 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.549977 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 6.867262 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.221874 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.429204 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.651077 # Average percentage of cache occupancy
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.tags.tag_accesses 1039605 # Number of tag accesses
system.iocache.tags.data_accesses 1039605 # Number of data accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.ReadReq_misses::realview.ide 8808 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8845 # number of ReadReq misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.demand_misses::realview.ide 8808 # number of demand (read+write) misses
system.iocache.demand_misses::total 8848 # number of demand (read+write) misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.overall_misses::realview.ide 8808 # number of overall misses
system.iocache.overall_misses::total 8848 # number of overall misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_miss_latency::realview.ethernet 2752000 # number of ReadReq miss cycles
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.ReadReq_miss_latency::realview.ide 58617716 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 61369716 # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9336377608 # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total 9336377608 # number of WriteInvalidateReq miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_miss_latency::realview.ethernet 2752000 # number of demand (read+write) miss cycles
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.demand_miss_latency::realview.ide 58617716 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 61369716 # number of demand (read+write) miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_miss_latency::realview.ethernet 2752000 # number of overall miss cycles
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.overall_miss_latency::realview.ide 58617716 # number of overall miss cycles
system.iocache.overall_miss_latency::total 61369716 # number of overall miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.ReadReq_accesses::realview.ide 8808 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8845 # number of ReadReq accesses(hits+misses)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.demand_accesses::realview.ide 8808 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8848 # number of demand (read+write) accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.overall_accesses::realview.ide 8808 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8848 # number of overall (read+write) accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 74378.378378 # average ReadReq miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.ReadReq_avg_miss_latency::realview.ide 6655.054042 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 6938.351159 # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 87530.728343 # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 87530.728343 # average WriteInvalidateReq miss latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_avg_miss_latency::realview.ethernet 68800 # average overall miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.demand_avg_miss_latency::realview.ide 6655.054042 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 6935.998644 # average overall miss latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_avg_miss_latency::realview.ethernet 68800 # average overall miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.overall_avg_miss_latency::realview.ide 6655.054042 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 6935.998644 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 56930 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.blocked::no_mshrs 7229 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 7.875225 # average number of cycles each access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.writebacks::writebacks 106630 # number of writebacks
system.iocache.writebacks::total 106630 # number of writebacks
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_misses::realview.ethernet 16 # number of ReadReq MSHR misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.ReadReq_mshr_misses::realview.ide 391 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 407 # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 34376 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 34376 # number of WriteInvalidateReq MSHR misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_misses::realview.ethernet 16 # number of demand (read+write) MSHR misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.demand_mshr_misses::realview.ide 391 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 407 # number of demand (read+write) MSHR misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_mshr_misses::realview.ethernet 16 # number of overall MSHR misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.overall_mshr_misses::realview.ide 391 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 407 # number of overall MSHR misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 1920000 # number of ReadReq MSHR miss cycles
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.ReadReq_mshr_miss_latency::realview.ide 38284716 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 40204716 # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7548587846 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7548587846 # number of WriteInvalidateReq MSHR miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_miss_latency::realview.ethernet 1920000 # number of demand (read+write) MSHR miss cycles
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.demand_mshr_miss_latency::realview.ide 38284716 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 40204716 # number of demand (read+write) MSHR miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_mshr_miss_latency::realview.ethernet 1920000 # number of overall MSHR miss cycles
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.overall_mshr_miss_latency::realview.ide 38284716 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 40204716 # number of overall MSHR miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 0.432432 # mshr miss rate for ReadReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.044391 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.046015 # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 0.322283 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.322283 # mshr miss rate for WriteInvalidateReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_miss_rate::realview.ethernet 0.400000 # mshr miss rate for demand accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.demand_mshr_miss_rate::realview.ide 0.044391 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 0.045999 # mshr miss rate for demand accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_mshr_miss_rate::realview.ethernet 0.400000 # mshr miss rate for overall accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.overall_mshr_miss_rate::realview.ide 0.044391 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 0.045999 # mshr miss rate for overall accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 120000 # average ReadReq mshr miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 97914.874680 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 98783.085995 # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219588.894752 # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219588.894752 # average WriteInvalidateReq mshr miss latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 120000 # average overall mshr miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.demand_avg_mshr_miss_latency::realview.ide 97914.874680 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 98783.085995 # average overall mshr miss latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 120000 # average overall mshr miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.overall_avg_mshr_miss_latency::realview.ide 97914.874680 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 98783.085995 # average overall mshr miss latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.l2c.tags.replacements 1295349 # number of replacements
system.l2c.tags.tagsinuse 65279.372199 # Cycle average of tags in use
system.l2c.tags.total_refs 28812912 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1358291 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 21.212621 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 37161.709727 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 165.709328 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 242.089797 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 3863.683177 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 8425.677492 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 52.724328 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 79.048207 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 858.449063 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 3027.055416 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker 115.755562 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.itb.walker 187.843721 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 2139.828130 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 8959.798251 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.567043 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002529 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.003694 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.058955 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.128566 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000805 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.001206 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.013099 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.046189 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker 0.001766 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.itb.walker 0.002866 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.032651 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.136716 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.996084 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 299 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 62643 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 299 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 576 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 2774 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 4979 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 54179 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.004562 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.955856 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 273263421 # Number of tag accesses
system.l2c.tags.data_accesses 273263421 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 201117 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 129157 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 6577739 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 3133333 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 70837 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 49793 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 2053111 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 984012 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker 392546 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker 149888 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst 5786914 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data 2465786 # number of ReadReq hits
system.l2c.ReadReq_hits::total 21994233 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 7869277 # number of Writeback hits
system.l2c.Writeback_hits::total 7869277 # number of Writeback hits
system.l2c.WriteInvalidateReq_hits::cpu0.data 350049 # number of WriteInvalidateReq hits
system.l2c.WriteInvalidateReq_hits::cpu1.data 108782 # number of WriteInvalidateReq hits
system.l2c.WriteInvalidateReq_hits::cpu2.data 265889 # number of WriteInvalidateReq hits
system.l2c.WriteInvalidateReq_hits::total 724720 # number of WriteInvalidateReq hits
system.l2c.UpgradeReq_hits::cpu0.data 4870 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 1538 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data 3474 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 9882 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu2.data 3 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 805786 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 246665 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data 552298 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 1604749 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 201117 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 129157 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 6577739 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 3939119 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 70837 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 49793 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 2053111 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 1230677 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker 392546 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker 149888 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 5786914 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 3018084 # number of demand (read+write) hits
system.l2c.demand_hits::total 23598982 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 201117 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 129157 # number of overall hits
system.l2c.overall_hits::cpu0.inst 6577739 # number of overall hits
system.l2c.overall_hits::cpu0.data 3939119 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 70837 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 49793 # number of overall hits
system.l2c.overall_hits::cpu1.inst 2053111 # number of overall hits
system.l2c.overall_hits::cpu1.data 1230677 # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker 392546 # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker 149888 # number of overall hits
system.l2c.overall_hits::cpu2.inst 5786914 # number of overall hits
system.l2c.overall_hits::cpu2.data 3018084 # number of overall hits
system.l2c.overall_hits::total 23598982 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 1985 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 1949 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 44357 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 135315 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 578 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker 479 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 11197 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 37623 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker 1473 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.itb.walker 1443 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst 33232 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data 109198 # number of ReadReq misses
system.l2c.ReadReq_misses::total 378829 # number of ReadReq misses
system.l2c.WriteInvalidateReq_misses::cpu0.data 405013 # number of WriteInvalidateReq misses
system.l2c.WriteInvalidateReq_misses::cpu1.data 30137 # number of WriteInvalidateReq misses
system.l2c.WriteInvalidateReq_misses::cpu2.data 71540 # number of WriteInvalidateReq misses
system.l2c.WriteInvalidateReq_misses::total 506690 # number of WriteInvalidateReq misses
system.l2c.UpgradeReq_misses::cpu0.data 17469 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 5625 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 12633 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 35727 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu2.data 1 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 4 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 257234 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 77509 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 168114 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 502857 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 1985 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 1949 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 44357 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 392549 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 578 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 479 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 11197 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 115132 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker 1473 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.itb.walker 1443 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst 33232 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 277312 # number of demand (read+write) misses
system.l2c.demand_misses::total 881686 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 1985 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 1949 # number of overall misses
system.l2c.overall_misses::cpu0.inst 44357 # number of overall misses
system.l2c.overall_misses::cpu0.data 392549 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 578 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 479 # number of overall misses
system.l2c.overall_misses::cpu1.inst 11197 # number of overall misses
system.l2c.overall_misses::cpu1.data 115132 # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker 1473 # number of overall misses
system.l2c.overall_misses::cpu2.itb.walker 1443 # number of overall misses
system.l2c.overall_misses::cpu2.inst 33232 # number of overall misses
system.l2c.overall_misses::cpu2.data 277312 # number of overall misses
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system.l2c.overall_mshr_misses::cpu2.inst 33232 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data 277308 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 440809 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 37895750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 31757500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 686314500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 2382171250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 97090496 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 101432248 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 2196003250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 8117820950 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 13650485944 # number of ReadReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 616367003 # number of WriteInvalidateReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu2.data 1933767537 # number of WriteInvalidateReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::total 2550134540 # number of WriteInvalidateReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 56255625 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 126429131 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 182684756 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 120500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 10001 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 130501 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4766611080 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 14083669373 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 18850280453 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 37895750 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 31757500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 686314500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 7148782330 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 97090496 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 101432248 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 2196003250 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 22201490323 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 32500766397 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 37895750 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 31757500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 686314500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 7148782330 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 97090496 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 101432248 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst 2196003250 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data 22201490323 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 32500766397 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 816699000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1310911000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 2127610000 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 743754000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 1345310999 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 2089064999 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1560453000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 2656221999 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 4216674999 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.008094 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.009528 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005424 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.036826 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.003710 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.009390 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.005710 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.042406 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.008724 # mshr miss rate for ReadReq accesses
system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.216939 # mshr miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu2.data 0.212015 # mshr miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.082570 # mshr miss rate for WriteInvalidateReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.785285 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.784317 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.400316 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.250000 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.428571 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.239097 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.233358 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.116541 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.008094 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.009528 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005424 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.085549 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003710 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.009390 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.005710 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.084150 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.018006 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.008094 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.009528 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005424 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.085549 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003710 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.009390 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005710 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.084150 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.018006 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 65563.581315 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 66299.582463 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61294.498526 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63316.887276 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 66409.367989 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 71380.892329 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 66080.983690 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 74343.104475 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 69935.784042 # average ReadReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 20452.168530 # average WriteInvalidateReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data 27030.577817 # average WriteInvalidateReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 25080.741367 # average WriteInvalidateReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10007.846988 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10005.737540 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 60250 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 43500.333333 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61497.517450 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 83774.518321 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 76744.769232 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 65563.581315 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 66299.582463 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61294.498526 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62092.053730 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 66409.367989 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 71380.892329 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 66080.983690 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 80060.763927 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 73729.815854 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 65563.581315 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 66299.582463 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61294.498526 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62092.053730 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 66409.367989 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 71380.892329 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 66080.983690 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 80060.763927 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 73729.815854 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 464434 # Transaction distribution
system.membus.trans_dist::ReadResp 464434 # Transaction distribution
system.membus.trans_dist::WriteReq 33772 # Transaction distribution
system.membus.trans_dist::WriteResp 33772 # Transaction distribution
system.membus.trans_dist::Writeback 1204397 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 613284 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 613284 # Transaction distribution
system.membus.trans_dist::UpgradeReq 36382 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution
system.membus.trans_dist::UpgradeResp 36386 # Transaction distribution
system.membus.trans_dist::ReadExReq 502275 # Transaction distribution
system.membus.trans_dist::ReadExResp 502275 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122952 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6750 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4037051 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 4166813 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337307 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 337307 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4504120 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156082 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 196 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13500 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 159247392 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 159417170 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14194688 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 14194688 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 173611858 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 579 # Total snoops (count)
system.membus.snoop_fanout::samples 2743991 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 2743991 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 2743991 # Request fanout histogram
system.membus.reqLayer0.occupancy 42257500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 1290500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 6097591000 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 4309666748 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 38158381 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.toL2Bus.trans_dist::ReadReq 22879889 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 22879700 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 33772 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 33772 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 7869277 # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq 1265786 # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateResp 1231410 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 45609 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 45616 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 2107606 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 2107606 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 29099470 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 28504181 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 848529 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1761011 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 60213191 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 928591700 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1156912126 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3110208 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6320128 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 2094934162 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 368424 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 34177702 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 5.003380 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.058037 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::5 34062190 99.66% 99.66% # Request fanout histogram
system.toL2Bus.snoop_fanout::6 115512 0.34% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 34177702 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 26362663917 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 981000 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 35502866905 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 21222039348 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 273701566 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 651522269 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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