sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
gem5/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt

955 lines
104 KiB
Text
Raw Normal View History

add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
---------- Begin Simulation Statistics ----------
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
sim_seconds 0.200409 # Number of seconds simulated
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
sim_ticks 200409284500 # Number of ticks simulated
final_tick 4321214250500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
host_inst_rate 14275836 # Simulator instruction rate (inst/s)
host_op_rate 14275831 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5462126987 # Simulator tick rate (ticks/s)
host_mem_usage 513712 # Number of bytes of host memory used
host_seconds 36.69 # Real time elapsed on the host
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
sim_insts 523790075 # Number of instructions simulated
sim_ops 523790075 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
testsys.voltage_domain.voltage 1 # Voltage in Volts
testsys.clk_domain.clock 1000 # Clock period in ticks
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.physmem.bytes_read::cpu.inst 81046720 # Number of bytes read from this memory
testsys.physmem.bytes_read::cpu.data 27826276 # Number of bytes read from this memory
testsys.physmem.bytes_read::tsunami.ethernet 57260496 # Number of bytes read from this memory
testsys.physmem.bytes_read::total 166133492 # Number of bytes read from this memory
testsys.physmem.bytes_inst_read::cpu.inst 81046720 # Number of instructions bytes read from this memory
testsys.physmem.bytes_inst_read::total 81046720 # Number of instructions bytes read from this memory
testsys.physmem.bytes_written::cpu.data 16606680 # Number of bytes written to this memory
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
testsys.physmem.bytes_written::tsunami.ethernet 902 # Number of bytes written to this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.physmem.bytes_written::total 16607582 # Number of bytes written to this memory
testsys.physmem.num_reads::cpu.inst 20261680 # Number of read requests responded to by this memory
testsys.physmem.num_reads::cpu.data 3842559 # Number of read requests responded to by this memory
testsys.physmem.num_reads::tsunami.ethernet 2385836 # Number of read requests responded to by this memory
testsys.physmem.num_reads::total 26490075 # Number of read requests responded to by this memory
testsys.physmem.num_writes::cpu.data 2258392 # Number of write requests responded to by this memory
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
testsys.physmem.num_writes::tsunami.ethernet 31 # Number of write requests responded to by this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.physmem.num_writes::total 2258423 # Number of write requests responded to by this memory
testsys.physmem.bw_read::cpu.inst 404406014 # Total read bandwidth from this memory (bytes/s)
testsys.physmem.bw_read::cpu.data 138847240 # Total read bandwidth from this memory (bytes/s)
testsys.physmem.bw_read::tsunami.ethernet 285717781 # Total read bandwidth from this memory (bytes/s)
testsys.physmem.bw_read::total 828971035 # Total read bandwidth from this memory (bytes/s)
testsys.physmem.bw_inst_read::cpu.inst 404406014 # Instruction read bandwidth from this memory (bytes/s)
testsys.physmem.bw_inst_read::total 404406014 # Instruction read bandwidth from this memory (bytes/s)
testsys.physmem.bw_write::cpu.data 82863826 # Write bandwidth from this memory (bytes/s)
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
testsys.physmem.bw_write::tsunami.ethernet 4501 # Write bandwidth from this memory (bytes/s)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.physmem.bw_write::total 82868326 # Write bandwidth from this memory (bytes/s)
testsys.physmem.bw_total::cpu.inst 404406014 # Total bandwidth to/from this memory (bytes/s)
testsys.physmem.bw_total::cpu.data 221711065 # Total bandwidth to/from this memory (bytes/s)
testsys.physmem.bw_total::tsunami.ethernet 285722281 # Total bandwidth to/from this memory (bytes/s)
testsys.physmem.bw_total::total 911839361 # Total bandwidth to/from this memory (bytes/s)
testsys.membus.throughput 916540501 # Throughput (bytes/s)
testsys.membus.data_through_bus 183683226 # Total data (bytes)
testsys.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
testsys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes.
testsys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
testsys.disk0.dma_write_txs 0 # Number of DMA write transactions.
testsys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
testsys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
testsys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
testsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
testsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
testsys.disk2.dma_write_txs 0 # Number of DMA write transactions.
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
testsys.cpu.clk_domain.clock 500 # Clock period in ticks
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
testsys.cpu.dtb.fetch_hits 0 # ITB hits
testsys.cpu.dtb.fetch_misses 0 # ITB misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.dtb.fetch_acv 0 # ITB acv
testsys.cpu.dtb.fetch_accesses 0 # ITB accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.cpu.dtb.read_hits 3916918 # DTB read hits
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
testsys.cpu.dtb.read_misses 3287 # DTB read misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.dtb.read_acv 80 # DTB read access violations
testsys.cpu.dtb.read_accesses 225414 # DTB read accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.cpu.dtb.write_hits 2316885 # DTB write hits
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
testsys.cpu.dtb.write_misses 528 # DTB write misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.dtb.write_acv 81 # DTB write access violations
testsys.cpu.dtb.write_accesses 109988 # DTB write accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.cpu.dtb.data_hits 6233803 # DTB hits
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.dtb.data_misses 3815 # DTB misses
testsys.cpu.dtb.data_acv 161 # DTB access violations
testsys.cpu.dtb.data_accesses 335402 # DTB accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.cpu.itb.fetch_hits 4052211 # ITB hits
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
testsys.cpu.itb.fetch_misses 1497 # ITB misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.itb.fetch_acv 69 # ITB acv
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.cpu.itb.fetch_accesses 4053708 # ITB accesses
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
testsys.cpu.itb.read_hits 0 # DTB read hits
testsys.cpu.itb.read_misses 0 # DTB read misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.itb.read_acv 0 # DTB read access violations
testsys.cpu.itb.read_accesses 0 # DTB read accesses
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
testsys.cpu.itb.write_hits 0 # DTB write hits
testsys.cpu.itb.write_misses 0 # DTB write misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.itb.write_acv 0 # DTB write access violations
testsys.cpu.itb.write_accesses 0 # DTB write accesses
testsys.cpu.itb.data_hits 0 # DTB hits
testsys.cpu.itb.data_misses 0 # DTB misses
testsys.cpu.itb.data_acv 0 # DTB access violations
testsys.cpu.itb.data_accesses 0 # DTB accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.cpu.numCycles 400804755 # number of cpu cycles simulated
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.cpu.committedInsts 20257704 # Number of instructions committed
testsys.cpu.committedOps 20257704 # Number of ops (including micro ops) committed
testsys.cpu.num_int_alu_accesses 18837017 # Number of integer alu accesses
testsys.cpu.num_fp_alu_accesses 17380 # Number of float alu accesses
testsys.cpu.num_func_calls 1221180 # number of times a function call or return occured
testsys.cpu.num_conditional_control_insts 1442148 # number of instructions that are conditional controls
testsys.cpu.num_int_insts 18837017 # number of integer instructions
testsys.cpu.num_fp_insts 17380 # number of float instructions
testsys.cpu.num_int_register_reads 24787248 # number of times the integer registers were read
testsys.cpu.num_int_register_writes 14693875 # number of times the integer registers were written
testsys.cpu.num_fp_register_reads 11166 # number of times the floating registers were read
testsys.cpu.num_fp_register_writes 10823 # number of times the floating registers were written
testsys.cpu.num_mem_refs 6263046 # number of memory refs
testsys.cpu.num_load_insts 3944033 # Number of load instructions
testsys.cpu.num_store_insts 2319013 # Number of store instructions
testsys.cpu.num_idle_cycles 380542207.362158 # Number of idle cycles
testsys.cpu.num_busy_cycles 20262547.637842 # Number of busy cycles
testsys.cpu.not_idle_fraction 0.050555 # Percentage of non-idle cycles
testsys.cpu.idle_fraction 0.949445 # Percentage of idle cycles
stats: updates due to branch predictor warming
2014-02-16 18:40:34 +01:00
testsys.cpu.Branches 2929848 # Number of branches fetched
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
testsys.cpu.op_class::No_OpClass 712819 3.52% 3.52% # Class of executed instruction
testsys.cpu.op_class::IntAlu 12147340 59.95% 63.47% # Class of executed instruction
testsys.cpu.op_class::IntMult 21654 0.11% 63.58% # Class of executed instruction
testsys.cpu.op_class::IntDiv 0 0.00% 63.58% # Class of executed instruction
testsys.cpu.op_class::FloatAdd 4653 0.02% 63.60% # Class of executed instruction
testsys.cpu.op_class::FloatCmp 1 0.00% 63.60% # Class of executed instruction
testsys.cpu.op_class::FloatCvt 0 0.00% 63.60% # Class of executed instruction
testsys.cpu.op_class::FloatMult 0 0.00% 63.60% # Class of executed instruction
testsys.cpu.op_class::FloatDiv 922 0.00% 63.60% # Class of executed instruction
testsys.cpu.op_class::FloatSqrt 0 0.00% 63.60% # Class of executed instruction
testsys.cpu.op_class::SimdAdd 0 0.00% 63.60% # Class of executed instruction
testsys.cpu.op_class::SimdAddAcc 0 0.00% 63.60% # Class of executed instruction
testsys.cpu.op_class::SimdAlu 0 0.00% 63.60% # Class of executed instruction
testsys.cpu.op_class::SimdCmp 0 0.00% 63.60% # Class of executed instruction
testsys.cpu.op_class::SimdCvt 0 0.00% 63.60% # Class of executed instruction
testsys.cpu.op_class::SimdMisc 0 0.00% 63.60% # Class of executed instruction
testsys.cpu.op_class::SimdMult 0 0.00% 63.60% # Class of executed instruction
testsys.cpu.op_class::SimdMultAcc 0 0.00% 63.60% # Class of executed instruction
testsys.cpu.op_class::SimdShift 0 0.00% 63.60% # Class of executed instruction
testsys.cpu.op_class::SimdShiftAcc 0 0.00% 63.60% # Class of executed instruction
testsys.cpu.op_class::SimdSqrt 0 0.00% 63.60% # Class of executed instruction
testsys.cpu.op_class::SimdFloatAdd 0 0.00% 63.60% # Class of executed instruction
testsys.cpu.op_class::SimdFloatAlu 0 0.00% 63.60% # Class of executed instruction
testsys.cpu.op_class::SimdFloatCmp 0 0.00% 63.60% # Class of executed instruction
testsys.cpu.op_class::SimdFloatCvt 0 0.00% 63.60% # Class of executed instruction
testsys.cpu.op_class::SimdFloatDiv 0 0.00% 63.60% # Class of executed instruction
testsys.cpu.op_class::SimdFloatMisc 0 0.00% 63.60% # Class of executed instruction
testsys.cpu.op_class::SimdFloatMult 0 0.00% 63.60% # Class of executed instruction
testsys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.60% # Class of executed instruction
testsys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.60% # Class of executed instruction
testsys.cpu.op_class::MemRead 4230637 20.88% 84.48% # Class of executed instruction
testsys.cpu.op_class::MemWrite 2319552 11.45% 95.93% # Class of executed instruction
testsys.cpu.op_class::IprAccess 824102 4.07% 100.00% # Class of executed instruction
testsys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
testsys.cpu.op_class::total 20261680 # Class of executed instruction
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
testsys.cpu.kern.inst.arm 0 # number of arm instructions executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.cpu.kern.inst.quiesce 19580 # number of quiesce instructions executed
testsys.cpu.kern.inst.hwrei 153667 # number of hwrei instructions executed
testsys.cpu.kern.ipl_count::0 62779 42.67% 42.67% # number of times we switched to this ipl
testsys.cpu.kern.ipl_count::21 19625 13.34% 56.01% # number of times we switched to this ipl
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.cpu.kern.ipl_count::22 205 0.14% 56.15% # number of times we switched to this ipl
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.cpu.kern.ipl_count::31 64509 43.85% 100.00% # number of times we switched to this ipl
testsys.cpu.kern.ipl_count::total 147118 # number of times we switched to this ipl
testsys.cpu.kern.ipl_good::0 62773 43.18% 43.18% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good::21 19625 13.50% 56.67% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good::22 205 0.14% 56.82% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good::31 62785 43.18% 100.00% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good::total 145388 # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_ticks::0 194346512500 96.98% 96.98% # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_ticks::21 1588986000 0.79% 97.77% # number of cycles we spent at this ipl
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.cpu.kern.ipl_ticks::22 8815000 0.00% 97.78% # number of cycles we spent at this ipl
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.cpu.kern.ipl_ticks::31 4458282500 2.22% 100.00% # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_ticks::total 200402596000 # number of cycles we spent at this ipl
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.cpu.kern.ipl_used::0 0.999904 # fraction of swpipl calls that actually changed the ipl
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.cpu.kern.ipl_used::31 0.973275 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.ipl_used::total 0.988241 # fraction of swpipl calls that actually changed the ipl
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
testsys.cpu.kern.syscall::2 3 3.61% 3.61% # number of syscalls executed
testsys.cpu.kern.syscall::3 7 8.43% 12.05% # number of syscalls executed
testsys.cpu.kern.syscall::4 1 1.20% 13.25% # number of syscalls executed
testsys.cpu.kern.syscall::6 7 8.43% 21.69% # number of syscalls executed
testsys.cpu.kern.syscall::17 7 8.43% 30.12% # number of syscalls executed
testsys.cpu.kern.syscall::19 2 2.41% 32.53% # number of syscalls executed
testsys.cpu.kern.syscall::20 1 1.20% 33.73% # number of syscalls executed
testsys.cpu.kern.syscall::33 3 3.61% 37.35% # number of syscalls executed
testsys.cpu.kern.syscall::45 10 12.05% 49.40% # number of syscalls executed
testsys.cpu.kern.syscall::48 5 6.02% 55.42% # number of syscalls executed
testsys.cpu.kern.syscall::54 1 1.20% 56.63% # number of syscalls executed
testsys.cpu.kern.syscall::59 3 3.61% 60.24% # number of syscalls executed
testsys.cpu.kern.syscall::71 15 18.07% 78.31% # number of syscalls executed
testsys.cpu.kern.syscall::74 4 4.82% 83.13% # number of syscalls executed
testsys.cpu.kern.syscall::97 2 2.41% 85.54% # number of syscalls executed
testsys.cpu.kern.syscall::98 2 2.41% 87.95% # number of syscalls executed
testsys.cpu.kern.syscall::101 2 2.41% 90.36% # number of syscalls executed
testsys.cpu.kern.syscall::102 2 2.41% 92.77% # number of syscalls executed
testsys.cpu.kern.syscall::104 1 1.20% 93.98% # number of syscalls executed
testsys.cpu.kern.syscall::105 3 3.61% 97.59% # number of syscalls executed
testsys.cpu.kern.syscall::118 2 2.41% 100.00% # number of syscalls executed
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
testsys.cpu.kern.syscall::total 83 # number of syscalls executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.cpu.kern.callpal::swpctx 438 0.34% 0.34% # number of callpals executed
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.cpu.kern.callpal::tbi 20 0.02% 0.36% # number of callpals executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.cpu.kern.callpal::swpipl 106830 83.26% 83.62% # number of callpals executed
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.cpu.kern.callpal::rdps 359 0.28% 83.90% # number of callpals executed
testsys.cpu.kern.callpal::wrusp 3 0.00% 83.90% # number of callpals executed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.kern.callpal::rdusp 3 0.00% 83.90% # number of callpals executed
testsys.cpu.kern.callpal::rti 20470 15.95% 99.86% # number of callpals executed
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.cpu.kern.callpal::callsys 140 0.11% 99.97% # number of callpals executed
testsys.cpu.kern.callpal::imb 44 0.03% 100.00% # number of callpals executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.cpu.kern.callpal::total 128307 # number of callpals executed
testsys.cpu.kern.mode_switch::kernel 1280 # number of protection mode switches
testsys.cpu.kern.mode_switch::user 702 # number of protection mode switches
testsys.cpu.kern.mode_switch::idle 19629 # number of protection mode switches
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.cpu.kern.mode_good::kernel 707
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.cpu.kern.mode_good::user 702
testsys.cpu.kern.mode_good::idle 5
testsys.cpu.kern.mode_switch_good::kernel 0.552344 # fraction of useful protection mode switches
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.cpu.kern.mode_switch_good::idle 0.000255 # fraction of useful protection mode switches
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.kern.mode_switch_good::total 0.065430 # fraction of useful protection mode switches
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.cpu.kern.mode_ticks::kernel 994603000 60.01% 60.01% # number of ticks spent at the given mode
testsys.cpu.kern.mode_ticks::user 533068000 32.16% 92.17% # number of ticks spent at the given mode
testsys.cpu.kern.mode_ticks::idle 129740500 7.83% 100.00% # number of ticks spent at the given mode
testsys.cpu.kern.swap_context 438 # number of times the context was actually changed
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
testsys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
testsys.tsunami.ethernet.rxBytes 798 # Bytes Received
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.txPackets 8 # Number of Packets Transmitted
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
testsys.tsunami.ethernet.rxPackets 5 # Number of Packets Received
testsys.tsunami.ethernet.txIpChecksums 2 # Number of tx IP Checksums done by device
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.rxIpChecksums 5 # Number of rx IP Checksums done by device
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
testsys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.rxTcpChecksums 5 # Number of rx TCP Checksums done by device
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
testsys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.tsunami.ethernet.descDMAReads 2385801 # Number of descriptors the device read w/ DMA
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.tsunami.ethernet.descDmaReadBytes 57259224 # number of descriptor bytes read w/ DMA
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.tsunami.ethernet.totBandwidth 70176 # Total Bandwidth (bits/s)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.totPackets 13 # Total Packets
testsys.tsunami.ethernet.totBytes 1758 # Total Bytes
testsys.tsunami.ethernet.totPPS 65 # Total Tranmission Rate (packets/s)
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.tsunami.ethernet.txBandwidth 38322 # Transmit Bandwidth (bits/s)
testsys.tsunami.ethernet.rxBandwidth 31855 # Receive Bandwidth (bits/s)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.txPPS 40 # Packet Tranmission Rate (packets/s)
testsys.tsunami.ethernet.rxPPS 25 # Packet Reception Rate (packets/s)
testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
testsys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
testsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
testsys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
testsys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
testsys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
testsys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
testsys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
testsys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
testsys.tsunami.ethernet.postedRxDesc 5 # number of RxDesc interrupts posted to CPU
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
testsys.tsunami.ethernet.totalRxDesc 5 # total number of RxDesc written to ISR
testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.tsunami.ethernet.postedTxIdle 19571 # number of TxIdle interrupts posted to CPU
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.tsunami.ethernet.totalTxIdle 2385801 # total number of TxIdle written to ISR
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
testsys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.tsunami.ethernet.postedInterrupts 2385819 # number of posts to CPU
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.iobus.throughput 290423421 # Throughput (bytes/s)
testsys.iobus.data_through_bus 58203550 # Total data (bytes)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
drivesys.voltage_domain.voltage 1 # Voltage in Volts
drivesys.clk_domain.clock 1000 # Clock period in ticks
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.physmem.bytes_read::cpu.inst 76205572 # Number of bytes read from this memory
drivesys.physmem.bytes_read::cpu.data 26284292 # Number of bytes read from this memory
drivesys.physmem.bytes_read::tsunami.ethernet 57260526 # Number of bytes read from this memory
drivesys.physmem.bytes_read::total 159750390 # Number of bytes read from this memory
drivesys.physmem.bytes_inst_read::cpu.inst 76205572 # Number of instructions bytes read from this memory
drivesys.physmem.bytes_inst_read::total 76205572 # Number of instructions bytes read from this memory
drivesys.physmem.bytes_written::cpu.data 14619632 # Number of bytes written to this memory
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
drivesys.physmem.bytes_written::tsunami.ethernet 1064 # Number of bytes written to this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.physmem.bytes_written::total 14620696 # Number of bytes written to this memory
drivesys.physmem.num_reads::cpu.inst 19051393 # Number of read requests responded to by this memory
drivesys.physmem.num_reads::cpu.data 3647049 # Number of read requests responded to by this memory
drivesys.physmem.num_reads::tsunami.ethernet 2385838 # Number of read requests responded to by this memory
drivesys.physmem.num_reads::total 25084280 # Number of read requests responded to by this memory
drivesys.physmem.num_writes::cpu.data 2024776 # Number of write requests responded to by this memory
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
drivesys.physmem.num_writes::tsunami.ethernet 37 # Number of write requests responded to by this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.physmem.num_writes::total 2024813 # Number of write requests responded to by this memory
drivesys.physmem.bw_read::cpu.inst 380249708 # Total read bandwidth from this memory (bytes/s)
drivesys.physmem.bw_read::cpu.data 131153065 # Total read bandwidth from this memory (bytes/s)
drivesys.physmem.bw_read::tsunami.ethernet 285717930 # Total read bandwidth from this memory (bytes/s)
drivesys.physmem.bw_read::total 797120704 # Total read bandwidth from this memory (bytes/s)
drivesys.physmem.bw_inst_read::cpu.inst 380249708 # Instruction read bandwidth from this memory (bytes/s)
drivesys.physmem.bw_inst_read::total 380249708 # Instruction read bandwidth from this memory (bytes/s)
drivesys.physmem.bw_write::cpu.data 72948876 # Write bandwidth from this memory (bytes/s)
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.physmem.bw_write::tsunami.ethernet 5309 # Write bandwidth from this memory (bytes/s)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.physmem.bw_write::total 72954185 # Write bandwidth from this memory (bytes/s)
drivesys.physmem.bw_total::cpu.inst 380249708 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.bw_total::cpu.data 204101941 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.bw_total::tsunami.ethernet 285723240 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.bw_total::total 870074889 # Total bandwidth to/from this memory (bytes/s)
drivesys.membus.throughput 874808223 # Throughput (bytes/s)
drivesys.membus.data_through_bus 175319690 # Total data (bytes)
drivesys.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
drivesys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes.
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
drivesys.disk0.dma_write_txs 0 # Number of DMA write transactions.
drivesys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
drivesys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
drivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
drivesys.disk2.dma_write_txs 0 # Number of DMA write transactions.
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
drivesys.cpu.clk_domain.clock 250 # Clock period in ticks
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.dtb.fetch_hits 0 # ITB hits
drivesys.cpu.dtb.fetch_misses 0 # ITB misses
drivesys.cpu.dtb.fetch_acv 0 # ITB acv
drivesys.cpu.dtb.fetch_accesses 0 # ITB accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.cpu.dtb.read_hits 3725273 # DTB read hits
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.dtb.read_misses 487 # DTB read misses
drivesys.cpu.dtb.read_acv 30 # DTB read access violations
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
drivesys.cpu.dtb.read_accesses 267991 # DTB read accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.cpu.dtb.write_hits 2084079 # DTB write hits
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.dtb.write_misses 82 # DTB write misses
drivesys.cpu.dtb.write_acv 10 # DTB write access violations
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
drivesys.cpu.dtb.write_accesses 133239 # DTB write accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.cpu.dtb.data_hits 5809352 # DTB hits
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.dtb.data_misses 569 # DTB misses
drivesys.cpu.dtb.data_acv 40 # DTB access violations
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
drivesys.cpu.dtb.data_accesses 401230 # DTB accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.cpu.itb.fetch_hits 4197628 # ITB hits
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.itb.fetch_misses 194 # ITB misses
drivesys.cpu.itb.fetch_acv 22 # ITB acv
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.cpu.itb.fetch_accesses 4197822 # ITB accesses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.itb.read_hits 0 # DTB read hits
drivesys.cpu.itb.read_misses 0 # DTB read misses
drivesys.cpu.itb.read_acv 0 # DTB read access violations
drivesys.cpu.itb.read_accesses 0 # DTB read accesses
drivesys.cpu.itb.write_hits 0 # DTB write hits
drivesys.cpu.itb.write_misses 0 # DTB write misses
drivesys.cpu.itb.write_acv 0 # DTB write access violations
drivesys.cpu.itb.write_accesses 0 # DTB write accesses
drivesys.cpu.itb.data_hits 0 # DTB hits
drivesys.cpu.itb.data_misses 0 # DTB misses
drivesys.cpu.itb.data_acv 0 # DTB access violations
drivesys.cpu.itb.data_accesses 0 # DTB accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.cpu.numCycles 801631448 # number of cpu cycles simulated
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.cpu.committedInsts 19050784 # Number of instructions committed
drivesys.cpu.committedOps 19050784 # Number of ops (including micro ops) committed
drivesys.cpu.num_int_alu_accesses 17740632 # Number of integer alu accesses
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
drivesys.cpu.num_fp_alu_accesses 1412 # Number of float alu accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.cpu.num_func_calls 1265024 # number of times a function call or return occured
drivesys.cpu.num_conditional_control_insts 1264985 # number of instructions that are conditional controls
drivesys.cpu.num_int_insts 17740632 # number of integer instructions
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
drivesys.cpu.num_fp_insts 1412 # number of float instructions
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.cpu.num_int_register_reads 23072330 # number of times the integer registers were read
drivesys.cpu.num_int_register_writes 13981107 # number of times the integer registers were written
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
drivesys.cpu.num_fp_register_reads 760 # number of times the floating registers were read
drivesys.cpu.num_fp_register_writes 766 # number of times the floating registers were written
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.cpu.num_mem_refs 5830788 # number of memory refs
drivesys.cpu.num_load_insts 3746196 # Number of load instructions
drivesys.cpu.num_store_insts 2084592 # Number of store instructions
drivesys.cpu.num_idle_cycles 782579974.227931 # Number of idle cycles
drivesys.cpu.num_busy_cycles 19051473.772069 # Number of busy cycles
drivesys.cpu.not_idle_fraction 0.023766 # Percentage of non-idle cycles
drivesys.cpu.idle_fraction 0.976234 # Percentage of idle cycles
stats: updates due to branch predictor warming
2014-02-16 18:40:34 +01:00
drivesys.cpu.Branches 2793313 # Number of branches fetched
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
drivesys.cpu.op_class::No_OpClass 623554 3.27% 3.27% # Class of executed instruction
drivesys.cpu.op_class::IntAlu 11538630 60.57% 63.84% # Class of executed instruction
drivesys.cpu.op_class::IntMult 20663 0.11% 63.95% # Class of executed instruction
drivesys.cpu.op_class::IntDiv 0 0.00% 63.95% # Class of executed instruction
drivesys.cpu.op_class::FloatAdd 138 0.00% 63.95% # Class of executed instruction
drivesys.cpu.op_class::FloatCmp 0 0.00% 63.95% # Class of executed instruction
drivesys.cpu.op_class::FloatCvt 0 0.00% 63.95% # Class of executed instruction
drivesys.cpu.op_class::FloatMult 0 0.00% 63.95% # Class of executed instruction
drivesys.cpu.op_class::FloatDiv 23 0.00% 63.95% # Class of executed instruction
drivesys.cpu.op_class::FloatSqrt 0 0.00% 63.95% # Class of executed instruction
drivesys.cpu.op_class::SimdAdd 0 0.00% 63.95% # Class of executed instruction
drivesys.cpu.op_class::SimdAddAcc 0 0.00% 63.95% # Class of executed instruction
drivesys.cpu.op_class::SimdAlu 0 0.00% 63.95% # Class of executed instruction
drivesys.cpu.op_class::SimdCmp 0 0.00% 63.95% # Class of executed instruction
drivesys.cpu.op_class::SimdCvt 0 0.00% 63.95% # Class of executed instruction
drivesys.cpu.op_class::SimdMisc 0 0.00% 63.95% # Class of executed instruction
drivesys.cpu.op_class::SimdMult 0 0.00% 63.95% # Class of executed instruction
drivesys.cpu.op_class::SimdMultAcc 0 0.00% 63.95% # Class of executed instruction
drivesys.cpu.op_class::SimdShift 0 0.00% 63.95% # Class of executed instruction
drivesys.cpu.op_class::SimdShiftAcc 0 0.00% 63.95% # Class of executed instruction
drivesys.cpu.op_class::SimdSqrt 0 0.00% 63.95% # Class of executed instruction
drivesys.cpu.op_class::SimdFloatAdd 0 0.00% 63.95% # Class of executed instruction
drivesys.cpu.op_class::SimdFloatAlu 0 0.00% 63.95% # Class of executed instruction
drivesys.cpu.op_class::SimdFloatCmp 0 0.00% 63.95% # Class of executed instruction
drivesys.cpu.op_class::SimdFloatCvt 0 0.00% 63.95% # Class of executed instruction
drivesys.cpu.op_class::SimdFloatDiv 0 0.00% 63.95% # Class of executed instruction
drivesys.cpu.op_class::SimdFloatMisc 0 0.00% 63.95% # Class of executed instruction
drivesys.cpu.op_class::SimdFloatMult 0 0.00% 63.95% # Class of executed instruction
drivesys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.95% # Class of executed instruction
drivesys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.95% # Class of executed instruction
drivesys.cpu.op_class::MemRead 4026028 21.13% 85.08% # Class of executed instruction
drivesys.cpu.op_class::MemWrite 2085021 10.94% 96.02% # Class of executed instruction
drivesys.cpu.op_class::IprAccess 757336 3.98% 100.00% # Class of executed instruction
drivesys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
drivesys.cpu.op_class::total 19051393 # Class of executed instruction
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.cpu.kern.inst.quiesce 19876 # number of quiesce instructions executed
drivesys.cpu.kern.inst.hwrei 143591 # number of hwrei instructions executed
drivesys.cpu.kern.ipl_count::0 60359 42.42% 42.42% # number of times we switched to this ipl
drivesys.cpu.kern.ipl_count::21 19727 13.86% 56.28% # number of times we switched to this ipl
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.kern.ipl_count::22 205 0.14% 56.42% # number of times we switched to this ipl
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.cpu.kern.ipl_count::31 62011 43.58% 100.00% # number of times we switched to this ipl
drivesys.cpu.kern.ipl_count::total 142302 # number of times we switched to this ipl
drivesys.cpu.kern.ipl_good::0 60359 42.91% 42.91% # number of times we switched to this ipl from a different ipl
drivesys.cpu.kern.ipl_good::21 19727 14.03% 56.94% # number of times we switched to this ipl from a different ipl
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.kern.ipl_good::22 205 0.15% 57.09% # number of times we switched to this ipl from a different ipl
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.cpu.kern.ipl_good::31 60360 42.91% 100.00% # number of times we switched to this ipl from a different ipl
drivesys.cpu.kern.ipl_good::total 140651 # number of times we switched to this ipl from a different ipl
drivesys.cpu.kern.ipl_ticks::0 197399332500 98.50% 98.50% # number of cycles we spent at this ipl
drivesys.cpu.kern.ipl_ticks::21 798910750 0.40% 98.90% # number of cycles we spent at this ipl
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.kern.ipl_ticks::22 4407500 0.00% 98.90% # number of cycles we spent at this ipl
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.cpu.kern.ipl_ticks::31 2205211250 1.10% 100.00% # number of cycles we spent at this ipl
drivesys.cpu.kern.ipl_ticks::total 200407862000 # number of cycles we spent at this ipl
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl
drivesys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
drivesys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.cpu.kern.ipl_used::31 0.973376 # fraction of swpipl calls that actually changed the ipl
drivesys.cpu.kern.ipl_used::total 0.988398 # fraction of swpipl calls that actually changed the ipl
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.kern.syscall::2 1 4.55% 4.55% # number of syscalls executed
drivesys.cpu.kern.syscall::6 3 13.64% 18.18% # number of syscalls executed
drivesys.cpu.kern.syscall::17 2 9.09% 27.27% # number of syscalls executed
drivesys.cpu.kern.syscall::97 1 4.55% 31.82% # number of syscalls executed
drivesys.cpu.kern.syscall::99 2 9.09% 40.91% # number of syscalls executed
drivesys.cpu.kern.syscall::101 2 9.09% 50.00% # number of syscalls executed
drivesys.cpu.kern.syscall::102 3 13.64% 63.64% # number of syscalls executed
drivesys.cpu.kern.syscall::104 1 4.55% 68.18% # number of syscalls executed
drivesys.cpu.kern.syscall::105 3 13.64% 81.82% # number of syscalls executed
drivesys.cpu.kern.syscall::106 1 4.55% 86.36% # number of syscalls executed
drivesys.cpu.kern.syscall::118 2 9.09% 95.45% # number of syscalls executed
drivesys.cpu.kern.syscall::150 1 4.55% 100.00% # number of syscalls executed
drivesys.cpu.kern.syscall::total 22 # number of syscalls executed
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.kern.callpal::swpctx 72 0.06% 0.06% # number of callpals executed
drivesys.cpu.kern.callpal::tbi 5 0.00% 0.06% # number of callpals executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.cpu.kern.callpal::swpipl 102333 83.31% 83.37% # number of callpals executed
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.kern.callpal::rdps 354 0.29% 83.66% # number of callpals executed
drivesys.cpu.kern.callpal::rdusp 1 0.00% 83.66% # number of callpals executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.cpu.kern.callpal::rti 20038 16.31% 99.97% # number of callpals executed
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.kern.callpal::callsys 25 0.02% 99.99% # number of callpals executed
drivesys.cpu.kern.callpal::imb 7 0.01% 100.00% # number of callpals executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.cpu.kern.callpal::total 122835 # number of callpals executed
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.kern.mode_switch::kernel 214 # number of protection mode switches
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.cpu.kern.mode_switch::user 140 # number of protection mode switches
drivesys.cpu.kern.mode_switch::idle 19896 # number of protection mode switches
drivesys.cpu.kern.mode_good::kernel 144
drivesys.cpu.kern.mode_good::user 140
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
drivesys.cpu.kern.mode_good::idle 4
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.cpu.kern.mode_switch_good::kernel 0.672897 # fraction of useful protection mode switches
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.kern.mode_switch_good::idle 0.000201 # fraction of useful protection mode switches
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.cpu.kern.mode_switch_good::total 0.014222 # fraction of useful protection mode switches
drivesys.cpu.kern.mode_ticks::kernel 78134250 2.63% 2.63% # number of ticks spent at the given mode
drivesys.cpu.kern.mode_ticks::user 319668250 10.78% 13.41% # number of ticks spent at the given mode
drivesys.cpu.kern.mode_ticks::idle 2567942000 86.59% 100.00% # number of ticks spent at the given mode
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
drivesys.cpu.kern.swap_context 72 # number of times the context was actually changed
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
drivesys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted
drivesys.tsunami.ethernet.rxBytes 960 # Bytes Received
drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted
drivesys.tsunami.ethernet.rxPackets 8 # Number of Packets Received
drivesys.tsunami.ethernet.txIpChecksums 2 # Number of tx IP Checksums done by device
drivesys.tsunami.ethernet.rxIpChecksums 8 # Number of rx IP Checksums done by device
drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device
drivesys.tsunami.ethernet.rxTcpChecksums 8 # Number of rx TCP Checksums done by device
drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
drivesys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.tsunami.ethernet.descDMAReads 2385809 # Number of descriptors the device read w/ DMA
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.tsunami.ethernet.descDmaReadBytes 57259416 # number of descriptor bytes read w/ DMA
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.tsunami.ethernet.totBandwidth 70176 # Total Bandwidth (bits/s)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.totPackets 13 # Total Packets
drivesys.tsunami.ethernet.totBytes 1758 # Total Bytes
drivesys.tsunami.ethernet.totPPS 65 # Total Tranmission Rate (packets/s)
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.tsunami.ethernet.txBandwidth 31855 # Transmit Bandwidth (bits/s)
drivesys.tsunami.ethernet.rxBandwidth 38322 # Receive Bandwidth (bits/s)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.txPPS 25 # Packet Tranmission Rate (packets/s)
drivesys.tsunami.ethernet.rxPPS 40 # Packet Reception Rate (packets/s)
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
drivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
drivesys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
drivesys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
drivesys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
drivesys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
drivesys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
drivesys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.tsunami.ethernet.postedRxDesc 8 # number of RxDesc interrupts posted to CPU
drivesys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.totalRxDesc 8 # total number of RxDesc written to ISR
drivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
drivesys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.tsunami.ethernet.postedTxIdle 19726 # number of TxIdle interrupts posted to CPU
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.tsunami.ethernet.totalTxIdle 2385809 # total number of TxIdle written to ISR
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
drivesys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.tsunami.ethernet.postedInterrupts 2385830 # number of posts to CPU
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.iobus.throughput 290456573 # Throughput (bytes/s)
drivesys.iobus.data_through_bus 58210194 # Total data (bytes)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
sim_seconds 0.000407 # Number of seconds simulated
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
sim_ticks 407341500 # Number of ticks simulated
final_tick 4321621592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
host_inst_rate 7312019890 # Simulator instruction rate (inst/s)
host_op_rate 7310591323 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5683411932 # Simulator tick rate (ticks/s)
host_mem_usage 513712 # Number of bytes of host memory used
host_seconds 0.07 # Real time elapsed on the host
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
sim_insts 523862353 # Number of instructions simulated
sim_ops 523862353 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
testsys.voltage_domain.voltage 1 # Voltage in Volts
testsys.clk_domain.clock 1000 # Clock period in ticks
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.physmem.bytes_read::cpu.inst 144504 # Number of bytes read from this memory
testsys.physmem.bytes_read::cpu.data 49936 # Number of bytes read from this memory
testsys.physmem.bytes_read::tsunami.ethernet 116376 # Number of bytes read from this memory
testsys.physmem.bytes_read::total 310816 # Number of bytes read from this memory
testsys.physmem.bytes_inst_read::cpu.inst 144504 # Number of instructions bytes read from this memory
testsys.physmem.bytes_inst_read::total 144504 # Number of instructions bytes read from this memory
testsys.physmem.bytes_written::cpu.data 27704 # Number of bytes written to this memory
testsys.physmem.bytes_written::total 27704 # Number of bytes written to this memory
testsys.physmem.num_reads::cpu.inst 36126 # Number of read requests responded to by this memory
testsys.physmem.num_reads::cpu.data 6905 # Number of read requests responded to by this memory
testsys.physmem.num_reads::tsunami.ethernet 4849 # Number of read requests responded to by this memory
testsys.physmem.num_reads::total 47880 # Number of read requests responded to by this memory
testsys.physmem.num_writes::cpu.data 3814 # Number of write requests responded to by this memory
testsys.physmem.num_writes::total 3814 # Number of write requests responded to by this memory
testsys.physmem.bw_read::cpu.inst 354749025 # Total read bandwidth from this memory (bytes/s)
testsys.physmem.bw_read::cpu.data 122590014 # Total read bandwidth from this memory (bytes/s)
testsys.physmem.bw_read::tsunami.ethernet 285696400 # Total read bandwidth from this memory (bytes/s)
testsys.physmem.bw_read::total 763035438 # Total read bandwidth from this memory (bytes/s)
testsys.physmem.bw_inst_read::cpu.inst 354749025 # Instruction read bandwidth from this memory (bytes/s)
testsys.physmem.bw_inst_read::total 354749025 # Instruction read bandwidth from this memory (bytes/s)
testsys.physmem.bw_write::cpu.data 68011730 # Write bandwidth from this memory (bytes/s)
testsys.physmem.bw_write::total 68011730 # Write bandwidth from this memory (bytes/s)
testsys.physmem.bw_total::cpu.inst 354749025 # Total bandwidth to/from this memory (bytes/s)
testsys.physmem.bw_total::cpu.data 190601743 # Total bandwidth to/from this memory (bytes/s)
testsys.physmem.bw_total::tsunami.ethernet 285696400 # Total bandwidth to/from this memory (bytes/s)
testsys.physmem.bw_total::total 831047168 # Total bandwidth to/from this memory (bytes/s)
testsys.membus.throughput 835780297 # Throughput (bytes/s)
testsys.membus.data_through_bus 340448 # Total data (bytes)
testsys.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
testsys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes.
testsys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
testsys.disk0.dma_write_txs 0 # Number of DMA write transactions.
testsys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
testsys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
testsys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
testsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
testsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
testsys.disk2.dma_write_txs 0 # Number of DMA write transactions.
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
testsys.cpu.clk_domain.clock 500 # Clock period in ticks
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
testsys.cpu.dtb.fetch_hits 0 # ITB hits
testsys.cpu.dtb.fetch_misses 0 # ITB misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.dtb.fetch_acv 0 # ITB acv
testsys.cpu.dtb.fetch_accesses 0 # ITB accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.cpu.dtb.read_hits 7065 # DTB read hits
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
testsys.cpu.dtb.read_misses 0 # DTB read misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.dtb.read_acv 0 # DTB read access violations
testsys.cpu.dtb.read_accesses 0 # DTB read accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.cpu.dtb.write_hits 3935 # DTB write hits
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
testsys.cpu.dtb.write_misses 0 # DTB write misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.dtb.write_acv 0 # DTB write access violations
testsys.cpu.dtb.write_accesses 0 # DTB write accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.cpu.dtb.data_hits 11000 # DTB hits
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.dtb.data_misses 0 # DTB misses
testsys.cpu.dtb.data_acv 0 # DTB access violations
testsys.cpu.dtb.data_accesses 0 # DTB accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.cpu.itb.fetch_hits 5992 # ITB hits
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
testsys.cpu.itb.fetch_misses 0 # ITB misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.itb.fetch_acv 0 # ITB acv
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.cpu.itb.fetch_accesses 5992 # ITB accesses
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
testsys.cpu.itb.read_hits 0 # DTB read hits
testsys.cpu.itb.read_misses 0 # DTB read misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.itb.read_acv 0 # DTB read access violations
testsys.cpu.itb.read_accesses 0 # DTB read accesses
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
testsys.cpu.itb.write_hits 0 # DTB write hits
testsys.cpu.itb.write_misses 0 # DTB write misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.itb.write_acv 0 # DTB write access violations
testsys.cpu.itb.write_accesses 0 # DTB write accesses
testsys.cpu.itb.data_hits 0 # DTB hits
testsys.cpu.itb.data_misses 0 # DTB misses
testsys.cpu.itb.data_acv 0 # DTB access violations
testsys.cpu.itb.data_accesses 0 # DTB accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.cpu.numCycles 821016 # number of cpu cycles simulated
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.cpu.committedInsts 36126 # Number of instructions committed
testsys.cpu.committedOps 36126 # Number of ops (including micro ops) committed
testsys.cpu.num_int_alu_accesses 33492 # Number of integer alu accesses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.cpu.num_func_calls 2384 # number of times a function call or return occured
testsys.cpu.num_conditional_control_insts 2346 # number of instructions that are conditional controls
testsys.cpu.num_int_insts 33492 # number of integer instructions
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.num_fp_insts 0 # number of float instructions
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.cpu.num_int_register_reads 43747 # number of times the integer registers were read
testsys.cpu.num_int_register_writes 26476 # number of times the integer registers were written
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.num_fp_register_reads 0 # number of times the floating registers were read
testsys.cpu.num_fp_register_writes 0 # number of times the floating registers were written
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.cpu.num_mem_refs 11041 # number of memory refs
testsys.cpu.num_load_insts 7105 # Number of load instructions
testsys.cpu.num_store_insts 3936 # Number of store instructions
testsys.cpu.num_idle_cycles 784609.171892 # Number of idle cycles
testsys.cpu.num_busy_cycles 36406.828108 # Number of busy cycles
testsys.cpu.not_idle_fraction 0.044344 # Percentage of non-idle cycles
testsys.cpu.idle_fraction 0.955656 # Percentage of idle cycles
stats: updates due to branch predictor warming
2014-02-16 18:40:34 +01:00
testsys.cpu.Branches 5238 # Number of branches fetched
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
testsys.cpu.op_class::No_OpClass 1261 3.49% 3.49% # Class of executed instruction
testsys.cpu.op_class::IntAlu 21664 59.97% 63.46% # Class of executed instruction
testsys.cpu.op_class::IntMult 44 0.12% 63.58% # Class of executed instruction
testsys.cpu.op_class::IntDiv 0 0.00% 63.58% # Class of executed instruction
testsys.cpu.op_class::FloatAdd 0 0.00% 63.58% # Class of executed instruction
testsys.cpu.op_class::FloatCmp 0 0.00% 63.58% # Class of executed instruction
testsys.cpu.op_class::FloatCvt 0 0.00% 63.58% # Class of executed instruction
testsys.cpu.op_class::FloatMult 0 0.00% 63.58% # Class of executed instruction
testsys.cpu.op_class::FloatDiv 0 0.00% 63.58% # Class of executed instruction
testsys.cpu.op_class::FloatSqrt 0 0.00% 63.58% # Class of executed instruction
testsys.cpu.op_class::SimdAdd 0 0.00% 63.58% # Class of executed instruction
testsys.cpu.op_class::SimdAddAcc 0 0.00% 63.58% # Class of executed instruction
testsys.cpu.op_class::SimdAlu 0 0.00% 63.58% # Class of executed instruction
testsys.cpu.op_class::SimdCmp 0 0.00% 63.58% # Class of executed instruction
testsys.cpu.op_class::SimdCvt 0 0.00% 63.58% # Class of executed instruction
testsys.cpu.op_class::SimdMisc 0 0.00% 63.58% # Class of executed instruction
testsys.cpu.op_class::SimdMult 0 0.00% 63.58% # Class of executed instruction
testsys.cpu.op_class::SimdMultAcc 0 0.00% 63.58% # Class of executed instruction
testsys.cpu.op_class::SimdShift 0 0.00% 63.58% # Class of executed instruction
testsys.cpu.op_class::SimdShiftAcc 0 0.00% 63.58% # Class of executed instruction
testsys.cpu.op_class::SimdSqrt 0 0.00% 63.58% # Class of executed instruction
testsys.cpu.op_class::SimdFloatAdd 0 0.00% 63.58% # Class of executed instruction
testsys.cpu.op_class::SimdFloatAlu 0 0.00% 63.58% # Class of executed instruction
testsys.cpu.op_class::SimdFloatCmp 0 0.00% 63.58% # Class of executed instruction
testsys.cpu.op_class::SimdFloatCvt 0 0.00% 63.58% # Class of executed instruction
testsys.cpu.op_class::SimdFloatDiv 0 0.00% 63.58% # Class of executed instruction
testsys.cpu.op_class::SimdFloatMisc 0 0.00% 63.58% # Class of executed instruction
testsys.cpu.op_class::SimdFloatMult 0 0.00% 63.58% # Class of executed instruction
testsys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.58% # Class of executed instruction
testsys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.58% # Class of executed instruction
testsys.cpu.op_class::MemRead 7674 21.24% 84.82% # Class of executed instruction
testsys.cpu.op_class::MemWrite 3938 10.90% 95.72% # Class of executed instruction
testsys.cpu.op_class::IprAccess 1545 4.28% 100.00% # Class of executed instruction
testsys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
testsys.cpu.op_class::total 36126 # Class of executed instruction
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
testsys.cpu.kern.inst.arm 0 # number of arm instructions executed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.kern.inst.quiesce 40 # number of quiesce instructions executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.cpu.kern.inst.hwrei 295 # number of hwrei instructions executed
testsys.cpu.kern.ipl_count::0 123 41.84% 41.84% # number of times we switched to this ipl
testsys.cpu.kern.ipl_count::21 40 13.61% 55.44% # number of times we switched to this ipl
testsys.cpu.kern.ipl_count::22 1 0.34% 55.78% # number of times we switched to this ipl
testsys.cpu.kern.ipl_count::31 130 44.22% 100.00% # number of times we switched to this ipl
testsys.cpu.kern.ipl_count::total 294 # number of times we switched to this ipl
testsys.cpu.kern.ipl_good::0 123 42.86% 42.86% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good::21 40 13.94% 56.79% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good::22 1 0.35% 57.14% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good::31 123 42.86% 100.00% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good::total 287 # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_ticks::0 397967000 96.95% 96.95% # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_ticks::21 3240000 0.79% 97.73% # number of cycles we spent at this ipl
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.kern.ipl_ticks::22 43000 0.01% 97.74% # number of cycles we spent at this ipl
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.cpu.kern.ipl_ticks::31 9258000 2.26% 100.00% # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_ticks::total 410508000 # number of cycles we spent at this ipl
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
testsys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.cpu.kern.ipl_used::31 0.946154 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.ipl_used::total 0.976190 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.callpal::swpipl 212 83.46% 83.46% # number of callpals executed
testsys.cpu.kern.callpal::rdps 1 0.39% 83.86% # number of callpals executed
testsys.cpu.kern.callpal::rti 41 16.14% 100.00% # number of callpals executed
testsys.cpu.kern.callpal::total 254 # number of callpals executed
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
testsys.cpu.kern.mode_switch::kernel 0 # number of protection mode switches
testsys.cpu.kern.mode_switch::user 0 # number of protection mode switches
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.cpu.kern.mode_switch::idle 41 # number of protection mode switches
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.kern.mode_good::kernel 0
testsys.cpu.kern.mode_good::user 0
testsys.cpu.kern.mode_good::idle 0
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
testsys.cpu.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches
testsys.cpu.kern.mode_switch_good::user nan # fraction of useful protection mode switches
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
testsys.cpu.kern.mode_switch_good::idle 0 # fraction of useful protection mode switches
testsys.cpu.kern.mode_switch_good::total 0 # fraction of useful protection mode switches
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
testsys.cpu.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode
testsys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode
testsys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
testsys.cpu.kern.swap_context 0 # number of times the context was actually changed
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
testsys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.tsunami.ethernet.descDMAReads 4849 # Number of descriptors the device read w/ DMA
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
testsys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.tsunami.ethernet.descDmaReadBytes 116376 # number of descriptor bytes read w/ DMA
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
testsys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
testsys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
testsys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
testsys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.tsunami.ethernet.postedTxIdle 40 # number of TxIdle interrupts posted to CPU
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.tsunami.ethernet.totalTxIdle 4849 # total number of TxIdle written to ISR
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
testsys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.tsunami.ethernet.postedInterrupts 4849 # number of posts to CPU
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
testsys.iobus.throughput 290429529 # Throughput (bytes/s)
testsys.iobus.data_through_bus 118304 # Total data (bytes)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
drivesys.voltage_domain.voltage 1 # Voltage in Volts
drivesys.clk_domain.clock 1000 # Clock period in ticks
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.physmem.bytes_read::cpu.inst 144608 # Number of bytes read from this memory
drivesys.physmem.bytes_read::cpu.data 49952 # Number of bytes read from this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.physmem.bytes_read::tsunami.ethernet 116400 # Number of bytes read from this memory
drivesys.physmem.bytes_read::total 310960 # Number of bytes read from this memory
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.physmem.bytes_inst_read::cpu.inst 144608 # Number of instructions bytes read from this memory
drivesys.physmem.bytes_inst_read::total 144608 # Number of instructions bytes read from this memory
drivesys.physmem.bytes_written::cpu.data 27688 # Number of bytes written to this memory
drivesys.physmem.bytes_written::total 27688 # Number of bytes written to this memory
drivesys.physmem.num_reads::cpu.inst 36152 # Number of read requests responded to by this memory
drivesys.physmem.num_reads::cpu.data 6909 # Number of read requests responded to by this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.physmem.num_reads::tsunami.ethernet 4850 # Number of read requests responded to by this memory
drivesys.physmem.num_reads::total 47911 # Number of read requests responded to by this memory
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.physmem.num_writes::cpu.data 3812 # Number of write requests responded to by this memory
drivesys.physmem.num_writes::total 3812 # Number of write requests responded to by this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.physmem.bw_read::cpu.inst 355004339 # Total read bandwidth from this memory (bytes/s)
drivesys.physmem.bw_read::cpu.data 122629293 # Total read bandwidth from this memory (bytes/s)
drivesys.physmem.bw_read::tsunami.ethernet 285755318 # Total read bandwidth from this memory (bytes/s)
drivesys.physmem.bw_read::total 763388950 # Total read bandwidth from this memory (bytes/s)
drivesys.physmem.bw_inst_read::cpu.inst 355004339 # Instruction read bandwidth from this memory (bytes/s)
drivesys.physmem.bw_inst_read::total 355004339 # Instruction read bandwidth from this memory (bytes/s)
drivesys.physmem.bw_write::cpu.data 67972451 # Write bandwidth from this memory (bytes/s)
drivesys.physmem.bw_write::total 67972451 # Write bandwidth from this memory (bytes/s)
drivesys.physmem.bw_total::cpu.inst 355004339 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.bw_total::cpu.data 190601743 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.bw_total::tsunami.ethernet 285755318 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.bw_total::total 831361401 # Total bandwidth to/from this memory (bytes/s)
drivesys.membus.throughput 836094530 # Throughput (bytes/s)
drivesys.membus.data_through_bus 340576 # Total data (bytes)
drivesys.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
drivesys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes.
drivesys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
drivesys.disk0.dma_write_txs 0 # Number of DMA write transactions.
drivesys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
drivesys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
drivesys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
drivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
drivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
drivesys.disk2.dma_write_txs 0 # Number of DMA write transactions.
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
drivesys.cpu.clk_domain.clock 250 # Clock period in ticks
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.dtb.fetch_hits 0 # ITB hits
drivesys.cpu.dtb.fetch_misses 0 # ITB misses
drivesys.cpu.dtb.fetch_acv 0 # ITB acv
drivesys.cpu.dtb.fetch_accesses 0 # ITB accesses
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.dtb.read_hits 7069 # DTB read hits
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.dtb.read_misses 0 # DTB read misses
drivesys.cpu.dtb.read_acv 0 # DTB read access violations
drivesys.cpu.dtb.read_accesses 0 # DTB read accesses
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.dtb.write_hits 3933 # DTB write hits
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.dtb.write_misses 0 # DTB write misses
drivesys.cpu.dtb.write_acv 0 # DTB write access violations
drivesys.cpu.dtb.write_accesses 0 # DTB write accesses
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.dtb.data_hits 11002 # DTB hits
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.dtb.data_misses 0 # DTB misses
drivesys.cpu.dtb.data_acv 0 # DTB access violations
drivesys.cpu.dtb.data_accesses 0 # DTB accesses
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.itb.fetch_hits 5992 # ITB hits
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.itb.fetch_misses 0 # ITB misses
drivesys.cpu.itb.fetch_acv 0 # ITB acv
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.itb.fetch_accesses 5992 # ITB accesses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.itb.read_hits 0 # DTB read hits
drivesys.cpu.itb.read_misses 0 # DTB read misses
drivesys.cpu.itb.read_acv 0 # DTB read access violations
drivesys.cpu.itb.read_accesses 0 # DTB read accesses
drivesys.cpu.itb.write_hits 0 # DTB write hits
drivesys.cpu.itb.write_misses 0 # DTB write misses
drivesys.cpu.itb.write_acv 0 # DTB write access violations
drivesys.cpu.itb.write_accesses 0 # DTB write accesses
drivesys.cpu.itb.data_hits 0 # DTB hits
drivesys.cpu.itb.data_misses 0 # DTB misses
drivesys.cpu.itb.data_acv 0 # DTB access violations
drivesys.cpu.itb.data_accesses 0 # DTB accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.cpu.numCycles 1626240 # number of cpu cycles simulated
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.committedInsts 36152 # Number of instructions committed
drivesys.cpu.committedOps 36152 # Number of ops (including micro ops) committed
drivesys.cpu.num_int_alu_accesses 33516 # Number of integer alu accesses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.num_func_calls 2388 # number of times a function call or return occured
drivesys.cpu.num_conditional_control_insts 2347 # number of instructions that are conditional controls
drivesys.cpu.num_int_insts 33516 # number of integer instructions
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.num_fp_insts 0 # number of float instructions
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.num_int_register_reads 43772 # number of times the integer registers were read
drivesys.cpu.num_int_register_writes 26499 # number of times the integer registers were written
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.num_fp_register_reads 0 # number of times the floating registers were read
drivesys.cpu.num_fp_register_writes 0 # number of times the floating registers were written
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.num_mem_refs 11043 # number of memory refs
drivesys.cpu.num_load_insts 7109 # Number of load instructions
drivesys.cpu.num_store_insts 3934 # Number of store instructions
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.cpu.num_idle_cycles 1590157.359061 # Number of idle cycles
drivesys.cpu.num_busy_cycles 36082.640939 # Number of busy cycles
drivesys.cpu.not_idle_fraction 0.022188 # Percentage of non-idle cycles
drivesys.cpu.idle_fraction 0.977812 # Percentage of idle cycles
stats: updates due to branch predictor warming
2014-02-16 18:40:34 +01:00
drivesys.cpu.Branches 5243 # Number of branches fetched
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
drivesys.cpu.op_class::No_OpClass 1262 3.49% 3.49% # Class of executed instruction
drivesys.cpu.op_class::IntAlu 21687 59.99% 63.48% # Class of executed instruction
drivesys.cpu.op_class::IntMult 44 0.12% 63.60% # Class of executed instruction
drivesys.cpu.op_class::IntDiv 0 0.00% 63.60% # Class of executed instruction
drivesys.cpu.op_class::FloatAdd 0 0.00% 63.60% # Class of executed instruction
drivesys.cpu.op_class::FloatCmp 0 0.00% 63.60% # Class of executed instruction
drivesys.cpu.op_class::FloatCvt 0 0.00% 63.60% # Class of executed instruction
drivesys.cpu.op_class::FloatMult 0 0.00% 63.60% # Class of executed instruction
drivesys.cpu.op_class::FloatDiv 0 0.00% 63.60% # Class of executed instruction
drivesys.cpu.op_class::FloatSqrt 0 0.00% 63.60% # Class of executed instruction
drivesys.cpu.op_class::SimdAdd 0 0.00% 63.60% # Class of executed instruction
drivesys.cpu.op_class::SimdAddAcc 0 0.00% 63.60% # Class of executed instruction
drivesys.cpu.op_class::SimdAlu 0 0.00% 63.60% # Class of executed instruction
drivesys.cpu.op_class::SimdCmp 0 0.00% 63.60% # Class of executed instruction
drivesys.cpu.op_class::SimdCvt 0 0.00% 63.60% # Class of executed instruction
drivesys.cpu.op_class::SimdMisc 0 0.00% 63.60% # Class of executed instruction
drivesys.cpu.op_class::SimdMult 0 0.00% 63.60% # Class of executed instruction
drivesys.cpu.op_class::SimdMultAcc 0 0.00% 63.60% # Class of executed instruction
drivesys.cpu.op_class::SimdShift 0 0.00% 63.60% # Class of executed instruction
drivesys.cpu.op_class::SimdShiftAcc 0 0.00% 63.60% # Class of executed instruction
drivesys.cpu.op_class::SimdSqrt 0 0.00% 63.60% # Class of executed instruction
drivesys.cpu.op_class::SimdFloatAdd 0 0.00% 63.60% # Class of executed instruction
drivesys.cpu.op_class::SimdFloatAlu 0 0.00% 63.60% # Class of executed instruction
drivesys.cpu.op_class::SimdFloatCmp 0 0.00% 63.60% # Class of executed instruction
drivesys.cpu.op_class::SimdFloatCvt 0 0.00% 63.60% # Class of executed instruction
drivesys.cpu.op_class::SimdFloatDiv 0 0.00% 63.60% # Class of executed instruction
drivesys.cpu.op_class::SimdFloatMisc 0 0.00% 63.60% # Class of executed instruction
drivesys.cpu.op_class::SimdFloatMult 0 0.00% 63.60% # Class of executed instruction
drivesys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.60% # Class of executed instruction
drivesys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.60% # Class of executed instruction
drivesys.cpu.op_class::MemRead 7678 21.24% 84.84% # Class of executed instruction
drivesys.cpu.op_class::MemWrite 3936 10.89% 95.73% # Class of executed instruction
drivesys.cpu.op_class::IprAccess 1545 4.27% 100.00% # Class of executed instruction
drivesys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
drivesys.cpu.op_class::total 36152 # Class of executed instruction
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.kern.inst.quiesce 41 # number of quiesce instructions executed
drivesys.cpu.kern.inst.hwrei 295 # number of hwrei instructions executed
drivesys.cpu.kern.ipl_count::0 123 41.84% 41.84% # number of times we switched to this ipl
drivesys.cpu.kern.ipl_count::21 40 13.61% 55.44% # number of times we switched to this ipl
drivesys.cpu.kern.ipl_count::22 1 0.34% 55.78% # number of times we switched to this ipl
drivesys.cpu.kern.ipl_count::31 130 44.22% 100.00% # number of times we switched to this ipl
drivesys.cpu.kern.ipl_count::total 294 # number of times we switched to this ipl
drivesys.cpu.kern.ipl_good::0 123 42.86% 42.86% # number of times we switched to this ipl from a different ipl
drivesys.cpu.kern.ipl_good::21 40 13.94% 56.79% # number of times we switched to this ipl from a different ipl
drivesys.cpu.kern.ipl_good::22 1 0.35% 57.14% # number of times we switched to this ipl from a different ipl
drivesys.cpu.kern.ipl_good::31 123 42.86% 100.00% # number of times we switched to this ipl from a different ipl
drivesys.cpu.kern.ipl_good::total 287 # number of times we switched to this ipl from a different ipl
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.cpu.kern.ipl_ticks::0 400289000 98.46% 98.46% # number of cycles we spent at this ipl
drivesys.cpu.kern.ipl_ticks::21 1620000 0.40% 98.86% # number of cycles we spent at this ipl
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.kern.ipl_ticks::22 21500 0.01% 98.86% # number of cycles we spent at this ipl
drivesys.cpu.kern.ipl_ticks::31 4629500 1.14% 100.00% # number of cycles we spent at this ipl
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.cpu.kern.ipl_ticks::total 406560000 # number of cycles we spent at this ipl
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
drivesys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
drivesys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.kern.ipl_used::31 0.946154 # fraction of swpipl calls that actually changed the ipl
drivesys.cpu.kern.ipl_used::total 0.976190 # fraction of swpipl calls that actually changed the ipl
drivesys.cpu.kern.callpal::swpipl 212 83.46% 83.46% # number of callpals executed
drivesys.cpu.kern.callpal::rdps 1 0.39% 83.86% # number of callpals executed
drivesys.cpu.kern.callpal::rti 41 16.14% 100.00% # number of callpals executed
drivesys.cpu.kern.callpal::total 254 # number of callpals executed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.kern.mode_switch::kernel 0 # number of protection mode switches
drivesys.cpu.kern.mode_switch::user 0 # number of protection mode switches
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.kern.mode_switch::idle 41 # number of protection mode switches
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.kern.mode_good::kernel 0
drivesys.cpu.kern.mode_good::user 0
drivesys.cpu.kern.mode_good::idle 0
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
drivesys.cpu.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches
drivesys.cpu.kern.mode_switch_good::user nan # fraction of useful protection mode switches
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
drivesys.cpu.kern.mode_switch_good::idle 0 # fraction of useful protection mode switches
drivesys.cpu.kern.mode_switch_good::total 0 # fraction of useful protection mode switches
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode
drivesys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode
drivesys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
drivesys.cpu.kern.swap_context 0 # number of times the context was actually changed
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
drivesys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.tsunami.ethernet.descDMAReads 4850 # Number of descriptors the device read w/ DMA
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.tsunami.ethernet.descDmaReadBytes 116400 # number of descriptor bytes read w/ DMA
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
drivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
drivesys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
drivesys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
drivesys.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
drivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.tsunami.ethernet.postedTxIdle 40 # number of TxIdle interrupts posted to CPU
drivesys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.tsunami.ethernet.totalTxIdle 4850 # total number of TxIdle written to ISR
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
drivesys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.tsunami.ethernet.postedInterrupts 4850 # number of posts to CPU
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
drivesys.iobus.throughput 290488448 # Throughput (bytes/s)
drivesys.iobus.data_through_bus 118328 # Total data (bytes)
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink