gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.824366                       # Number of seconds simulated
sim_ticks                                2824365837500                       # Number of ticks simulated
final_tick                               2824365837500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  90810                       # Simulator instruction rate (inst/s)
host_op_rate                                   110172                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2134851185                       # Simulator tick rate (ticks/s)
host_mem_usage                                 669748                       # Number of bytes of host memory used
host_seconds                                  1322.98                       # Real time elapsed on the host
sim_insts                                   120140086                       # Number of instructions simulated
sim_ops                                     145755972                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker         2176                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           286496                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          1047804                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher     10514048                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          640                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst            32208                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           549728                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher      1343808                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             13778252                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       286496                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst        32208                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          318704                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7259968                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17704                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
system.physmem.bytes_written::realview.ide      2318336                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9596048                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker           34                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst              6722                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             16897                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       164282                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           10                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst               570                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              8613                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher        20997                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                218146                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          113437                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4426                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::realview.ide         36224                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               154097                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker           770                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker           113                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              101437                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              370987                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher      3722623                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           227                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               11404                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              194638                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       475791                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4878352                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         101437                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          11404                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             112841                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2570477                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6268                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::realview.ide          820834                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3397594                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2570477                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          770                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker          113                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             101437                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             377256                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher      3722623                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          227                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              11404                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             194652                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       475791                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide          821174                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                8275946                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        218146                       # Number of read requests accepted
system.physmem.writeReqs                       154097                       # Number of write requests accepted
system.physmem.readBursts                      218146                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     154097                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 13946112                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     15232                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   9610368                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  13778252                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                9596048                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      238                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3916                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          13753                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               13737                       # Per bank write bursts
system.physmem.perBankRdBursts::1               13637                       # Per bank write bursts
system.physmem.perBankRdBursts::2               14389                       # Per bank write bursts
system.physmem.perBankRdBursts::3               14286                       # Per bank write bursts
system.physmem.perBankRdBursts::4               15951                       # Per bank write bursts
system.physmem.perBankRdBursts::5               13008                       # Per bank write bursts
system.physmem.perBankRdBursts::6               13922                       # Per bank write bursts
system.physmem.perBankRdBursts::7               13905                       # Per bank write bursts
system.physmem.perBankRdBursts::8               13614                       # Per bank write bursts
system.physmem.perBankRdBursts::9               13369                       # Per bank write bursts
system.physmem.perBankRdBursts::10              12796                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11719                       # Per bank write bursts
system.physmem.perBankRdBursts::12              13344                       # Per bank write bursts
system.physmem.perBankRdBursts::13              14168                       # Per bank write bursts
system.physmem.perBankRdBursts::14              13355                       # Per bank write bursts
system.physmem.perBankRdBursts::15              12708                       # Per bank write bursts
system.physmem.perBankWrBursts::0                9678                       # Per bank write bursts
system.physmem.perBankWrBursts::1                9778                       # Per bank write bursts
system.physmem.perBankWrBursts::2               10288                       # Per bank write bursts
system.physmem.perBankWrBursts::3                9945                       # Per bank write bursts
system.physmem.perBankWrBursts::4                9066                       # Per bank write bursts
system.physmem.perBankWrBursts::5                9050                       # Per bank write bursts
system.physmem.perBankWrBursts::6                9464                       # Per bank write bursts
system.physmem.perBankWrBursts::7                9420                       # Per bank write bursts
system.physmem.perBankWrBursts::8                9418                       # Per bank write bursts
system.physmem.perBankWrBursts::9                9295                       # Per bank write bursts
system.physmem.perBankWrBursts::10               9149                       # Per bank write bursts
system.physmem.perBankWrBursts::11               8660                       # Per bank write bursts
system.physmem.perBankWrBursts::12               9452                       # Per bank write bursts
system.physmem.perBankWrBursts::13               9588                       # Per bank write bursts
system.physmem.perBankWrBursts::14               9180                       # Per bank write bursts
system.physmem.perBankWrBursts::15               8731                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           6                       # Number of times write queue was full causing retry
system.physmem.totGap                    2824364779500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     559                       # Read request sizes (log2)
system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
system.physmem.readPktSize::4                    3083                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  214476                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4436                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 149661                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     53531                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     76693                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     20729                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     15217                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                     11073                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      9725                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      8854                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      8206                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      7203                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      2475                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1454                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1095                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      641                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      479                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      300                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      216                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        5                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2958                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3567                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4160                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4854                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5584                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6912                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7776                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     8777                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     9674                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    10921                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    10781                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    10780                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    10773                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    11406                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     9525                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     9277                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     9241                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     8653                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      876                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      584                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      425                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      300                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      258                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      224                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      188                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      183                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      162                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      154                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      147                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      143                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      144                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      128                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      102                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       88                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       79                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       72                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       59                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       48                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       30                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       29                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       23                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       23                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       13                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       21                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       14                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        92847                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      253.712882                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     143.703009                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     308.429657                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          46968     50.59%     50.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        18903     20.36%     70.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6762      7.28%     78.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3669      3.95%     82.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         3165      3.41%     85.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         2101      2.26%     87.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1261      1.36%     89.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1081      1.16%     90.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8937      9.63%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          92847                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          7530                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        28.938645                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      528.498472                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           7529     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            7530                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          7530                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        19.941833                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.646034                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       10.689402                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            6119     81.26%     81.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             568      7.54%     88.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              91      1.21%     90.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             218      2.90%     92.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             217      2.88%     95.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              12      0.16%     95.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              20      0.27%     96.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              25      0.33%     96.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              26      0.35%     96.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               8      0.11%     97.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               6      0.08%     97.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               5      0.07%     97.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             157      2.08%     99.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               7      0.09%     99.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               8      0.11%     99.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               4      0.05%     99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              13      0.17%     99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               1      0.01%     99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               1      0.01%     99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               6      0.08%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             2      0.03%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             2      0.03%     99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             2      0.03%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             3      0.04%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             7      0.09%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            7530                       # Writes before turning the bus around for reads
system.physmem.totQLat                     8946488000                       # Total ticks spent queuing
system.physmem.totMemAccLat               13032263000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1089540000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       41056.26                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  59806.26                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.94                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.40                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        4.88                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.40                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.07                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.56                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        23.08                       # Average write queue length when enqueuing
system.physmem.readRowHits                     185273                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     89950                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   85.02                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  59.89                       # Row buffer hit rate for writes
system.physmem.avgGap                      7587422.14                       # Average gap between requests
system.physmem.pageHitRate                      74.77                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     2697372741500                       # Time in different power states
system.physmem.memoryStateTime::REF       94311620000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       32676864750                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.physmem.actEnergy::0                 364906080                       # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1                 337017240                       # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0                 199105500                       # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1                 183888375                       # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0                880113000                       # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1                819569400                       # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0               496944720                       # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1               476105040                       # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0          184473528720                       # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1          184473528720                       # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0           78935898240                       # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1           78466357035                       # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0          1625374711500                       # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1          1625786589750                       # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0            1890725207760                       # Total energy per rank (pJ)
system.physmem.totalEnergy::1            1890543055560                       # Total energy per rank (pJ)
system.physmem.averagePower::0             669.434632                       # Core power per rank (mW)
system.physmem.averagePower::1             669.370138                       # Core power per rank (mW)
system.realview.nvmem.bytes_read::cpu0.inst          128                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          192                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           320                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          128                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          192                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          320                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            8                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             20                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           45                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           68                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              113                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           45                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           68                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          113                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           45                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           68                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             113                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               24027931                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         15718166                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           977317                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            14657289                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               10772949                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            73.498919                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                3877670                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             32392                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    17722563                       # DTB read hits
system.cpu0.dtb.read_misses                     56347                       # DTB read misses
system.cpu0.dtb.write_hits                   14648246                       # DTB write hits
system.cpu0.dtb.write_misses                     8736                       # DTB write misses
system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3529                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      316                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  2360                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      858                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                17778910                       # DTB read accesses
system.cpu0.dtb.write_accesses               14656982                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         32370809                       # DTB hits
system.cpu0.dtb.misses                          65083                       # DTB misses
system.cpu0.dtb.accesses                     32435892                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.inst_hits                    37749898                       # ITB inst hits
system.cpu0.itb.inst_misses                     10270                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2361                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     1943                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                37760168                       # ITB inst accesses
system.cpu0.itb.hits                         37749898                       # DTB hits
system.cpu0.itb.misses                          10270                       # DTB misses
system.cpu0.itb.accesses                     37760168                       # DTB accesses
system.cpu0.numCycles                       126937172                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          18140410                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                     112713647                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   24027931                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches          14650619                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                    104775763                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                2822832                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                    131776                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles               38634                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles       364177                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       430173                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles        37568                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                 37750515                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               265085                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   3932                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         125329917                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             1.084963                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            1.263075                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                62773644     50.09%     50.09% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                21461872     17.12%     67.21% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 8766803      6.99%     74.21% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                32327598     25.79%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           125329917                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.189290                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.887948                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                19211260                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             58677383                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                 41416135                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles              4957927                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1067212                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved             3055574                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred               348409                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts             110727822                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts              3998029                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1067212                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                24961632                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               12004838                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      36556596                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                 40485229                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles             10254410                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts             105647594                       # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts              1060765                       # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents              1435224                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                161199                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                 61281                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents               6055537                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands          109729609                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            482383818                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       120922156                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups             9389                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             98138163                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                11591443                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           1228785                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts       1087461                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 12318010                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads            18735902                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores           16202980                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1699572                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         2289990                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                 102687216                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1694558                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                100671408                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued           483936                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        9020941                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     22487287                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        122833                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    125329917                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.803251                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.034851                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           69186063     55.20%     55.20% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           23179586     18.49%     73.70% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2           22515563     17.97%     91.66% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            9334163      7.45%     99.11% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            1114503      0.89%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5                 39      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      125329917                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                9379139     40.75%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                    80      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead               5583986     24.26%     65.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite              8051096     34.98%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass             2273      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             66410061     65.97%     65.97% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               93146      0.09%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  1      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              2      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc          8111      0.01%     66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead            18430824     18.31%     84.38% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite           15726990     15.62%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total             100671408                       # Type of FU issued
system.cpu0.iq.rate                          0.793081                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                   23014301                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.228608                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         350139117                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes        113410576                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     98583429                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads              31853                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes             11293                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         9723                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses             123662855                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                  20581                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          365420                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      2006460                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2583                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        19225                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores      1022371                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads       106487                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       336614                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1067212                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                1617559                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               190582                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts          104556500                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts             18735902                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts            16202980                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            876211                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 27258                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents               139659                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         19225                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        291750                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       400567                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              692317                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             99574081                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts             17974103                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts          1032379                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       174726                       # number of nop insts executed
system.cpu0.iew.exec_refs                    33509859                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                16843488                       # Number of branches executed
system.cpu0.iew.exec_stores                  15535756                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.784436                       # Inst execution rate
system.cpu0.iew.wb_sent                      99043344                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     98593152                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 51321674                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 84801576                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.776708                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.605197                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts        8525747                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls        1571725                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           633113                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    123576047                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.768210                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.481297                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     79251877     64.13%     64.13% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1     24711108     20.00%     84.13% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      8248464      6.67%     90.80% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      3214478      2.60%     93.40% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      3439388      2.78%     96.19% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5      1513562      1.22%     97.41% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6      1143910      0.93%     98.34% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       534023      0.43%     98.77% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1519237      1.23%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    123576047                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            78902307                       # Number of instructions committed
system.cpu0.commit.committedOps              94932349                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      31910051                       # Number of memory references committed
system.cpu0.commit.loads                     16729442                       # Number of loads committed
system.cpu0.commit.membars                     647161                       # Number of memory barriers committed
system.cpu0.commit.branches                  16205593                       # Number of branches committed
system.cpu0.commit.fp_insts                      9708                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 81881586                       # Number of committed integer instructions.
system.cpu0.commit.function_calls             1929479                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu        62923469     66.28%     66.28% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult          90718      0.10%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc         8111      0.01%     66.39% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.39% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.39% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.39% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead       16729442     17.62%     84.01% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite      15180609     15.99%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total         94932349                       # Class of committed instruction
system.cpu0.commit.bw_lim_events              1519237                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                   221333052                       # The number of ROB reads
system.cpu0.rob.rob_writes                  208669303                       # The number of ROB writes
system.cpu0.timesIdled                         109478                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                        1607255                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  5521794529                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   78780256                       # Number of Instructions Simulated
system.cpu0.committedOps                     94810298                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              1.611282                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        1.611282                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.620624                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.620624                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               110616528                       # number of integer regfile reads
system.cpu0.int_regfile_writes               59738270                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                     8164                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                    2269                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                350776322                       # number of cc regfile reads
system.cpu0.cc_regfile_writes                41073406                       # number of cc regfile writes
system.cpu0.misc_regfile_reads              245816593                       # number of misc regfile reads
system.cpu0.misc_regfile_writes               1224552                       # number of misc regfile writes
system.cpu0.dcache.tags.replacements           712837                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          493.082878                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           28842463                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           713349                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            40.432471                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        256881000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   493.082878                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.963052                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.963052                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          176                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          321                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           15                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         63484078                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        63484078                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     15589241                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       15589241                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     12071944                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      12071944                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       310964                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       310964                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       363200                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       363200                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       360654                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       360654                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     27661185                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        27661185                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     27972149                       # number of overall hits
system.cpu0.dcache.overall_hits::total       27972149                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       638343                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       638343                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1832165                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1832165                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       146120                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       146120                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        24976                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        24976                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20612                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        20612                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      2470508                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       2470508                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      2616628                       # number of overall misses
system.cpu0.dcache.overall_misses::total      2616628                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   8099233830                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   8099233830                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  24956974532                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  24956974532                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    395327755                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    395327755                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    453888287                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total    453888287                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       344500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total       344500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  33056208362                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  33056208362                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  33056208362                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  33056208362                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     16227584                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     16227584                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     13904109                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     13904109                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       457084                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       457084                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       388176                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       388176                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       381266                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       381266                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     30131693                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     30131693                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     30588777                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     30588777                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.039337                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.039337                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.131771                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.131771                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.319679                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.319679                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.064342                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.064342                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.054062                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.054062                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.081990                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.081990                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.085542                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.085542                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12687.902632                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 12687.902632                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 13621.575858                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 13621.575858                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15828.305373                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15828.305373                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22020.584465                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22020.584465                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13380.328403                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 13380.328403                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12633.132552                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 12633.132552                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs         1355                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets      3366874                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs               70                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets         191323                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    19.357143                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    17.597853                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       513073                       # number of writebacks
system.cpu0.dcache.writebacks::total           513073                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       248142                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       248142                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1519584                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1519584                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        18421                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18421                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1767726                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      1767726                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1767726                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      1767726                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       390201                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       390201                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       312581                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       312581                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       101511                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       101511                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6555                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6555                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20612                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total        20612                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       702782                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       702782                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       804293                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       804293                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4170777489                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4170777489                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4999843092                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4999843092                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1415062493                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1415062493                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     97847997                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     97847997                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    411963713                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    411963713                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       324500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       324500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9170620581                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   9170620581                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10585683074                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  10585683074                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   4217063246                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   4217063246                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3187063995                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3187063995                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   7404127241                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   7404127241                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.024046                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.024046                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.022481                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.022481                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.222084                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.222084                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016887                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016887                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.054062                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.054062                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023324                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.023324                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026294                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.026294                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10688.792415                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10688.792415                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15995.351899                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15995.351899                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13939.991656                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13939.991656                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14927.230664                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14927.230664                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19986.595818                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19986.595818                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13049.025987                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13049.025987                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13161.476072                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13161.476072                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          1263629                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.774279                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           36446507                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1264141                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            28.831046                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       6311559000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.774279                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999559                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999559                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          144                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          236                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          132                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         76758780                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        76758780                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     36446507                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       36446507                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     36446507                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        36446507                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     36446507                       # number of overall hits
system.cpu0.icache.overall_hits::total       36446507                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1300794                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1300794                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1300794                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1300794                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1300794                       # number of overall misses
system.cpu0.icache.overall_misses::total      1300794                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  11016728605                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  11016728605                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  11016728605                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  11016728605                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  11016728605                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  11016728605                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     37747301                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     37747301                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     37747301                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     37747301                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     37747301                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     37747301                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.034461                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.034461                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.034461                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.034461                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.034461                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.034461                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  8469.233872                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  8469.233872                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  8469.233872                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  8469.233872                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  8469.233872                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  8469.233872                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs       724171                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets           84                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs            96135                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              2                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs     7.532855                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets           42                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        36615                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        36615                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        36615                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        36615                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        36615                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        36615                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1264179                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1264179                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      1264179                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1264179                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      1264179                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1264179                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   8918143809                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   8918143809                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   8918143809                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   8918143809                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   8918143809                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   8918143809                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    244130748                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    244130748                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    244130748                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    244130748                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.033491                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.033491                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.033491                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.033491                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.033491                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.033491                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  7054.494505                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  7054.494505                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  7054.494505                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  7054.494505                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  7054.494505                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  7054.494505                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified     11567606                       # number of hwpf identified
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr       525705                       # number of hwpf that were already in mshr
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache     10416149                       # number of hwpf that were already in the cache
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher       118627                       # number of hwpf that were already in the prefetch queue
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit        25546                       # number of hwpf removed because MSHR allocated
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued       481574                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page       882370                       # number of hwpf spanning a virtual page
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu0.l2cache.tags.replacements          396542                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16205.769061                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           2244815                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          412792                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            5.438126                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle    2809084521500                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  4618.987809                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     8.979975                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     2.443926                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst   942.112111                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1410.719068                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  9222.526172                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.281921                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000548                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000149                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.057502                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.086103                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.562898                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.989122                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         8075                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024         8170                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::0           46                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1          189                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2         3306                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3         4046                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          488                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            3                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          491                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         3813                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         3549                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4          254                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.492859                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000305                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.498657                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        43582688                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       43582688                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        54105                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker        12184                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.inst      1242379                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.data       407374                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total       1716042                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks       513072                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total       513072                       # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        15340                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total        15340                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         2133                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total         2133                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       216716                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       216716                       # number of ReadExReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        54105                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker        12184                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      1242379                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data       624090                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        1932758                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        54105                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker        12184                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      1242379                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data       624090                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       1932758                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          529                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          208                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.inst        21771                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.data        90784                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total       113292                       # number of ReadReq misses
system.cpu0.l2cache.Writeback_misses::writebacks            1                       # number of Writeback misses
system.cpu0.l2cache.Writeback_misses::total            1                       # number of Writeback misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        27958                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        27958                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        18479                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        18479                       # number of SCUpgradeReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data        52756                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total        52756                       # number of ReadExReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          529                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker          208                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst        21771                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data       143540                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total       166048                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          529                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker          208                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst        21771                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data       143540                       # number of overall misses
system.cpu0.l2cache.overall_misses::total       166048                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     13920749                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      4946000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst    810765185                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data   2694797858                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total   3524429792                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    501186435                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total    501186435                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    362145290                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    362145290                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       314500                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       314500                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2597613271                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total   2597613271                       # number of ReadExReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     13920749                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      4946000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst    810765185                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data   5292411129                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total   6122043063                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     13920749                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      4946000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst    810765185                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data   5292411129                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total   6122043063                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        54634                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker        12392                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      1264150                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.data       498158                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total      1829334                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks       513073                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total       513073                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        43298                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        43298                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        20612                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        20612                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       269472                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       269472                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        54634                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker        12392                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      1264150                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data       767630                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      2098806                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        54634                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker        12392                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      1264150                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data       767630                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      2098806                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.009683                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.016785                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.017222                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.182239                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.061931                       # miss rate for ReadReq accesses
system.cpu0.l2cache.Writeback_miss_rate::writebacks     0.000002                       # miss rate for Writeback accesses
system.cpu0.l2cache.Writeback_miss_rate::total     0.000002                       # miss rate for Writeback accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.645711                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.645711                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.896517                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.896517                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.195775                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.195775                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.009683                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.016785                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.017222                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.186991                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.079115                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.009683                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.016785                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.017222                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.186991                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.079115                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26315.215501                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23778.846154                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 37240.603785                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29683.621101                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31109.255658                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17926.405143                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17926.405143                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19597.667082                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19597.667082                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data          inf                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49238.252919                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49238.252919                       # average ReadExReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26315.215501                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23778.846154                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37240.603785                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36870.636262                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 36869.116539                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26315.215501                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23778.846154                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37240.603785                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36870.636262                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 36869.116539                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs        65149                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs            1474                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    44.198779                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks       211864                       # number of writebacks
system.cpu0.l2cache.writebacks::total          211864                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            1                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst         5535                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data         3178                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total         8714                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         8807                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         8807                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker            1                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst         5535                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data        11985                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total        17521                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker            1                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst         5535                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data        11985                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total        17521                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          529                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          207                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst        16236                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data        87606                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total       104578                       # number of ReadReq MSHR misses
system.cpu0.l2cache.Writeback_mshr_misses::writebacks            1                       # number of Writeback MSHR misses
system.cpu0.l2cache.Writeback_mshr_misses::total            1                       # number of Writeback MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       481571                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       481571                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        27958                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total        27958                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        18479                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        18479                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        43949                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total        43949                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          529                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          207                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        16236                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data       131555                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total       148527                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          529                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          207                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        16236                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data       131555                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       481571                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total       630098                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     10212251                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      3484000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst    587444763                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data   2008905945                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total   2610046959                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  21960966186                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  21960966186                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    481827867                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    481827867                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    249217743                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    249217743                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       244500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       244500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1317766861                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1317766861                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     10212251                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      3484000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst    587444763                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   3326672806                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total   3927813820                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     10212251                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      3484000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst    587444763                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   3326672806                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  21960966186                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  25888780006                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    218713750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   4053860233                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   4272573983                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   3040265950                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   3040265950                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    218713750                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   7094126183                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   7312839933                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.009683                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.016704                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.012843                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.175860                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.057167                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks     0.000002                       # mshr miss rate for Writeback accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::total     0.000002                       # mshr miss rate for Writeback accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.645711                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.645711                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.896517                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.896517                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.163093                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.163093                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.009683                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.016704                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.012843                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.171378                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.070767                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.009683                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.016704                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.012843                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.171378                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.300217                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19304.822306                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16830.917874                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36181.618810                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22931.145641                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24957.897062                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45602.758858                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45602.758858                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17233.989091                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17233.989091                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13486.538395                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13486.538395                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 29984.001024                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 29984.001024                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19304.822306                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16830.917874                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 36181.618810                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 25287.315617                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26445.116511                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19304.822306                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16830.917874                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 36181.618810                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 25287.315617                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45602.758858                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 41086.910300                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq       2021884                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      1920690                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        19107                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        19107                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback       513073                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       646583                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq        36230                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        80962                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        43193                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       104964                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           11                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           21                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       291894                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       281156                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      2534332                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2360691                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        28712                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       120464                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          5044199                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     80953568                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     86204446                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        49568                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       218536                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         167426118                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    1040274                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples      3610797                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       5.254659                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.435670                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::5           2691274     74.53%     74.53% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::6            919523     25.47%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       3610797                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy    1890423984                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    117333499                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   1901305348                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   1220101128                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy     16329482                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy     65866183                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups               33911271                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         11563003                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           305102                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            18755199                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits               14959397                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            79.761334                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS               12490268                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect              7230                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    10163694                       # DTB read hits
system.cpu1.dtb.read_misses                     18763                       # DTB read misses
system.cpu1.dtb.write_hits                    6542250                       # DTB write hits
system.cpu1.dtb.write_misses                     2833                       # DTB write misses
system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    2049                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                       53                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   373                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      411                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                10182457                       # DTB read accesses
system.cpu1.dtb.write_accesses                6545083                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         16705944                       # DTB hits
system.cpu1.dtb.misses                          21596                       # DTB misses
system.cpu1.dtb.accesses                     16727540                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.inst_hits                    43642438                       # ITB inst hits
system.cpu1.itb.inst_misses                      7000                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1205                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                      538                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                43649438                       # ITB inst accesses
system.cpu1.itb.hits                         43642438                       # DTB hits
system.cpu1.itb.misses                           7000                       # DTB misses
system.cpu1.itb.accesses                     43649438                       # DTB accesses
system.cpu1.numCycles                       104622324                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles           9983715                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                     109168018                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                   33911271                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches          27449665                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     91793931                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                3775602                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                     78298                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles               31640                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles       200637                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       294928                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles         7575                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                 43641835                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               116209                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   2258                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         104278525                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.296897                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            1.339782                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                47329971     45.39%     45.39% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                14035379     13.46%     58.85% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                 7536372      7.23%     66.07% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                35376803     33.93%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           104278525                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.324130                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       1.043449                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                13017622                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             61671390                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                 26724772                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles              1111637                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               1753104                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved              754173                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred               137598                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              68061604                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts              1168958                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               1753104                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                17450100                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                2254257                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      56981217                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                 23380222                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              2459625                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              55156752                       # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts               230613                       # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents               263389                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                 35416                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                 18082                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents               1432431                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands           55002738                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            260522478                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups        58680214                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups             1689                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             52222609                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                 2780129                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts           1878054                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts       1805384                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                 13101359                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            10457131                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            6914141                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads           629237                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores          831086                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  54264809                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             589071                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 53908897                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued           111732                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined        2292977                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined      5809537                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved         48790                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    104278525                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.516970                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       0.852578                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           71027306     68.11%     68.11% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1           16528003     15.85%     83.96% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2           13076309     12.54%     96.50% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            3359364      3.22%     99.72% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4             287531      0.28%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5                 12      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      104278525                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                2925381     45.12%     45.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                   677      0.01%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead               1673591     25.81%     70.94% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite              1884116     29.06%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass               66      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             36727260     68.13%     68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               46535      0.09%     68.21% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     68.21% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     68.21% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.21% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.21% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.21% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.21% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  2      0.00%     68.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 1      0.00%     68.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc          3339      0.01%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            10380151     19.25%     87.48% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            6751543     12.52%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              53908897                       # Type of FU issued
system.cpu1.iq.rate                          0.515271                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    6483765                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.120273                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         218686026                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         57154966                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     51920427                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads               5790                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              2052                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         1786                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              60388895                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   3701                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads           91393                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads       490676                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses          687                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        10193                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores       356081                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads        51970                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked        70495                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               1753104                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                 548003                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles               114295                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           54906042                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             10457131                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             6914141                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            301584                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                  9824                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                96972                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         10193                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect         54960                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       127313                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              182273                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             53638837                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             10278190                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           248481                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                        52162                       # number of nop insts executed
system.cpu1.iew.exec_refs                    16965416                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                11807917                       # Number of branches executed
system.cpu1.iew.exec_stores                   6687226                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.512690                       # Inst execution rate
system.cpu1.iew.wb_sent                      53497875                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     51922213                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 25229776                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 38490454                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.496282                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.655481                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts        3658692                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         540281                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           170405                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    102346479                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.498098                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.159114                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     76767559     75.01%     75.01% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1     14288132     13.96%     88.97% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      6080244      5.94%     94.91% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3       703970      0.69%     95.60% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4      1980102      1.93%     97.53% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5      1566998      1.53%     99.06% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6       444730      0.43%     99.50% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       123732      0.12%     99.62% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8       391012      0.38%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    102346479                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            41392684                       # Number of instructions committed
system.cpu1.commit.committedOps              50978528                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      16524515                       # Number of memory references committed
system.cpu1.commit.loads                      9966455                       # Number of loads committed
system.cpu1.commit.membars                     209698                       # Number of memory barriers committed
system.cpu1.commit.branches                  11639872                       # Number of branches committed
system.cpu1.commit.fp_insts                      1784                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 45828467                       # Number of committed integer instructions.
system.cpu1.commit.function_calls             3366626                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu        34405041     67.49%     67.49% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult          45633      0.09%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc         3339      0.01%     67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead        9966455     19.55%     87.14% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite       6558060     12.86%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total         50978528                       # Class of committed instruction
system.cpu1.commit.bw_lim_events               391012                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                   136555973                       # The number of ROB reads
system.cpu1.rob.rob_writes                  111202855                       # The number of ROB writes
system.cpu1.timesIdled                          53415                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                         343799                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  5543567058                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   41359830                       # Number of Instructions Simulated
system.cpu1.committedOps                     50945674                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              2.529564                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        2.529564                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.395325                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.395325                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                56285102                       # number of integer regfile reads
system.cpu1.int_regfile_writes               35740910                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                     1413                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                     520                       # number of floating regfile writes
system.cpu1.cc_regfile_reads                191162273                       # number of cc regfile reads
system.cpu1.cc_regfile_writes                15560809                       # number of cc regfile writes
system.cpu1.misc_regfile_reads              205875636                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                388862                       # number of misc regfile writes
system.cpu1.dcache.tags.replacements           191071                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          472.558495                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs           15741437                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           191395                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            82.245811                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     102871508500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   472.558495                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.922966                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.922966                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          324                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          320                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.632812                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         32983767                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        32983767                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      9574609                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        9574609                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      5910607                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       5910607                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data        49573                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total        49573                       # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        79145                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        79145                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        71001                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        71001                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data     15485216                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total        15485216                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data     15534789                       # number of overall hits
system.cpu1.dcache.overall_hits::total       15534789                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       219415                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       219415                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       398307                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       398307                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30093                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total        30093                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        18121                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        18121                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23394                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        23394                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       617722                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        617722                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       647815                       # number of overall misses
system.cpu1.dcache.overall_misses::total       647815                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   3455998019                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   3455998019                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   8728631208                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   8728631208                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    363006249                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    363006249                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    542688316                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total    542688316                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       504500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total       504500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  12184629227                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  12184629227                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  12184629227                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  12184629227                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      9794024                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      9794024                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      6308914                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      6308914                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        79666                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total        79666                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        97266                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        97266                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        94395                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        94395                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data     16102938                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     16102938                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data     16182604                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     16182604                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.022403                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.022403                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.063134                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.063134                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.377740                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.377740                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.186304                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.186304                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.247831                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.247831                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.038361                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.038361                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.040032                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.040032                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15750.965153                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15750.965153                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21914.330424                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 21914.330424                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20032.351912                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20032.351912                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23197.756519                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23197.756519                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19725.101627                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 19725.101627                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18808.809964                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 18808.809964                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs          357                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets      1112453                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs               37                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets          39616                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs     9.648649                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets    28.080902                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       117473                       # number of writebacks
system.cpu1.dcache.writebacks::total           117473                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        79558                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        79558                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       306502                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total       306502                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        13187                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        13187                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data       386060                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total       386060                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data       386060                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total       386060                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       139857                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       139857                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        91805                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        91805                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        28628                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total        28628                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4934                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4934                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23394                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        23394                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       231662                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       231662                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       260290                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       260290                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1829354050                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1829354050                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2195265722                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2195265722                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    493416244                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    493416244                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     87143250                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     87143250                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    494733684                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    494733684                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       482500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       482500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4024619772                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   4024619772                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4518036016                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   4518036016                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2298838492                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2298838492                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1826630495                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   1826630495                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   4125468987                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   4125468987                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.014280                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.014280                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014552                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.014552                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.359350                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.359350                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.050727                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.050727                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.247831                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.247831                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.014386                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.014386                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.016085                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.016085                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13080.175107                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13080.175107                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23912.267545                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23912.267545                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17235.442364                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17235.442364                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17661.785570                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17661.785570                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21147.887664                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21147.887664                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17372.809403                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17372.809403                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17357.701087                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17357.701087                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements           607164                       # number of replacements
system.cpu1.icache.tags.tagsinuse          499.524787                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs           43017402                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           607676                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            70.790030                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      78589984500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.524787                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975634                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.975634                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          495                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3           17                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         87891037                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        87891037                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst     43017402                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       43017402                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     43017402                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        43017402                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     43017402                       # number of overall hits
system.cpu1.icache.overall_hits::total       43017402                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       624277                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       624277                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       624277                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        624277                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       624277                       # number of overall misses
system.cpu1.icache.overall_misses::total       624277                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5095487535                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   5095487535                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   5095487535                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   5095487535                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   5095487535                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   5095487535                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     43641679                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     43641679                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     43641679                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     43641679                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     43641679                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     43641679                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.014305                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.014305                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.014305                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.014305                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.014305                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.014305                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8162.222115                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  8162.222115                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8162.222115                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  8162.222115                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8162.222115                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  8162.222115                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs       276500                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs            36143                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs     7.650167                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        16598                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total        16598                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst        16598                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total        16598                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst        16598                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total        16598                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       607679                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       607679                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       607679                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       607679                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       607679                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       607679                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4104857215                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   4104857215                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4104857215                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   4104857215                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4104857215                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   4104857215                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8190250                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8190250                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8190250                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      8190250                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.013924                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.013924                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.013924                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.013924                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.013924                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.013924                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  6754.976254                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  6754.976254                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  6754.976254                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  6754.976254                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  6754.976254                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  6754.976254                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified      4841342                       # number of hwpf identified
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr        43201                       # number of hwpf that were already in mshr
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache      4639993                       # number of hwpf that were already in the cache
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher        42894                       # number of hwpf that were already in the prefetch queue
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit         5995                       # number of hwpf removed because MSHR allocated
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued       109259                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page       564002                       # number of hwpf spanning a virtual page
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu1.l2cache.tags.replacements           85775                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       15600.933964                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs            846435                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs          100895                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            8.389266                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  5997.093337                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    10.379548                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     1.187782                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst   717.531946                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data  1990.637648                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  6884.103702                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.366034                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000634                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000072                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.043795                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.121499                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.420172                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.952205                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         9541                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           25                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024         5554                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          314                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3         8089                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4         1138                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            9                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           13                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            3                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          428                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4157                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4          969                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.582336                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.001526                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.338989                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        16876081                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       16876081                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        16270                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         7392                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.inst       601743                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.data       101269                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total        726674                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks       117472                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total       117472                       # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         2261                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total         2261                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data          802                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total          802                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data        28891                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        28891                       # number of ReadExReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        16270                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         7392                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst       601743                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data       130160                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total         755565                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        16270                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         7392                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst       601743                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data       130160                       # number of overall hits
system.cpu1.l2cache.overall_hits::total        755565                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          463                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          277                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.inst         5933                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.data        72130                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        78803                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        28401                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        28401                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22590                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        22590                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            2                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            2                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data        32934                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        32934                       # number of ReadExReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          463                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          277                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst         5933                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data       105064                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total       111737                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          463                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          277                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst         5933                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data       105064                       # number of overall misses
system.cpu1.l2cache.overall_misses::total       111737                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     10189999                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      5582499                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst    184105701                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data   1612613119                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total   1812491318                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    537520391                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total    537520391                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    443077527                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    443077527                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data       471499                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       471499                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1278985047                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   1278985047                       # number of ReadExReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     10189999                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      5582499                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst    184105701                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data   2891598166                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total   3091476365                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     10189999                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      5582499                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst    184105701                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data   2891598166                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total   3091476365                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        16733                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         7669                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst       607676                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.data       173399                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total       805477                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks       117472                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total       117472                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        30662                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        30662                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23392                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        23392                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        61825                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total        61825                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        16733                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         7669                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst       607676                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data       235224                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total       867302                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        16733                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         7669                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst       607676                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data       235224                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total       867302                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.027670                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.036119                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.009763                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.415977                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.097834                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.926261                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.926261                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.965715                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.965715                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.532697                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.532697                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.027670                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.036119                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.009763                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.446655                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.128833                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.027670                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.036119                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.009763                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.446655                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.128833                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22008.637149                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20153.425993                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 31030.794033                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22357.037557                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23000.283213                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18926.107919                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18926.107919                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19613.879017                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19613.879017                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 235749.500000                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 235749.500000                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38834.792221                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38834.792221                       # average ReadExReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22008.637149                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20153.425993                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 31030.794033                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27522.254683                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 27667.436615                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22008.637149                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20153.425993                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 31030.794033                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27522.254683                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 27667.436615                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs        22985                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs             493                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    46.622718                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks        40759                       # number of writebacks
system.cpu1.l2cache.writebacks::total           40759                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker           13                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst         1321                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data           73                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total         1407                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         1252                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total         1252                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker           13                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst         1321                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data         1325                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total         2659                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker           13                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst         1321                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data         1325                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total         2659                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          463                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          264                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst         4612                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data        72057                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total        77396                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       109257                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total       109257                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        28401                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total        28401                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22590                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22590                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        31682                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total        31682                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          463                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          264                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst         4612                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data       103739                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total       109078                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          463                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          264                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst         4612                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data       103739                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       109257                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total       218335                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      6946001                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3570001                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst    126408787                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data   1106793437                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total   1243718226                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   3470833266                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   3470833266                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    417527555                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    417527555                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    308789786                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    308789786                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       394499                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       394499                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data    943695401                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total    943695401                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      6946001                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3570001                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    126408787                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2050488838                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total   2187413627                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      6946001                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3570001                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    126408787                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2050488838                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   3470833266                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total   5658246893                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      7340750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2182197007                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2189537757                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   1737457999                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   1737457999                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      7340750                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   3919655006                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   3926995756                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.027670                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.034424                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.007590                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.415556                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.096087                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.926261                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.926261                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.965715                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.965715                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.512446                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.512446                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.027670                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.034424                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.007590                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.441022                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.125767                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.027670                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.034424                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.007590                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.441022                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.251740                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15002.161987                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13522.731061                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27408.670208                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15359.971092                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16069.541397                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31767.605426                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31767.605426                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14701.156825                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14701.156825                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13669.313236                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13669.313236                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 197249.500000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 197249.500000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29786.484471                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29786.484471                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15002.161987                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13522.731061                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27408.670208                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19765.843492                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20053.664598                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15002.161987                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13522.731061                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27408.670208                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19765.843492                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31767.605426                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25915.436797                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq       1294408                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp       865128                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq        11871                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp        11871                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback       117472                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq       157468                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq        36230                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        84838                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41861                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        87109                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           12                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           21                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq        79574                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp        66376                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1215557                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       825064                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        17352                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        37871                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          2095844                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     38892880                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     25436874                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        30676                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        66932                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total          64427362                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                     834611                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples      1797339                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       5.418381                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.493294                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::5           1045366     58.16%     58.16% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::6            751973     41.84%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total       1797339                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy     659657903                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy     81258998                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy    912908354                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy    403842529                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy      9825216                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy     21209360                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                31016                       # Transaction distribution
system.iobus.trans_dist::ReadResp               31016                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59408                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59439                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateReq           31                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56654                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       107968                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72942                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72942                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  180910                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71598                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       162848                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321208                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321208                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2484056                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             40134000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                90000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           326664315                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            84753000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36832361                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36453                       # number of replacements
system.iocache.tags.tagsinuse               14.560247                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36469                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         254140674000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide    14.560247                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.910015                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.910015                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328487                       # Number of tag accesses
system.iocache.tags.data_accesses              328487                       # Number of data accesses
system.iocache.WriteInvalidateReq_hits::realview.ide        36224                       # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total        36224                       # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::realview.ide          247                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              247                       # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide           31                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total           31                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ide          247                       # number of demand (read+write) misses
system.iocache.demand_misses::total               247                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          247                       # number of overall misses
system.iocache.overall_misses::total              247                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     30832377                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     30832377                       # number of ReadReq miss cycles
system.iocache.demand_miss_latency::realview.ide     30832377                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     30832377                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     30832377                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     30832377                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          247                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            247                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide        36255                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        36255                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          247                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             247                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          247                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            247                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide     0.000855                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total     0.000855                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 124827.437247                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 124827.437247                       # average ReadReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 124827.437247                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 124827.437247                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 124827.437247                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 124827.437247                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                      36224                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_misses::realview.ide          247                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          247                       # number of ReadReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          247                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          247                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          247                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          247                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     17987377                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     17987377                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   2253111299                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2253111299                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     17987377                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     17987377                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     17987377                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     17987377                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72823.388664                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 72823.388664                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide          inf                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 72823.388664                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 72823.388664                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 72823.388664                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 72823.388664                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   153470                       # number of replacements
system.l2c.tags.tagsinuse                64454.116988                       # Cycle average of tags in use
system.l2c.tags.total_refs                     519887                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   218097                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.383742                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   14115.348135                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    14.484821                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     2.876495                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     1418.724430                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2146.622945                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 39266.214752                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     5.503287                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker     0.002749                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      292.346121                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      885.503464                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  6306.489787                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.215383                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000221                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000044                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.021648                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.032755                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.599155                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000084                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.004461                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.013512                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.096229                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.983492                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        44297                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        20314                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          411                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         7726                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        36160                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           14                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0            5                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          331                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         4599                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        15358                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.675919                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.000244                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.309967                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  6595063                       # Number of tag accesses
system.l2c.tags.data_accesses                 6595063                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker          272                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker          133                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst              12554                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data              38932                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher       181919                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker           84                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker           48                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst               4143                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data              11543                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher        44205                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                 293833                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          252624                       # number of Writeback hits
system.l2c.Writeback_hits::total               252624                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data           11705                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             720                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               12425                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           181                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           174                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               355                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data             3713                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data             1233                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 4946                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker           272                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker           133                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst               12554                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data               42645                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher       181919                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker            84                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker            48                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst                4143                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               12776                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher        44205                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  298779                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker          272                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker          133                       # number of overall hits
system.l2c.overall_hits::cpu0.inst              12554                       # number of overall hits
system.l2c.overall_hits::cpu0.data              42645                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher       181919                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker           84                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker           48                       # number of overall hits
system.l2c.overall_hits::cpu1.inst               4143                       # number of overall hits
system.l2c.overall_hits::cpu1.data              12776                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher        44205                       # number of overall hits
system.l2c.overall_hits::total                 298779                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker           34                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            5                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             3728                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             8660                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher       164285                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           10                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst              483                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             1392                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher        21015                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               199613                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          8842                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          2853                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             11695                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          749                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         1205                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1954                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data           7764                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           7212                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              14976                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker           34                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            5                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              3728                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             16424                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       164285                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           10                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst               483                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              8604                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher        21015                       # number of demand (read+write) misses
system.l2c.demand_misses::total                214589                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           34                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            5                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             3728                       # number of overall misses
system.l2c.overall_misses::cpu0.data            16424                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       164285                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           10                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst              483                       # number of overall misses
system.l2c.overall_misses::cpu1.data             8604                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher        21015                       # number of overall misses
system.l2c.overall_misses::total               214589                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      2728250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       375000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    350452746                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    764076744                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher  19012823834                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       769500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker        74500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst     49625500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    122837500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher   2533288397                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    22837051971                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      6562735                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      2836384                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      9399119                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1040457                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      1019459                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      2059916                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data    712108661                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    561982732                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   1274091393                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      2728250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       375000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    350452746                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   1476185405                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  19012823834                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker       769500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker        74500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst     49625500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    684820232                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher   2533288397                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     24111143364                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      2728250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       375000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    350452746                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   1476185405                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  19012823834                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker       769500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker        74500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst     49625500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    684820232                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher   2533288397                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    24111143364                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker          306                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker          138                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst          16282                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data          47592                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher       346204                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker           94                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker           49                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst           4626                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data          12935                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher        65220                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total             493446                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       252624                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           252624                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        20547                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         3573                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           24120                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          930                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         1379                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          2309                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data        11477                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data         8445                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            19922                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker          306                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker          138                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst           16282                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data           59069                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       346204                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker           94                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker           49                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst            4626                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           21380                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher        65220                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              513368                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker          306                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker          138                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst          16282                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data          59069                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       346204                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker           94                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker           49                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst           4626                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          21380                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher        65220                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             513368                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.111111                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.036232                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.228965                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.181963                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.474532                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.106383                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.020408                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.104410                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.107615                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.322217                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.404529                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.430330                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.798489                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.484867                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.805376                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.873822                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.846254                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.676483                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.853996                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.751732                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.111111                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.036232                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.228965                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.278048                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.474532                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.106383                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.020408                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.104410                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.402432                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.322217                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.418002                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.111111                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.036232                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.228965                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.278048                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.474532                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.106383                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.020408                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.104410                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.402432                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.322217                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.418002                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 80242.647059                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        75000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 94005.564914                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 88230.570901                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 115730.735210                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        76950                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker        74500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 102744.306418                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 88245.330460                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 120546.676041                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 114406.636697                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   742.222913                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   994.175955                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   803.686960                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1389.128171                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   846.024066                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  1054.204708                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 91719.302035                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77923.285080                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 85075.547075                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 80242.647059                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        75000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 94005.564914                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 89879.773807                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 115730.735210                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        76950                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker        74500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 102744.306418                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 79593.239424                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 120546.676041                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 112359.642684                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 80242.647059                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        75000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 94005.564914                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 89879.773807                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 115730.735210                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        76950                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker        74500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 102744.306418                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 79593.239424                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 120546.676041                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 112359.642684                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs               853                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                       17                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs     50.176471                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks              113437                       # number of writebacks
system.l2c.writebacks::total                   113437                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.data             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher            3                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             2                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher           18                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                24                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.data              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher            3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              2                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher           18                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 24                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.data             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher            3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             2                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher           18                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                24                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           34                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            5                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         3728                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         8659                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       164282                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           10                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst          481                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         1392                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher        20997                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          199589                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         8842                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         2853                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        11695                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          749                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1205                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1954                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data         7764                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         7212                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         14976                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           34                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            5                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         3728                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        16423                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       164282                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           10                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst          481                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         8604                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher        20997                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           214565                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           34                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            5                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         3728                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        16423                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       164282                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           10                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst          481                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         8604                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher        20997                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          214565                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      2306250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       312500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    304401246                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    656530744                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher  16993327084                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       644500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker        62500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     43489500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    105535000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher   2275742147                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  20382351471                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     89515758                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     28874331                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    118390089                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      7686202                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     12118693                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     19804895                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data    616004335                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    470989766                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   1086994101                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      2306250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       312500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    304401246                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   1272535079                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  16993327084                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       644500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker        62500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst     43489500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    576524766                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher   2275742147                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  21469345572                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      2306250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       312500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    304401246                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   1272535079                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  16993327084                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       644500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker        62500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst     43489500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    576524766                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   2275742147                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  21469345572                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    159081750                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3686344747                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      5350750                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   1919845500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   5770622747                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2713919500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1535238000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   4249157500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    159081750                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   6400264247                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      5350750                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   3455083500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  10019780247                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.111111                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.036232                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.228965                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.181942                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.474524                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.106383                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.020408                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.103978                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.107615                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.321941                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.404480                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.430330                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.798489                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.484867                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.805376                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.873822                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.846254                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.676483                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.853996                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.751732                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.111111                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.036232                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.228965                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.278031                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.474524                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.106383                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.020408                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.103978                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.402432                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.321941                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.417956                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.111111                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.036232                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.228965                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.278031                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.474524                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.106383                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.020408                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.103978                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.402432                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.321941                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.417956                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 81652.694742                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 75820.619471                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103439.981763                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        64450                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 90414.760915                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75815.373563                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108384.157118                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 102121.617279                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10123.926487                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10120.690852                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10123.137153                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10261.951936                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10057.006639                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10135.565507                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79341.104456                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65306.401276                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 72582.405248                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 81652.694742                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77484.934482                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103439.981763                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        64450                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 90414.760915                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67006.597629                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108384.157118                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 100059.867975                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 81652.694742                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77484.934482                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103439.981763                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        64450                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 90414.760915                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67006.597629                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108384.157118                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 100059.867975                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              237839                       # Transaction distribution
system.membus.trans_dist::ReadResp             237839                       # Transaction distribution
system.membus.trans_dist::WriteReq              30978                       # Transaction distribution
system.membus.trans_dist::WriteResp             30978                       # Transaction distribution
system.membus.trans_dist::Writeback            113437                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            79519                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          40695                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           13753                       # Transaction distribution
system.membus.trans_dist::ReadExReq             31200                       # Transaction distribution
system.membus.trans_dist::ReadExResp            14872                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107968                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           40                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13742                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       708866                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       830616                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72710                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72710                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 903326                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162848                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          320                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27484                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     21055004                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     21245656                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2319296                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2319296                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                23564952                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           123021                       # Total snoops (count)
system.membus.snoop_fanout::samples            500917                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  500917    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              500917                       # Request fanout histogram
system.membus.reqLayer0.occupancy            81243492                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               26500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            11638997                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          1642210248                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
system.membus.respLayer2.occupancy         2114152611                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer3.occupancy           38560639                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.toL2Bus.trans_dist::ReadReq             659694                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            659679                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             30978                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            30978                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           252624                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq        36230                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           91840                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         41050                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         132890                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           21                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           21                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            40171                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           40171                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1298541                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       426600                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1725141                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     40737982                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      8560538                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               49298520                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          291438                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          1083643                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.033661                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.180356                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                1047166     96.63%     96.63% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                  36477      3.37%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            1083643                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         1586607093                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          1044000                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        2272505602                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         846502909                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    1854                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2770                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------