gem5/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt

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---------- Begin Simulation Statistics ----------
sim_seconds 0.000018 # Number of seconds simulated
sim_ticks 18326500 # Number of ticks simulated
final_tick 18326500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 41507 # Simulator instruction rate (inst/s)
host_op_rate 41499 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 131284333 # Simulator tick rate (ticks/s)
host_mem_usage 224304 # Number of bytes of host memory used
host_seconds 0.14 # Real time elapsed on the host
sim_insts 5792 # Number of instructions simulated
sim_ops 5792 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory
system.physmem.bytes_read::total 28544 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 22080 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 22080 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 345 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory
system.physmem.num_reads::total 446 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1204812703 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 352713284 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1557525987 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1204812703 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1204812703 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1204812703 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 352713284 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1557525987 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 446 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
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system.physmem.cpureqs 446 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 28544 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 28544 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 70 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 54 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 59 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 53 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 61 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 52 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 13 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 8 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 28 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 2 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 4 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 18199000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 446 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 248 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 40 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 66 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 306.424242 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 157.375410 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 461.580898 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64 31 46.97% 46.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128 7 10.61% 57.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192 7 10.61% 68.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256 4 6.06% 74.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320 2 3.03% 77.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384 1 1.52% 78.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448 1 1.52% 80.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512 2 3.03% 83.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576 3 4.55% 87.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704 2 3.03% 90.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960 1 1.52% 92.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088 2 3.03% 95.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920 1 1.52% 96.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984 1 1.52% 98.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304 1 1.52% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 66 # Bytes accessed per row activation
system.physmem.totQLat 2004500 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 10972000 # Sum of mem lat for all requests
system.physmem.totBusLat 2230000 # Total cycles spent in databus access
system.physmem.totBankLat 6737500 # Total cycles spent in bank access
system.physmem.avgQLat 4494.39 # Average queueing delay per request
system.physmem.avgBankLat 15106.50 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 24600.90 # Average memory access latency
system.physmem.avgRdBW 1557.53 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 1557.53 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 12.17 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.60 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 380 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 85.20 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 40804.93 # Average gap between requests
system.membus.throughput 1557525987 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 399 # Transaction distribution
system.membus.trans_dist::ReadResp 399 # Transaction distribution
system.membus.trans_dist::ReadExReq 47 # Transaction distribution
system.membus.trans_dist::ReadExResp 47 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side 892 # Packet count per connected master and slave (bytes)
system.membus.pkt_count 892 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 28544 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size 28544 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 28544 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 559500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 3.1 # Layer utilization (%)
system.membus.respLayer1.occupancy 4174500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 22.8 # Layer utilization (%)
system.cpu.branchPred.lookups 2238 # Number of BP lookups
system.cpu.branchPred.condPredicted 1804 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 1851 # Number of BTB lookups
system.cpu.branchPred.BTBHits 603 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 32.576985 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 199 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions.
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 9 # Number of system calls
system.cpu.numCycles 36654 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 7507 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 13158 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2238 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 802 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 2262 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1292 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 1225 # Number of cycles fetch has spent blocked
system.cpu.fetch.CacheLines 1813 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 312 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 11857 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.109724 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.526984 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 9595 80.92% 80.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 178 1.50% 82.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 176 1.48% 83.91% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 141 1.19% 85.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 227 1.91% 87.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 133 1.12% 88.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 257 2.17% 90.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 110 0.93% 91.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 1040 8.77% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 11857 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.061057 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.358979 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 7580 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 1390 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 2096 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 81 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 710 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 341 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 154 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 11719 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 436 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 710 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 7768 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 673 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 449 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 1984 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 273 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 11300 # Number of instructions processed by rename
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system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 232 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 9692 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 18178 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 18123 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 4694 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 27 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 580 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 2023 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1831 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 10310 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 8903 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 241 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 4245 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 3499 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 11857 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.750864 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.481785 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 8486 71.57% 71.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1113 9.39% 80.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 789 6.65% 87.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 496 4.18% 91.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 461 3.89% 95.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 303 2.56% 98.24% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 131 1.10% 99.34% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 45 0.38% 99.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 33 0.28% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 11857 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 8 4.68% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 71 41.52% 46.20% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 92 53.80% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 5478 61.53% 61.53% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.53% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.53% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 1796 20.17% 81.73% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1627 18.27% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 8903 # Type of FU issued
system.cpu.iq.rate 0.242893 # Inst issue rate
system.cpu.iq.fu_busy_cnt 171 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.019207 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 30013 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 14583 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 8130 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 9040 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 66 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1062 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 785 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 710 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 456 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 10367 # Number of instructions dispatched to IQ
2012-11-02 17:50:06 +01:00
system.cpu.iew.iewDispSquashedInsts 55 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2023 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1831 # Number of dispatched store instructions
2012-11-02 17:50:06 +01:00
system.cpu.iew.iewDispNonSpecInsts 48 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations
2012-11-02 17:50:06 +01:00
system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 262 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 328 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 8502 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 1678 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 401 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 3201 # number of memory reference insts executed
system.cpu.iew.exec_branches 1351 # Number of branches executed
system.cpu.iew.exec_stores 1523 # Number of stores executed
system.cpu.iew.exec_rate 0.231953 # Inst execution rate
system.cpu.iew.wb_sent 8272 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 8157 # cumulative count of insts written-back
system.cpu.iew.wb_producers 4222 # num instructions producing a value
system.cpu.iew.wb_consumers 6684 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.222541 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.631658 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 4581 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards
2012-11-02 17:50:06 +01:00
system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 11147 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.519602 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.320329 # Number of insts commited each cycle
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 8765 78.63% 78.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 1011 9.07% 87.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 612 5.49% 93.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 265 2.38% 95.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 170 1.53% 97.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 108 0.97% 98.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 71 0.64% 98.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 44 0.39% 99.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 101 0.91% 100.00% # Number of insts commited each cycle
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 11147 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5792 # Number of instructions committed
system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 2007 # Number of memory references committed
system.cpu.commit.loads 961 # Number of loads committed
2011-04-20 03:45:23 +02:00
system.cpu.commit.membars 7 # Number of memory barriers committed
system.cpu.commit.branches 1037 # Number of branches committed
system.cpu.commit.fp_insts 22 # Number of committed floating point instructions.
system.cpu.commit.int_insts 5698 # Number of committed integer instructions.
system.cpu.commit.function_calls 103 # Number of function calls committed.
system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 21419 # The number of ROB reads
system.cpu.rob.rob_writes 21457 # The number of ROB writes
system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 24797 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5792 # Number of Instructions Simulated
system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 5792 # Number of Instructions Simulated
system.cpu.cpi 6.328384 # CPI: Cycles Per Instruction
system.cpu.cpi_total 6.328384 # CPI: Total CPI of All Threads
system.cpu.ipc 0.158018 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.158018 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 13474 # number of integer regfile reads
system.cpu.int_regfile_writes 7049 # number of integer regfile writes
system.cpu.fp_regfile_reads 25 # number of floating regfile reads
2011-02-08 04:23:13 +01:00
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
system.cpu.toL2Bus.throughput 1581971462 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 702 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 204 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count 906 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 22464 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 6528 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size 28992 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 28992 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 526500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 153000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 167.412828 # Cycle average of tags in use
system.cpu.icache.total_refs 1371 # Total number of references to valid blocks.
2012-11-02 17:50:06 +01:00
system.cpu.icache.sampled_refs 351 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 3.905983 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 167.412828 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.081745 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.081745 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1371 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1371 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1371 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1371 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1371 # number of overall hits
system.cpu.icache.overall_hits::total 1371 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 442 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 442 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 442 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 442 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 442 # number of overall misses
system.cpu.icache.overall_misses::total 442 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 28629500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 28629500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 28629500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 28629500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 28629500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 28629500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1813 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1813 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1813 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1813 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1813 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1813 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.243795 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.243795 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.243795 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.243795 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.243795 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.243795 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64772.624434 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 64772.624434 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 64772.624434 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 64772.624434 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 64772.624434 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 64772.624434 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 425 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 70.833333 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 91 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 91 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 91 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 91 # number of overall MSHR hits
2012-11-02 17:50:06 +01:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23362000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 23362000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23362000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 23362000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23362000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 23362000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193602 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.193602 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.193602 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66558.404558 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66558.404558 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66558.404558 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 66558.404558 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66558.404558 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 66558.404558 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 197.575721 # Cycle average of tags in use
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.total_refs 7 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.017544 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 166.296629 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 31.279092 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.005075 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.000955 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.006030 # Average percentage of cache occupancy
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 7 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 6 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
system.cpu.l2cache.overall_hits::total 7 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 345 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 54 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 399 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.demand_misses::cpu.inst 345 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 101 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 345 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses
system.cpu.l2cache.overall_misses::total 446 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22950500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4123000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 27073500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3627500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 3627500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 22950500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 7750500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 30701000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 22950500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 7750500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 30701000 # number of overall miss cycles
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses)
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses)
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.demand_accesses::cpu.inst 351 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 102 # number of demand (read+write) accesses
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.demand_accesses::total 453 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 351 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 102 # number of overall (read+write) accesses
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.overall_accesses::total 453 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.982906 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981818 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.982759 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982906 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.990196 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.984547 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66523.188406 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76351.851852 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 67853.383459 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77180.851064 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77180.851064 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66523.188406 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76737.623762 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 68836.322870 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66523.188406 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76737.623762 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 68836.322870 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 345 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 399 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 345 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18670000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3463750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22133750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3054750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3054750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18670000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6518500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 25188500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18670000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6518500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 25188500 # number of overall MSHR miss cycles
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54115.942029 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64143.518519 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55473.057644 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64994.680851 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64994.680851 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54115.942029 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64539.603960 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56476.457399 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54115.942029 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64539.603960 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56476.457399 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2012-11-02 17:50:06 +01:00
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 63.158434 # Cycle average of tags in use
system.cpu.dcache.total_refs 2188 # Total number of references to valid blocks.
2012-11-02 17:50:06 +01:00
system.cpu.dcache.sampled_refs 102 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 21.450980 # Average number of references to valid blocks.
2012-11-02 17:50:06 +01:00
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 63.158434 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.015420 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.015420 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1473 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1473 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 2188 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 2188 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 2188 # number of overall hits
system.cpu.dcache.overall_hits::total 2188 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 104 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 104 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 331 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 331 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 435 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 435 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 435 # number of overall misses
system.cpu.dcache.overall_misses::total 435 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7358500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 7358500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 19767997 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 19767997 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 27126497 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 27126497 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 27126497 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 27126497 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1577 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1577 # number of ReadReq accesses(hits+misses)
2012-11-02 17:50:06 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2623 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2623 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2623 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2623 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065948 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.065948 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316444 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.316444 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.165841 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.165841 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.165841 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.165841 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70754.807692 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 70754.807692 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59722.045317 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 59722.045317 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 62359.763218 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 62359.763218 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 62359.763218 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 62359.763218 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 500 # number of cycles access was blocked
2012-11-02 17:50:06 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 100 # average number of cycles each access was blocked
2012-11-02 17:50:06 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 333 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 333 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 333 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 333 # number of overall MSHR hits
2012-11-02 17:50:06 +01:00
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4188500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4188500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3676999 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3676999 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7865499 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7865499 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7865499 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7865499 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034876 # mshr miss rate for ReadReq accesses
2012-11-02 17:50:06 +01:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.038887 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.038887 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76154.545455 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76154.545455 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78234.021277 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78234.021277 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77112.735294 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 77112.735294 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77112.735294 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 77112.735294 # average overall mshr miss latency
2012-11-02 17:50:06 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------