2011-02-07 10:23:16 +01:00
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---------- Begin Simulation Statistics ----------
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2014-09-20 23:18:53 +02:00
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sim_seconds 5.192511 # Number of seconds simulated
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sim_ticks 5192511044000 # Number of ticks simulated
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final_tick 5192511044000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2011-11-05 21:32:23 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2014-09-20 23:18:53 +02:00
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host_inst_rate 1018343 # Simulator instruction rate (inst/s)
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host_op_rate 1963050 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 41210458750 # Simulator tick rate (ticks/s)
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host_mem_usage 646888 # Number of bytes of host memory used
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host_seconds 126.00 # Real time elapsed on the host
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sim_insts 128310974 # Number of instructions simulated
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sim_ops 247343919 # Number of ops (including micro ops) simulated
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2014-01-24 22:29:33 +01:00
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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2014-09-03 13:42:59 +02:00
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system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
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2014-09-20 23:18:53 +02:00
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system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory
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2012-06-29 17:19:03 +02:00
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system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
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2014-09-20 23:18:53 +02:00
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system.physmem.bytes_read::cpu.inst 827456 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9076288 # Number of bytes read from this memory
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system.physmem.bytes_read::total 9932544 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 827456 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 827456 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 5141952 # Number of bytes written to this memory
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2014-09-03 13:42:59 +02:00
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system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory
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2014-09-20 23:18:53 +02:00
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system.physmem.bytes_written::total 8132032 # Number of bytes written to this memory
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2014-09-03 13:42:59 +02:00
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system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
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2014-09-20 23:18:53 +02:00
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system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory
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2012-06-29 17:19:03 +02:00
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system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
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2014-09-20 23:18:53 +02:00
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system.physmem.num_reads::cpu.inst 12929 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 141817 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 155196 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 80343 # Number of write requests responded to by this memory
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2014-09-03 13:42:59 +02:00
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system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory
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2014-09-20 23:18:53 +02:00
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system.physmem.num_writes::total 127063 # Number of write requests responded to by this memory
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2014-09-03 13:42:59 +02:00
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system.physmem.bw_read::pc.south_bridge.ide 5460 # Total read bandwidth from this memory (bytes/s)
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2014-09-20 23:18:53 +02:00
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system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s)
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2012-06-29 17:19:03 +02:00
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system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
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2014-09-20 23:18:53 +02:00
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system.physmem.bw_read::cpu.inst 159356 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 1747957 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1912859 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 159356 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 159356 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 990263 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::pc.south_bridge.ide 575845 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 1566108 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 990263 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::pc.south_bridge.ide 581305 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s)
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2012-06-29 17:19:03 +02:00
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system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
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2014-09-20 23:18:53 +02:00
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system.physmem.bw_total::cpu.inst 159356 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 1747957 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 3478967 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 155196 # Number of read requests accepted
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system.physmem.writeReqs 127063 # Number of write requests accepted
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system.physmem.readBursts 155196 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 127063 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 9914944 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 17600 # Total number of bytes read from write queue
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system.physmem.bytesWritten 8130496 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 9932544 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 8132032 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 275 # Number of DRAM read bursts serviced by the write queue
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2013-11-01 16:56:34 +01:00
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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2014-09-20 23:18:53 +02:00
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system.physmem.neitherReadNorWriteReqs 1594 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 10479 # Per bank write bursts
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system.physmem.perBankRdBursts::1 9637 # Per bank write bursts
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system.physmem.perBankRdBursts::2 10137 # Per bank write bursts
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system.physmem.perBankRdBursts::3 9789 # Per bank write bursts
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system.physmem.perBankRdBursts::4 9555 # Per bank write bursts
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system.physmem.perBankRdBursts::5 9513 # Per bank write bursts
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system.physmem.perBankRdBursts::6 9351 # Per bank write bursts
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system.physmem.perBankRdBursts::7 9512 # Per bank write bursts
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system.physmem.perBankRdBursts::8 9073 # Per bank write bursts
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system.physmem.perBankRdBursts::9 8991 # Per bank write bursts
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system.physmem.perBankRdBursts::10 9630 # Per bank write bursts
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system.physmem.perBankRdBursts::11 9438 # Per bank write bursts
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system.physmem.perBankRdBursts::12 9550 # Per bank write bursts
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system.physmem.perBankRdBursts::13 10095 # Per bank write bursts
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system.physmem.perBankRdBursts::14 10146 # Per bank write bursts
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system.physmem.perBankRdBursts::15 10025 # Per bank write bursts
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system.physmem.perBankWrBursts::0 8301 # Per bank write bursts
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system.physmem.perBankWrBursts::1 8002 # Per bank write bursts
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system.physmem.perBankWrBursts::2 8301 # Per bank write bursts
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system.physmem.perBankWrBursts::3 8212 # Per bank write bursts
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system.physmem.perBankWrBursts::4 7990 # Per bank write bursts
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system.physmem.perBankWrBursts::5 7535 # Per bank write bursts
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system.physmem.perBankWrBursts::6 7392 # Per bank write bursts
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system.physmem.perBankWrBursts::7 7734 # Per bank write bursts
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system.physmem.perBankWrBursts::8 7444 # Per bank write bursts
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system.physmem.perBankWrBursts::9 7612 # Per bank write bursts
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system.physmem.perBankWrBursts::10 7970 # Per bank write bursts
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system.physmem.perBankWrBursts::11 7896 # Per bank write bursts
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system.physmem.perBankWrBursts::12 8102 # Per bank write bursts
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system.physmem.perBankWrBursts::13 8416 # Per bank write bursts
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system.physmem.perBankWrBursts::14 8297 # Per bank write bursts
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system.physmem.perBankWrBursts::15 7835 # Per bank write bursts
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2013-11-01 16:56:34 +01:00
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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2014-09-20 23:18:53 +02:00
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system.physmem.numWrRetry 1 # Number of times write queue was full causing retry
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system.physmem.totGap 5192510980500 # Total gap between requests
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2013-11-01 16:56:34 +01:00
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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2014-09-20 23:18:53 +02:00
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system.physmem.readPktSize::6 155196 # Read request sizes (log2)
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2013-11-01 16:56:34 +01:00
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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2014-09-20 23:18:53 +02:00
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system.physmem.writePktSize::6 127063 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 151525 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 2962 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 63 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see
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2014-09-03 13:42:59 +02:00
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system.physmem.rdQLenPdf::4 34 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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2012-10-25 19:14:42 +02:00
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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2014-03-23 16:12:19 +01:00
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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2014-09-20 23:18:53 +02:00
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system.physmem.wrQLenPdf::15 2384 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 3176 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 6154 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 6388 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 6392 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 7149 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 7445 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 8129 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 8789 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 9861 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 9041 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 8343 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 7645 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 7364 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 6417 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 6189 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 6244 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 6141 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 237 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 221 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 254 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 206 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 203 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 199 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 233 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 205 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 193 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 182 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 177 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 173 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 179 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 150 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 152 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 129 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 126 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 111 # What write queue length does an incoming req see
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|
|
system.physmem.wrQLenPdf::51 66 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::52 64 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::53 57 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::54 49 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::55 47 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::56 41 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::57 37 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::58 30 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::59 27 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::60 19 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::61 15 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.bytesPerActivate::samples 57292 # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::mean 314.972003 # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::gmean 184.928814 # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::stdev 333.427002 # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::0-127 21127 36.88% 36.88% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::128-255 13732 23.97% 60.84% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::256-383 5729 10.00% 70.84% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::384-511 3461 6.04% 76.89% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::512-639 2250 3.93% 80.81% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::640-767 1575 2.75% 83.56% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::768-895 1105 1.93% 85.49% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::896-1023 1008 1.76% 87.25% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::1024-1151 7305 12.75% 100.00% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::total 57292 # Bytes accessed per row activation
|
|
|
|
|
system.physmem.rdPerTurnAround::samples 5905 # Reads before turning the bus around for writes
|
|
|
|
|
system.physmem.rdPerTurnAround::mean 26.232854 # Reads before turning the bus around for writes
|
|
|
|
|
system.physmem.rdPerTurnAround::stdev 621.882480 # Reads before turning the bus around for writes
|
|
|
|
|
system.physmem.rdPerTurnAround::0-2047 5904 99.98% 99.98% # Reads before turning the bus around for writes
|
2014-09-03 13:42:59 +02:00
|
|
|
system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes
|
2014-09-20 23:18:53 +02:00
|
|
|
system.physmem.rdPerTurnAround::total 5905 # Reads before turning the bus around for writes
|
|
|
|
|
system.physmem.wrPerTurnAround::samples 5905 # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::mean 21.513802 # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::gmean 19.393687 # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::stdev 14.130484 # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::16-19 4886 82.74% 82.74% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::20-23 42 0.71% 83.45% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::24-27 41 0.69% 84.15% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::28-31 275 4.66% 88.81% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::32-35 267 4.52% 93.33% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::36-39 20 0.34% 93.67% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::40-43 10 0.17% 93.84% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::44-47 19 0.32% 94.16% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::48-51 22 0.37% 94.53% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::52-55 8 0.14% 94.67% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::56-59 6 0.10% 94.77% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::60-63 2 0.03% 94.80% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::64-67 226 3.83% 98.63% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::68-71 6 0.10% 98.73% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::72-75 4 0.07% 98.80% # Writes before turning the bus around for reads
|
2014-09-03 13:42:59 +02:00
|
|
|
system.physmem.wrPerTurnAround::76-79 3 0.05% 98.85% # Writes before turning the bus around for reads
|
2014-09-20 23:18:53 +02:00
|
|
|
system.physmem.wrPerTurnAround::80-83 15 0.25% 99.10% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::88-91 1 0.02% 99.12% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::92-95 1 0.02% 99.14% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::96-99 13 0.22% 99.36% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::100-103 1 0.02% 99.37% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::104-107 6 0.10% 99.48% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::108-111 3 0.05% 99.53% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::112-115 8 0.14% 99.66% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::116-119 2 0.03% 99.70% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::120-123 3 0.05% 99.75% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::128-131 12 0.20% 99.95% # Writes before turning the bus around for reads
|
2014-09-03 13:42:59 +02:00
|
|
|
system.physmem.wrPerTurnAround::132-135 1 0.02% 99.97% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads
|
2014-09-20 23:18:53 +02:00
|
|
|
system.physmem.wrPerTurnAround::total 5905 # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.totQLat 1558594500 # Total ticks spent queuing
|
|
|
|
|
system.physmem.totMemAccLat 4463363250 # Total ticks spent from burst creation until serviced by the DRAM
|
|
|
|
|
system.physmem.totBusLat 774605000 # Total ticks spent in databus transfers
|
|
|
|
|
system.physmem.avgQLat 10060.58 # Average queueing delay per DRAM burst
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
2014-09-20 23:18:53 +02:00
|
|
|
system.physmem.avgMemAccLat 28810.58 # Average memory access latency per DRAM burst
|
2014-09-03 13:42:59 +02:00
|
|
|
system.physmem.avgRdBW 1.91 # Average DRAM read bandwidth in MiByte/s
|
|
|
|
|
system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s
|
2014-09-20 23:18:53 +02:00
|
|
|
system.physmem.avgRdBWSys 1.91 # Average system read bandwidth in MiByte/s
|
2014-09-03 13:42:59 +02:00
|
|
|
system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.busUtil 0.03 # Data bus utilization in percentage
|
2014-09-03 13:42:59 +02:00
|
|
|
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
|
2014-09-03 13:42:59 +02:00
|
|
|
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
2014-09-20 23:18:53 +02:00
|
|
|
system.physmem.avgWrQLen 22.05 # Average write queue length when enqueuing
|
|
|
|
|
system.physmem.readRowHits 125976 # Number of row buffer hits during reads
|
|
|
|
|
system.physmem.writeRowHits 98691 # Number of row buffer hits during writes
|
|
|
|
|
system.physmem.readRowHitRate 81.32 # Row buffer hit rate for reads
|
|
|
|
|
system.physmem.writeRowHitRate 77.67 # Row buffer hit rate for writes
|
|
|
|
|
system.physmem.avgGap 18396263.65 # Average gap between requests
|
|
|
|
|
system.physmem.pageHitRate 79.67 # Row buffer hit rate, read and write combined
|
|
|
|
|
system.physmem.memoryStateTime::IDLE 4970934831000 # Time in different power states
|
|
|
|
|
system.physmem.memoryStateTime::REF 173389320000 # Time in different power states
|
2014-05-10 00:58:50 +02:00
|
|
|
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
2014-09-20 23:18:53 +02:00
|
|
|
system.physmem.memoryStateTime::ACT 48186778000 # Time in different power states
|
2014-05-10 00:58:50 +02:00
|
|
|
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
2014-09-20 23:18:53 +02:00
|
|
|
system.membus.trans_dist::ReadReq 623858 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadResp 623858 # Transaction distribution
|
2014-09-03 13:42:59 +02:00
|
|
|
system.membus.trans_dist::WriteReq 13773 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::WriteResp 13773 # Transaction distribution
|
2014-09-20 23:18:53 +02:00
|
|
|
system.membus.trans_dist::Writeback 80343 # Transaction distribution
|
2014-09-03 13:42:59 +02:00
|
|
|
system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::UpgradeReq 2146 # Transaction distribution
|
2014-09-20 23:18:53 +02:00
|
|
|
system.membus.trans_dist::UpgradeResp 1594 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadExReq 113180 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadExResp 113180 # Transaction distribution
|
2014-09-03 13:42:59 +02:00
|
|
|
system.membus.trans_dist::MessageReq 1654 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::MessageResp 1654 # Transaction distribution
|
|
|
|
|
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3308 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count_system.apicbridge.master::total 3308 # Packet count per connected master and slave (bytes)
|
2013-10-02 11:03:38 +02:00
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480328 # Packet count per connected master and slave (bytes)
|
2014-09-03 13:42:59 +02:00
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710110 # Packet count per connected master and slave (bytes)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393589 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1584027 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94722 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count_system.iocache.mem_side::total 94722 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count::total 1682057 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6616 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.apicbridge.master::total 6616 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246444 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420217 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15046144 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16712805 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size::total 19737853 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.snoops 948 # Total snoops (count)
|
|
|
|
|
system.membus.snoop_fanout::samples 284802 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::1 284802 100.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::total 284802 # Request fanout histogram
|
2014-09-03 13:42:59 +02:00
|
|
|
system.membus.reqLayer0.occupancy 256795500 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.membus.reqLayer1.occupancy 358101500 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
2014-09-03 13:42:59 +02:00
|
|
|
system.membus.reqLayer2.occupancy 3308000 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.membus.reqLayer3.occupancy 1310597750 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
2014-09-03 13:42:59 +02:00
|
|
|
system.membus.respLayer0.occupancy 1654000 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.membus.respLayer2.occupancy 2618526656 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.membus.respLayer4.occupancy 54286498 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.iocache.tags.replacements 47504 # number of replacements
|
|
|
|
|
system.iocache.tags.tagsinuse 0.112573 # Cycle average of tags in use
|
2013-06-27 11:49:51 +02:00
|
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
2014-09-20 23:18:53 +02:00
|
|
|
system.iocache.tags.sampled_refs 47520 # Sample count of references to valid blocks.
|
2013-06-27 11:49:51 +02:00
|
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
2014-09-20 23:18:53 +02:00
|
|
|
system.iocache.tags.warmup_cycle 5045778761000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.112573 # Average occupied blocks per requestor
|
|
|
|
|
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007036 # Average percentage of cache occupancy
|
|
|
|
|
system.iocache.tags.occ_percent::total 0.007036 # Average percentage of cache occupancy
|
2014-01-24 22:29:33 +01:00
|
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
|
|
|
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
|
|
|
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
2014-09-20 23:18:53 +02:00
|
|
|
system.iocache.tags.tag_accesses 428031 # Number of tag accesses
|
|
|
|
|
system.iocache.tags.data_accesses 428031 # Number of data accesses
|
2014-09-03 13:42:59 +02:00
|
|
|
system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits
|
|
|
|
|
system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits
|
2014-09-20 23:18:53 +02:00
|
|
|
system.iocache.ReadReq_misses::pc.south_bridge.ide 839 # number of ReadReq misses
|
|
|
|
|
system.iocache.ReadReq_misses::total 839 # number of ReadReq misses
|
|
|
|
|
system.iocache.demand_misses::pc.south_bridge.ide 839 # number of demand (read+write) misses
|
|
|
|
|
system.iocache.demand_misses::total 839 # number of demand (read+write) misses
|
|
|
|
|
system.iocache.overall_misses::pc.south_bridge.ide 839 # number of overall misses
|
|
|
|
|
system.iocache.overall_misses::total 839 # number of overall misses
|
|
|
|
|
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 140842436 # number of ReadReq miss cycles
|
|
|
|
|
system.iocache.ReadReq_miss_latency::total 140842436 # number of ReadReq miss cycles
|
|
|
|
|
system.iocache.demand_miss_latency::pc.south_bridge.ide 140842436 # number of demand (read+write) miss cycles
|
|
|
|
|
system.iocache.demand_miss_latency::total 140842436 # number of demand (read+write) miss cycles
|
|
|
|
|
system.iocache.overall_miss_latency::pc.south_bridge.ide 140842436 # number of overall miss cycles
|
|
|
|
|
system.iocache.overall_miss_latency::total 140842436 # number of overall miss cycles
|
|
|
|
|
system.iocache.ReadReq_accesses::pc.south_bridge.ide 839 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.iocache.ReadReq_accesses::total 839 # number of ReadReq accesses(hits+misses)
|
2014-09-03 13:42:59 +02:00
|
|
|
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
|
|
|
|
|
system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.iocache.demand_accesses::pc.south_bridge.ide 839 # number of demand (read+write) accesses
|
|
|
|
|
system.iocache.demand_accesses::total 839 # number of demand (read+write) accesses
|
|
|
|
|
system.iocache.overall_accesses::pc.south_bridge.ide 839 # number of overall (read+write) accesses
|
|
|
|
|
system.iocache.overall_accesses::total 839 # number of overall (read+write) accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167869.411204 # average ReadReq miss latency
|
|
|
|
|
system.iocache.ReadReq_avg_miss_latency::total 167869.411204 # average ReadReq miss latency
|
|
|
|
|
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167869.411204 # average overall miss latency
|
|
|
|
|
system.iocache.demand_avg_miss_latency::total 167869.411204 # average overall miss latency
|
|
|
|
|
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167869.411204 # average overall miss latency
|
|
|
|
|
system.iocache.overall_avg_miss_latency::total 167869.411204 # average overall miss latency
|
2014-09-03 13:42:59 +02:00
|
|
|
system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked
|
2011-11-05 21:32:23 +01:00
|
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2014-09-03 13:42:59 +02:00
|
|
|
system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked
|
2011-11-05 21:32:23 +01:00
|
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
2014-09-03 13:42:59 +02:00
|
|
|
system.iocache.avg_blocked_cycles::no_mshrs 12.076923 # average number of cycles each access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2014-09-03 13:42:59 +02:00
|
|
|
system.iocache.fast_writes 46720 # number of fast writes performed
|
2011-11-05 21:32:23 +01:00
|
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
2014-09-20 23:18:53 +02:00
|
|
|
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 839 # number of ReadReq MSHR misses
|
|
|
|
|
system.iocache.ReadReq_mshr_misses::total 839 # number of ReadReq MSHR misses
|
2014-09-03 13:42:59 +02:00
|
|
|
system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses
|
|
|
|
|
system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.iocache.demand_mshr_misses::pc.south_bridge.ide 839 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.iocache.demand_mshr_misses::total 839 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.iocache.overall_mshr_misses::pc.south_bridge.ide 839 # number of overall MSHR misses
|
|
|
|
|
system.iocache.overall_mshr_misses::total 839 # number of overall MSHR misses
|
|
|
|
|
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97188936 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.iocache.ReadReq_mshr_miss_latency::total 97188936 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2836981412 # number of WriteInvalidateReq MSHR miss cycles
|
|
|
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2836981412 # number of WriteInvalidateReq MSHR miss cycles
|
|
|
|
|
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97188936 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.iocache.demand_mshr_miss_latency::total 97188936 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97188936 # number of overall MSHR miss cycles
|
|
|
|
|
system.iocache.overall_mshr_miss_latency::total 97188936 # number of overall MSHR miss cycles
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
2014-09-03 13:42:59 +02:00
|
|
|
system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses
|
|
|
|
|
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115839.017878 # average ReadReq mshr miss latency
|
|
|
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 115839.017878 # average ReadReq mshr miss latency
|
|
|
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60723.061045 # average WriteInvalidateReq mshr miss latency
|
|
|
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60723.061045 # average WriteInvalidateReq mshr miss latency
|
|
|
|
|
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115839.017878 # average overall mshr miss latency
|
|
|
|
|
system.iocache.demand_avg_mshr_miss_latency::total 115839.017878 # average overall mshr miss latency
|
|
|
|
|
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115839.017878 # average overall mshr miss latency
|
|
|
|
|
system.iocache.overall_avg_mshr_miss_latency::total 115839.017878 # average overall mshr miss latency
|
2011-11-05 21:32:23 +01:00
|
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-02-07 10:23:16 +01:00
|
|
|
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
2011-11-05 21:32:23 +01:00
|
|
|
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
|
2011-02-07 10:23:16 +01:00
|
|
|
system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
|
|
|
|
|
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
|
2011-11-05 21:32:23 +01:00
|
|
|
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
|
2011-02-07 10:23:16 +01:00
|
|
|
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
|
|
|
|
|
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
2011-11-05 21:32:23 +01:00
|
|
|
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
2011-02-07 10:23:16 +01:00
|
|
|
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
|
|
|
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
|
2011-11-05 21:32:23 +01:00
|
|
|
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
|
2011-02-07 10:23:16 +01:00
|
|
|
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
|
2014-09-20 23:18:53 +02:00
|
|
|
system.iobus.trans_dist::ReadReq 230144 # Transaction distribution
|
|
|
|
|
system.iobus.trans_dist::ReadResp 230144 # Transaction distribution
|
2013-10-02 11:03:38 +02:00
|
|
|
system.iobus.trans_dist::WriteReq 57579 # Transaction distribution
|
|
|
|
|
system.iobus.trans_dist::WriteResp 57579 # Transaction distribution
|
2014-09-03 13:42:59 +02:00
|
|
|
system.iobus.trans_dist::MessageReq 1654 # Transaction distribution
|
|
|
|
|
system.iobus.trans_dist::MessageResp 1654 # Transaction distribution
|
2013-05-30 18:54:18 +02:00
|
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
|
2013-06-27 11:49:51 +02:00
|
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
|
2013-10-02 11:03:38 +02:00
|
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27236 # Packet count per connected master and slave (bytes)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
|
2013-10-02 11:03:38 +02:00
|
|
|
system.iobus.pkt_count_system.bridge.master::total 480328 # Packet count per connected master and slave (bytes)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95118 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95118 # Packet count per connected master and slave (bytes)
|
2014-09-03 13:42:59 +02:00
|
|
|
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3308 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3308 # Packet count per connected master and slave (bytes)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.iobus.pkt_count::total 578754 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::total 246444 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027256 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027256 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6616 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6616 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size::total 3280316 # Cumulative packet size per connected master and slave (bytes)
|
2014-09-03 13:42:59 +02:00
|
|
|
system.iobus.reqLayer0.occupancy 3944816 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
2013-06-27 11:49:51 +02:00
|
|
|
system.iobus.reqLayer3.occupancy 8813000 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer6.occupancy 77000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer9.occupancy 218343000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
|
2013-10-02 11:03:38 +02:00
|
|
|
system.iobus.reqLayer13.occupancy 20374000 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.iobus.reqLayer18.occupancy 421888846 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
|
2013-10-02 11:03:38 +02:00
|
|
|
system.iobus.respLayer0.occupancy 469469000 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.iobus.respLayer1.occupancy 52218502 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
|
2014-09-03 13:42:59 +02:00
|
|
|
system.iobus.respLayer2.occupancy 1654000 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
|
|
|
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.numCycles 10385022088 # number of cpu cycles simulated
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.committedInsts 128310974 # Number of instructions committed
|
|
|
|
|
system.cpu.committedOps 247343919 # Number of ops (including micro ops) committed
|
|
|
|
|
system.cpu.num_int_alu_accesses 231936467 # Number of integer alu accesses
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.num_func_calls 2299885 # number of times a function call or return occured
|
|
|
|
|
system.cpu.num_conditional_control_insts 23161985 # number of instructions that are conditional controls
|
|
|
|
|
system.cpu.num_int_insts 231936467 # number of integer instructions
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.num_fp_insts 0 # number of float instructions
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.num_int_register_reads 434450917 # number of times the integer registers were read
|
|
|
|
|
system.cpu.num_int_register_writes 197819265 # number of times the integer registers were written
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
|
|
|
|
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.num_cc_register_reads 132769519 # number of times the CC registers were read
|
|
|
|
|
system.cpu.num_cc_register_writes 95505601 # number of times the CC registers were written
|
|
|
|
|
system.cpu.num_mem_refs 22243286 # number of memory refs
|
|
|
|
|
system.cpu.num_load_insts 13879256 # Number of load instructions
|
|
|
|
|
system.cpu.num_store_insts 8364030 # Number of store instructions
|
|
|
|
|
system.cpu.num_idle_cycles 9788400874.998116 # Number of idle cycles
|
|
|
|
|
system.cpu.num_busy_cycles 596621213.001885 # Number of busy cycles
|
|
|
|
|
system.cpu.not_idle_fraction 0.057450 # Percentage of non-idle cycles
|
|
|
|
|
system.cpu.idle_fraction 0.942550 # Percentage of idle cycles
|
|
|
|
|
system.cpu.Branches 26299942 # Number of branches fetched
|
|
|
|
|
system.cpu.op_class::No_OpClass 174748 0.07% 0.07% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::IntAlu 224664535 90.83% 90.90% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::IntMult 139903 0.06% 90.96% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::IntDiv 122942 0.05% 91.01% # Class of executed instruction
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.op_class::FloatAdd 0 0.00% 91.01% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::FloatCmp 0 0.00% 91.01% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::FloatCvt 0 0.00% 91.01% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::FloatMult 0 0.00% 91.01% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::FloatDiv 0 0.00% 91.01% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::FloatSqrt 0 0.00% 91.01% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdAdd 0 0.00% 91.01% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdAddAcc 0 0.00% 91.01% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdAlu 0 0.00% 91.01% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdCmp 0 0.00% 91.01% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdCvt 0 0.00% 91.01% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdMisc 0 0.00% 91.01% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdMult 0 0.00% 91.01% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdMultAcc 0 0.00% 91.01% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdShift 0 0.00% 91.01% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdShiftAcc 0 0.00% 91.01% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdSqrt 0 0.00% 91.01% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdFloatAdd 0 0.00% 91.01% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdFloatAlu 0 0.00% 91.01% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdFloatCmp 0 0.00% 91.01% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdFloatCvt 0 0.00% 91.01% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdFloatDiv 0 0.00% 91.01% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdFloatMisc 0 0.00% 91.01% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdFloatMult 0 0.00% 91.01% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.01% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.01% # Class of executed instruction
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.op_class::MemRead 13879256 5.61% 96.62% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::MemWrite 8364030 3.38% 100.00% # Class of executed instruction
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.op_class::total 247345414 # Class of executed instruction
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
|
|
|
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.icache.tags.replacements 790109 # number of replacements
|
|
|
|
|
system.cpu.icache.tags.tagsinuse 510.353605 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.tags.total_refs 144545821 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.sampled_refs 790621 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.avg_refs 182.825679 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.warmup_cycle 161037022250 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 510.353605 # Average occupied blocks per requestor
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.996784 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.tags.occ_percent::total 0.996784 # Average percentage of cache occupancy
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 154 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 297 # Occupied blocks per task id
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.icache.tags.tag_accesses 146127077 # Number of tag accesses
|
|
|
|
|
system.cpu.icache.tags.data_accesses 146127077 # Number of data accesses
|
|
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 144545821 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 144545821 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits::cpu.inst 144545821 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_hits::total 144545821 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits::cpu.inst 144545821 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_hits::total 144545821 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 790628 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 790628 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 790628 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_misses::total 790628 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 790628 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_misses::total 790628 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 11108318120 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::total 11108318120 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 11108318120 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::total 11108318120 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 11108318120 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::total 11108318120 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 145336449 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 145336449 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses::cpu.inst 145336449 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_accesses::total 145336449 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 145336449 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::total 145336449 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005440 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.005440 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.005440 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::total 0.005440 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.005440 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::total 0.005440 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14049.993322 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 14049.993322 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14049.993322 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::total 14049.993322 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14049.993322 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::total 14049.993322 # average overall miss latency
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 790628 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::total 790628 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 790628 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::total 790628 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 790628 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::total 790628 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9522182380 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 9522182380 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9522182380 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::total 9522182380 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9522182380 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::total 9522182380 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005440 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005440 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005440 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.005440 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005440 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.005440 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12043.821342 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12043.821342 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12043.821342 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 12043.821342 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12043.821342 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 12043.821342 # average overall mshr miss latency
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.itb_walker_cache.tags.replacements 3485 # number of replacements
|
|
|
|
|
system.cpu.itb_walker_cache.tags.tagsinuse 3.066895 # Cycle average of tags in use
|
|
|
|
|
system.cpu.itb_walker_cache.tags.total_refs 7845 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.itb_walker_cache.tags.sampled_refs 3494 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.itb_walker_cache.tags.avg_refs 2.245278 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.itb_walker_cache.tags.warmup_cycle 5167508806000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.066895 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191681 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.itb_walker_cache.tags.occ_percent::total 0.191681 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 9 # Occupied blocks per task id
|
|
|
|
|
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
|
|
|
|
|
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
|
|
|
|
|
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
|
|
|
|
|
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.562500 # Percentage of cache occupancy per task id
|
|
|
|
|
system.cpu.itb_walker_cache.tags.tag_accesses 28811 # Number of tag accesses
|
|
|
|
|
system.cpu.itb_walker_cache.tags.data_accesses 28811 # Number of data accesses
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7868 # number of ReadReq hits
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_hits::total 7868 # number of ReadReq hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7870 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.itb_walker_cache.demand_hits::total 7870 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7870 # number of overall hits
|
|
|
|
|
system.cpu.itb_walker_cache.overall_hits::total 7870 # number of overall hits
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4357 # number of ReadReq misses
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_misses::total 4357 # number of ReadReq misses
|
|
|
|
|
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4357 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.itb_walker_cache.demand_misses::total 4357 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4357 # number of overall misses
|
|
|
|
|
system.cpu.itb_walker_cache.overall_misses::total 4357 # number of overall misses
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 43584500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_miss_latency::total 43584500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 43584500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.itb_walker_cache.demand_miss_latency::total 43584500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 43584500 # number of overall miss cycles
|
|
|
|
|
system.cpu.itb_walker_cache.overall_miss_latency::total 43584500 # number of overall miss cycles
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12225 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12227 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12227 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.356401 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.356401 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.356343 # miss rate for demand accesses
|
|
|
|
|
system.cpu.itb_walker_cache.demand_miss_rate::total 0.356343 # miss rate for demand accesses
|
|
|
|
|
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.356343 # miss rate for overall accesses
|
|
|
|
|
system.cpu.itb_walker_cache.overall_miss_rate::total 0.356343 # miss rate for overall accesses
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10003.327978 # average ReadReq miss latency
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10003.327978 # average ReadReq miss latency
|
|
|
|
|
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10003.327978 # average overall miss latency
|
|
|
|
|
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10003.327978 # average overall miss latency
|
|
|
|
|
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10003.327978 # average overall miss latency
|
|
|
|
|
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10003.327978 # average overall miss latency
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.itb_walker_cache.writebacks::writebacks 747 # number of writebacks
|
|
|
|
|
system.cpu.itb_walker_cache.writebacks::total 747 # number of writebacks
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4357 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4357 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4357 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.itb_walker_cache.demand_mshr_misses::total 4357 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4357 # number of overall MSHR misses
|
|
|
|
|
system.cpu.itb_walker_cache.overall_mshr_misses::total 4357 # number of overall MSHR misses
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 34868500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 34868500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 34868500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 34868500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 34868500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 34868500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.356401 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.356401 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.356343 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.356343 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.356343 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.356343 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8002.868947 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8002.868947 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8002.868947 # average overall mshr miss latency
|
|
|
|
|
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8002.868947 # average overall mshr miss latency
|
|
|
|
|
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8002.868947 # average overall mshr miss latency
|
|
|
|
|
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8002.868947 # average overall mshr miss latency
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dtb_walker_cache.tags.replacements 7826 # number of replacements
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.tagsinuse 5.051872 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.total_refs 12792 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.sampled_refs 7842 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.avg_refs 1.631217 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.warmup_cycle 5165211267000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.051872 # Average occupied blocks per requestor
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315742 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315742 # Average percentage of cache occupancy
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.tag_accesses 52641 # Number of tag accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.data_accesses 52641 # Number of data accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12792 # number of ReadReq hits
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_hits::total 12792 # number of ReadReq hits
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12792 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_hits::total 12792 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12792 # number of overall hits
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_hits::total 12792 # number of overall hits
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9019 # number of ReadReq misses
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_misses::total 9019 # number of ReadReq misses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9019 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_misses::total 9019 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9019 # number of overall misses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_misses::total 9019 # number of overall misses
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 95783000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 95783000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 95783000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_miss_latency::total 95783000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 95783000 # number of overall miss cycles
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_miss_latency::total 95783000 # number of overall miss cycles
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21811 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21811 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21811 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_accesses::total 21811 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21811 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_accesses::total 21811 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.413507 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.413507 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.413507 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.413507 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.413507 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.413507 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10620.135270 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10620.135270 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10620.135270 # average overall miss latency
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10620.135270 # average overall miss latency
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10620.135270 # average overall miss latency
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10620.135270 # average overall miss latency
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dtb_walker_cache.writebacks::writebacks 2842 # number of writebacks
|
|
|
|
|
system.cpu.dtb_walker_cache.writebacks::total 2842 # number of writebacks
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9019 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9019 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9019 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_mshr_misses::total 9019 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9019 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_mshr_misses::total 9019 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 77744500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 77744500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 77744500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 77744500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 77744500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 77744500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.413507 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.413507 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.413507 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.413507 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.413507 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.413507 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8620.079831 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8620.079831 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8620.079831 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8620.079831 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8620.079831 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8620.079831 # average overall mshr miss latency
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dcache.tags.replacements 1621218 # number of replacements
|
|
|
|
|
system.cpu.dcache.tags.tagsinuse 511.996934 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.tags.total_refs 20024389 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.tags.sampled_refs 1621730 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.tags.avg_refs 12.347548 # Average number of references to valid blocks.
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit.
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.996934 # Average occupied blocks per requestor
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dcache.tags.tag_accesses 88244906 # Number of tag accesses
|
|
|
|
|
system.cpu.dcache.tags.data_accesses 88244906 # Number of data accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 11933720 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 11933720 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 8029176 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 8029176 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 59323 # number of SoftPFReq hits
|
|
|
|
|
system.cpu.dcache.SoftPFReq_hits::total 59323 # number of SoftPFReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits::cpu.data 19962896 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::total 19962896 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::cpu.data 20022219 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::total 20022219 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 906567 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 906567 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 324536 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 324536 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 402460 # number of SoftPFReq misses
|
|
|
|
|
system.cpu.dcache.SoftPFReq_misses::total 402460 # number of SoftPFReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses::cpu.data 1231103 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_misses::total 1231103 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses::cpu.data 1633563 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::total 1633563 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12726532750 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::total 12726532750 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 11379509067 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::total 11379509067 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 24106041817 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::total 24106041817 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 24106041817 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::total 24106041817 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 12840287 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 12840287 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 8353712 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 8353712 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 461783 # number of SoftPFReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.SoftPFReq_accesses::total 461783 # number of SoftPFReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 21193999 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 21193999 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 21655782 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 21655782 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070603 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.070603 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038849 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.038849 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871535 # miss rate for SoftPFReq accesses
|
|
|
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.871535 # miss rate for SoftPFReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.058087 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::total 0.058087 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.075433 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::total 0.075433 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14038.160169 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 14038.160169 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35063.934562 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 35063.934562 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19580.848895 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::total 19580.848895 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14756.726136 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::total 14756.726136 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 8324 # number of cycles access was blocked
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 80 # number of cycles access was blocked
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 104.050000 # average number of cycles each access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dcache.writebacks::writebacks 1537872 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::total 1537872 # number of writebacks
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 287 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 287 # number of ReadReq MSHR hits
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9293 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 9293 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 9580 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::total 9580 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 9580 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::total 9580 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906280 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 906280 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315243 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 315243 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402425 # number of SoftPFReq MSHR misses
|
|
|
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 402425 # number of SoftPFReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1221523 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::total 1221523 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1623948 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::total 1623948 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10906302000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10906302000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10245705379 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 10245705379 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5368514000 # number of SoftPFReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5368514000 # number of SoftPFReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21152007379 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 21152007379 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26520521379 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 26520521379 # number of overall MSHR miss cycles
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94214672000 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94214672000 # number of ReadReq MSHR uncacheable cycles
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2536037000 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2536037000 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96750709000 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 96750709000 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070581 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070581 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037737 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037737 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871459 # mshr miss rate for SoftPFReq accesses
|
|
|
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871459 # mshr miss rate for SoftPFReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057635 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.057635 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074989 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.074989 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12034.141766 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12034.141766 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32500.976640 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32500.976640 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13340.408772 # average SoftPFReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13340.408772 # average SoftPFReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17316.094236 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 17316.094236 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16330.893218 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16330.893218 # average overall mshr miss latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 2694994 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 2694474 # Transaction distribution
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.toL2Bus.trans_dist::WriteReq 13773 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::WriteResp 13773 # Transaction distribution
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.toL2Bus.trans_dist::Writeback 1541461 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46721 # Transaction distribution
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 2183 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 2183 # Transaction distribution
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 313073 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 313073 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1581243 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5975195 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 7975 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18479 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count::total 7582892 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50599360 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203853221 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 231552 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 605440 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size::total 255289573 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.snoops 53135 # Total snoops (count)
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::samples 4016986 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::mean 3.011840 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.108164 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::3 3969426 98.82% 98.82% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::4 47560 1.18% 100.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::total 4016986 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 3830670000 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.toL2Bus.snoopLayer0.occupancy 478500 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1188381870 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.toL2Bus.respLayer1.occupancy 3052447844 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.toL2Bus.respLayer2.occupancy 6536500 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.toL2Bus.respLayer3.occupancy 13528750 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.tags.replacements 87289 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tags.tagsinuse 64708.241819 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.tags.total_refs 3488268 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.sampled_refs 151942 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.avg_refs 22.957892 # Average number of references to valid blocks.
|
2013-06-27 11:49:51 +02:00
|
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 50201.970335 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.012829 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141259 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3236.502324 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 11269.615072 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.766021 # Average percentage of cache occupancy
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
|
2013-06-27 11:49:51 +02:00
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049385 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.171961 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::total 0.987369 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 64653 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2860 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4737 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56942 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.986526 # Percentage of cache occupancy per task id
|
|
|
|
|
system.cpu.l2cache.tags.tag_accesses 32181921 # Number of tag accesses
|
|
|
|
|
system.cpu.l2cache.tags.data_accesses 32181921 # Number of data accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6616 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2866 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 777686 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 1279269 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::total 2066437 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::writebacks 1541461 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::total 1541461 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 312 # number of UpgradeReq hits
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_hits::total 312 # number of UpgradeReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 199613 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::total 199613 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6616 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.itb.walker 2866 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 777686 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.data 1478882 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::total 2266050 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.dtb.walker 6616 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.itb.walker 2866 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 777686 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.data 1478882 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::total 2266050 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 12929 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 28637 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::total 41573 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1319 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses::total 1319 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 113455 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 113455 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 12929 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 142092 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::total 155028 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 12929 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 142092 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::total 155028 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 164250 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 365000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 954586500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2172547250 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 3127663000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 15242851 # number of UpgradeReq miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 15242851 # number of UpgradeReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7899568975 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 7899568975 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 164250 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 365000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 954586500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 10072116225 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::total 11027231975 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 164250 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 365000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 954586500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 10072116225 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::total 11027231975 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6618 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2871 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 790615 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1307906 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 2108010 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 1541461 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::total 1541461 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1631 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 1631 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 313068 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 313068 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6618 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.itb.walker 2871 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 790615 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1620974 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::total 2421078 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6618 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.itb.walker 2871 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 790615 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1620974 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::total 2421078 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000302 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001742 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016353 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021895 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.019721 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.808706 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.808706 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.362397 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.362397 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000302 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001742 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016353 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.087658 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::total 0.064033 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000302 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001742 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016353 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.087658 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::total 0.064033 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 82125 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 73000 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73832.972388 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75865.043475 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 75233.035865 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11556.369219 # average UpgradeReq miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11556.369219 # average UpgradeReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69627.332202 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69627.332202 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 82125 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 73000 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73832.972388 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70884.470801 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 71130.582701 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 82125 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 73000 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73832.972388 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70884.470801 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 71130.582701 # average overall miss latency
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.writebacks::writebacks 80343 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.writebacks::total 80343 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 2 # number of ReadReq MSHR misses
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12929 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28637 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 41573 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1319 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 1319 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113455 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 113455 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 2 # number of demand (read+write) MSHR misses
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 12929 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 142092 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::total 155028 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 2 # number of overall MSHR misses
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 12929 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 142092 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::total 155028 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 138750 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 301500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 792612500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1813424750 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2606477500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 13194319 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 13194319 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6481465525 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6481465525 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 138750 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 301500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 792612500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8294890275 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 9087943025 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 138750 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 301500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 792612500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8294890275 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 9087943025 # number of overall MSHR miss cycles
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86655868500 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86655868500 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2370634000 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2370634000 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89026502500 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89026502500 # number of overall MSHR uncacheable cycles
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000302 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001742 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016353 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021895 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019721 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.808706 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.808706 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362397 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362397 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000302 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001742 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016353 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087658 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.064033 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000302 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001742 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016353 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087658 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.064033 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 69375 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 60300 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61305.011989 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63324.536439 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62696.401511 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10003.274450 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10003.274450 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57128.073025 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57128.073025 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 69375 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 60300 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61305.011989 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58376.898594 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58621.300830 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69375 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 60300 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61305.011989 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58376.898594 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58621.300830 # average overall mshr miss latency
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-02-07 10:23:16 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
