2007-03-30 00:41:20 +02:00
|
|
|
[root]
|
|
|
|
type=Root
|
|
|
|
children=system
|
2014-01-24 22:29:33 +01:00
|
|
|
eventq_index=0
|
2012-02-12 23:07:43 +01:00
|
|
|
full_system=false
|
2014-01-24 22:29:33 +01:00
|
|
|
sim_quantum=0
|
2011-02-08 04:23:13 +01:00
|
|
|
time_sync_enable=false
|
|
|
|
time_sync_period=100000000000
|
|
|
|
time_sync_spin_threshold=100000000
|
2007-03-30 00:41:20 +02:00
|
|
|
|
|
|
|
[system]
|
|
|
|
type=System
|
2014-09-01 23:55:52 +02:00
|
|
|
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
|
2012-02-12 23:07:43 +01:00
|
|
|
boot_osflags=a
|
2013-09-28 21:25:17 +02:00
|
|
|
cache_line_size=64
|
|
|
|
clk_domain=system.clk_domain
|
2014-01-24 22:29:33 +01:00
|
|
|
eventq_index=0
|
2016-01-22 16:42:13 +01:00
|
|
|
exit_on_work_items=false
|
2012-02-12 23:07:43 +01:00
|
|
|
init_param=0
|
|
|
|
kernel=
|
2014-09-01 23:55:52 +02:00
|
|
|
kernel_addr_check=true
|
2012-02-12 23:07:43 +01:00
|
|
|
load_addr_mask=1099511627775
|
2014-09-01 23:55:52 +02:00
|
|
|
load_offset=0
|
2013-01-24 19:29:00 +01:00
|
|
|
mem_mode=timing
|
|
|
|
mem_ranges=
|
2011-12-01 00:57:11 +01:00
|
|
|
memories=system.physmem
|
2015-08-30 19:24:19 +02:00
|
|
|
mmap_using_noreserve=false
|
2015-11-16 12:08:57 +01:00
|
|
|
multi_thread=false
|
2012-01-25 18:19:50 +01:00
|
|
|
num_work_ids=16
|
2012-02-12 23:07:43 +01:00
|
|
|
readfile=
|
|
|
|
symbolfile=
|
2011-02-08 04:23:13 +01:00
|
|
|
work_begin_ckpt_count=0
|
|
|
|
work_begin_cpu_id_exit=-1
|
|
|
|
work_begin_exit_count=0
|
|
|
|
work_cpus_ckpt_count=0
|
|
|
|
work_end_ckpt_count=0
|
|
|
|
work_end_exit_count=0
|
|
|
|
work_item_id=-1
|
2012-05-09 20:52:14 +02:00
|
|
|
system_port=system.membus.slave[0]
|
2007-03-30 00:41:20 +02:00
|
|
|
|
2013-09-28 21:25:17 +02:00
|
|
|
[system.clk_domain]
|
|
|
|
type=SrcClockDomain
|
|
|
|
clock=1000
|
2014-09-01 23:55:52 +02:00
|
|
|
domain_id=-1
|
2014-01-24 22:29:33 +01:00
|
|
|
eventq_index=0
|
2014-09-01 23:55:52 +02:00
|
|
|
init_perf_level=0
|
2013-09-28 21:25:17 +02:00
|
|
|
voltage_domain=system.voltage_domain
|
|
|
|
|
2007-03-30 00:41:20 +02:00
|
|
|
[system.cpu]
|
|
|
|
type=TimingSimpleCPU
|
2013-01-24 19:29:00 +01:00
|
|
|
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
|
2014-09-01 23:55:52 +02:00
|
|
|
branchPred=Null
|
2009-02-16 18:09:45 +01:00
|
|
|
checker=Null
|
2013-09-28 21:25:17 +02:00
|
|
|
clk_domain=system.cpu_clk_domain
|
2007-03-30 00:41:20 +02:00
|
|
|
cpu_id=0
|
2009-02-16 18:09:45 +01:00
|
|
|
do_checkpoint_insts=true
|
2012-02-12 23:07:43 +01:00
|
|
|
do_quiesce=true
|
2009-02-16 18:09:45 +01:00
|
|
|
do_statistics_insts=true
|
2007-08-27 05:27:53 +02:00
|
|
|
dtb=system.cpu.dtb
|
2014-01-24 22:29:33 +01:00
|
|
|
eventq_index=0
|
2007-03-30 00:41:20 +02:00
|
|
|
function_trace=false
|
|
|
|
function_trace_start=0
|
2012-02-12 23:07:43 +01:00
|
|
|
interrupts=system.cpu.interrupts
|
2013-01-24 19:29:00 +01:00
|
|
|
isa=system.cpu.isa
|
2007-08-27 05:27:53 +02:00
|
|
|
itb=system.cpu.itb
|
2007-03-30 00:41:20 +02:00
|
|
|
max_insts_all_threads=0
|
|
|
|
max_insts_any_thread=0
|
|
|
|
max_loads_all_threads=0
|
|
|
|
max_loads_any_thread=0
|
2008-09-28 23:16:26 +02:00
|
|
|
numThreads=1
|
2012-02-12 23:07:43 +01:00
|
|
|
profile=0
|
2007-03-30 00:41:20 +02:00
|
|
|
progress_interval=0
|
2013-09-28 21:25:17 +02:00
|
|
|
simpoint_start_insts=
|
2014-09-01 23:55:52 +02:00
|
|
|
socket_id=0
|
2013-01-24 19:29:00 +01:00
|
|
|
switched_out=false
|
2007-03-30 00:41:20 +02:00
|
|
|
system=system
|
2007-08-13 01:43:55 +02:00
|
|
|
tracer=system.cpu.tracer
|
2007-03-30 00:41:20 +02:00
|
|
|
workload=system.cpu.workload
|
|
|
|
dcache_port=system.cpu.dcache.cpu_side
|
|
|
|
icache_port=system.cpu.icache.cpu_side
|
|
|
|
|
|
|
|
[system.cpu.dcache]
|
2015-08-30 19:24:19 +02:00
|
|
|
type=Cache
|
2013-09-28 21:25:17 +02:00
|
|
|
children=tags
|
2012-05-09 20:52:14 +02:00
|
|
|
addr_ranges=0:18446744073709551615
|
2007-03-30 00:41:20 +02:00
|
|
|
assoc=2
|
2013-09-28 21:25:17 +02:00
|
|
|
clk_domain=system.cpu_clk_domain
|
2015-11-16 12:08:57 +01:00
|
|
|
clusivity=mostly_incl
|
2015-08-30 19:24:19 +02:00
|
|
|
demand_mshr_reserve=1
|
2014-01-24 22:29:33 +01:00
|
|
|
eventq_index=0
|
2009-04-22 07:55:52 +02:00
|
|
|
forward_snoops=true
|
2013-01-24 19:29:00 +01:00
|
|
|
hit_latency=2
|
2015-08-30 19:24:19 +02:00
|
|
|
is_read_only=false
|
2007-03-30 00:41:20 +02:00
|
|
|
max_miss_count=0
|
2013-01-24 19:29:00 +01:00
|
|
|
mshrs=4
|
2009-02-16 18:09:45 +01:00
|
|
|
prefetch_on_access=false
|
2012-02-12 23:07:43 +01:00
|
|
|
prefetcher=Null
|
2013-01-24 19:29:00 +01:00
|
|
|
response_latency=2
|
2014-01-24 22:29:33 +01:00
|
|
|
sequential_access=false
|
2007-03-30 00:41:20 +02:00
|
|
|
size=262144
|
2012-02-12 23:07:43 +01:00
|
|
|
system=system
|
2013-09-28 21:25:17 +02:00
|
|
|
tags=system.cpu.dcache.tags
|
2013-01-24 19:29:00 +01:00
|
|
|
tgts_per_mshr=20
|
2007-03-30 00:41:20 +02:00
|
|
|
write_buffers=8
|
2015-11-16 12:08:57 +01:00
|
|
|
writeback_clean=false
|
2007-03-30 00:41:20 +02:00
|
|
|
cpu_side=system.cpu.dcache_port
|
2012-05-09 20:52:14 +02:00
|
|
|
mem_side=system.cpu.toL2Bus.slave[1]
|
2007-03-30 00:41:20 +02:00
|
|
|
|
2013-09-28 21:25:17 +02:00
|
|
|
[system.cpu.dcache.tags]
|
|
|
|
type=LRU
|
|
|
|
assoc=2
|
|
|
|
block_size=64
|
|
|
|
clk_domain=system.cpu_clk_domain
|
2014-01-24 22:29:33 +01:00
|
|
|
eventq_index=0
|
2013-09-28 21:25:17 +02:00
|
|
|
hit_latency=2
|
2014-01-24 22:29:33 +01:00
|
|
|
sequential_access=false
|
2013-09-28 21:25:17 +02:00
|
|
|
size=262144
|
|
|
|
|
2007-08-27 05:27:53 +02:00
|
|
|
[system.cpu.dtb]
|
2009-04-09 07:21:30 +02:00
|
|
|
type=SparcTLB
|
2014-01-24 22:29:33 +01:00
|
|
|
eventq_index=0
|
2007-08-27 05:27:53 +02:00
|
|
|
size=64
|
|
|
|
|
2007-03-30 00:41:20 +02:00
|
|
|
[system.cpu.icache]
|
2015-08-30 19:24:19 +02:00
|
|
|
type=Cache
|
2013-09-28 21:25:17 +02:00
|
|
|
children=tags
|
2012-05-09 20:52:14 +02:00
|
|
|
addr_ranges=0:18446744073709551615
|
2007-03-30 00:41:20 +02:00
|
|
|
assoc=2
|
2013-09-28 21:25:17 +02:00
|
|
|
clk_domain=system.cpu_clk_domain
|
2015-11-16 12:08:57 +01:00
|
|
|
clusivity=mostly_incl
|
2015-08-30 19:24:19 +02:00
|
|
|
demand_mshr_reserve=1
|
2014-01-24 22:29:33 +01:00
|
|
|
eventq_index=0
|
2009-04-22 07:55:52 +02:00
|
|
|
forward_snoops=true
|
2013-01-24 19:29:00 +01:00
|
|
|
hit_latency=2
|
2015-08-30 19:24:19 +02:00
|
|
|
is_read_only=true
|
2007-03-30 00:41:20 +02:00
|
|
|
max_miss_count=0
|
2013-01-24 19:29:00 +01:00
|
|
|
mshrs=4
|
2009-02-16 18:09:45 +01:00
|
|
|
prefetch_on_access=false
|
2012-02-12 23:07:43 +01:00
|
|
|
prefetcher=Null
|
2013-01-24 19:29:00 +01:00
|
|
|
response_latency=2
|
2014-01-24 22:29:33 +01:00
|
|
|
sequential_access=false
|
2007-03-30 00:41:20 +02:00
|
|
|
size=131072
|
2012-02-12 23:07:43 +01:00
|
|
|
system=system
|
2013-09-28 21:25:17 +02:00
|
|
|
tags=system.cpu.icache.tags
|
2013-01-24 19:29:00 +01:00
|
|
|
tgts_per_mshr=20
|
2007-03-30 00:41:20 +02:00
|
|
|
write_buffers=8
|
2015-11-16 12:08:57 +01:00
|
|
|
writeback_clean=true
|
2007-03-30 00:41:20 +02:00
|
|
|
cpu_side=system.cpu.icache_port
|
2012-05-09 20:52:14 +02:00
|
|
|
mem_side=system.cpu.toL2Bus.slave[0]
|
2007-03-30 00:41:20 +02:00
|
|
|
|
2013-09-28 21:25:17 +02:00
|
|
|
[system.cpu.icache.tags]
|
|
|
|
type=LRU
|
|
|
|
assoc=2
|
|
|
|
block_size=64
|
|
|
|
clk_domain=system.cpu_clk_domain
|
2014-01-24 22:29:33 +01:00
|
|
|
eventq_index=0
|
2013-09-28 21:25:17 +02:00
|
|
|
hit_latency=2
|
2014-01-24 22:29:33 +01:00
|
|
|
sequential_access=false
|
2013-09-28 21:25:17 +02:00
|
|
|
size=131072
|
|
|
|
|
2012-02-12 23:07:43 +01:00
|
|
|
[system.cpu.interrupts]
|
|
|
|
type=SparcInterrupts
|
2014-01-24 22:29:33 +01:00
|
|
|
eventq_index=0
|
2012-02-12 23:07:43 +01:00
|
|
|
|
2013-01-24 19:29:00 +01:00
|
|
|
[system.cpu.isa]
|
|
|
|
type=SparcISA
|
2014-01-24 22:29:33 +01:00
|
|
|
eventq_index=0
|
2013-01-24 19:29:00 +01:00
|
|
|
|
2007-08-27 05:27:53 +02:00
|
|
|
[system.cpu.itb]
|
2009-04-09 07:21:30 +02:00
|
|
|
type=SparcTLB
|
2014-01-24 22:29:33 +01:00
|
|
|
eventq_index=0
|
2007-08-27 05:27:53 +02:00
|
|
|
size=64
|
|
|
|
|
2007-03-30 00:41:20 +02:00
|
|
|
[system.cpu.l2cache]
|
2015-08-30 19:24:19 +02:00
|
|
|
type=Cache
|
2013-09-28 21:25:17 +02:00
|
|
|
children=tags
|
2012-05-09 20:52:14 +02:00
|
|
|
addr_ranges=0:18446744073709551615
|
2013-01-24 19:29:00 +01:00
|
|
|
assoc=8
|
2013-09-28 21:25:17 +02:00
|
|
|
clk_domain=system.cpu_clk_domain
|
2015-11-16 12:08:57 +01:00
|
|
|
clusivity=mostly_incl
|
2015-08-30 19:24:19 +02:00
|
|
|
demand_mshr_reserve=1
|
2014-01-24 22:29:33 +01:00
|
|
|
eventq_index=0
|
2009-04-22 07:55:52 +02:00
|
|
|
forward_snoops=true
|
2013-01-24 19:29:00 +01:00
|
|
|
hit_latency=20
|
2015-08-30 19:24:19 +02:00
|
|
|
is_read_only=false
|
2007-03-30 00:41:20 +02:00
|
|
|
max_miss_count=0
|
2013-01-24 19:29:00 +01:00
|
|
|
mshrs=20
|
2009-02-16 18:09:45 +01:00
|
|
|
prefetch_on_access=false
|
2012-02-12 23:07:43 +01:00
|
|
|
prefetcher=Null
|
2013-01-24 19:29:00 +01:00
|
|
|
response_latency=20
|
2014-01-24 22:29:33 +01:00
|
|
|
sequential_access=false
|
2007-03-30 00:41:20 +02:00
|
|
|
size=2097152
|
2012-02-12 23:07:43 +01:00
|
|
|
system=system
|
2013-09-28 21:25:17 +02:00
|
|
|
tags=system.cpu.l2cache.tags
|
2013-01-24 19:29:00 +01:00
|
|
|
tgts_per_mshr=12
|
2007-03-30 00:41:20 +02:00
|
|
|
write_buffers=8
|
2015-11-16 12:08:57 +01:00
|
|
|
writeback_clean=false
|
2012-05-09 20:52:14 +02:00
|
|
|
cpu_side=system.cpu.toL2Bus.master[0]
|
|
|
|
mem_side=system.membus.slave[1]
|
2007-03-30 00:41:20 +02:00
|
|
|
|
2013-09-28 21:25:17 +02:00
|
|
|
[system.cpu.l2cache.tags]
|
|
|
|
type=LRU
|
|
|
|
assoc=8
|
|
|
|
block_size=64
|
|
|
|
clk_domain=system.cpu_clk_domain
|
2014-01-24 22:29:33 +01:00
|
|
|
eventq_index=0
|
2013-09-28 21:25:17 +02:00
|
|
|
hit_latency=20
|
2014-01-24 22:29:33 +01:00
|
|
|
sequential_access=false
|
2013-09-28 21:25:17 +02:00
|
|
|
size=2097152
|
|
|
|
|
2007-03-30 00:41:20 +02:00
|
|
|
[system.cpu.toL2Bus]
|
2014-10-11 23:18:51 +02:00
|
|
|
type=CoherentXBar
|
2015-11-16 12:08:57 +01:00
|
|
|
children=snoop_filter
|
2013-09-28 21:25:17 +02:00
|
|
|
clk_domain=system.cpu_clk_domain
|
2014-01-24 22:29:33 +01:00
|
|
|
eventq_index=0
|
2015-08-30 19:24:19 +02:00
|
|
|
forward_latency=0
|
|
|
|
frontend_latency=1
|
|
|
|
response_latency=1
|
2015-11-16 12:08:57 +01:00
|
|
|
snoop_filter=system.cpu.toL2Bus.snoop_filter
|
2015-08-30 19:24:19 +02:00
|
|
|
snoop_response_latency=1
|
2013-09-28 21:25:17 +02:00
|
|
|
system=system
|
2010-08-17 14:06:22 +02:00
|
|
|
use_default_range=false
|
2013-01-24 19:29:00 +01:00
|
|
|
width=32
|
2012-05-09 20:52:14 +02:00
|
|
|
master=system.cpu.l2cache.cpu_side
|
|
|
|
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
2007-03-30 00:41:20 +02:00
|
|
|
|
2015-11-16 12:08:57 +01:00
|
|
|
[system.cpu.toL2Bus.snoop_filter]
|
|
|
|
type=SnoopFilter
|
|
|
|
eventq_index=0
|
|
|
|
lookup_latency=0
|
|
|
|
max_capacity=8388608
|
|
|
|
system=system
|
|
|
|
|
2007-08-13 01:43:55 +02:00
|
|
|
[system.cpu.tracer]
|
|
|
|
type=ExeTracer
|
2014-01-24 22:29:33 +01:00
|
|
|
eventq_index=0
|
2007-08-13 01:43:55 +02:00
|
|
|
|
2007-03-30 00:41:20 +02:00
|
|
|
[system.cpu.workload]
|
|
|
|
type=LiveProcess
|
|
|
|
cmd=twolf smred
|
2015-08-30 19:24:19 +02:00
|
|
|
cwd=build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing
|
|
|
|
drivers=
|
2007-03-30 00:41:20 +02:00
|
|
|
egid=100
|
|
|
|
env=
|
2008-07-25 01:31:54 +02:00
|
|
|
errout=cerr
|
2007-03-30 00:41:20 +02:00
|
|
|
euid=100
|
2014-01-24 22:29:33 +01:00
|
|
|
eventq_index=0
|
2015-12-12 23:27:38 +01:00
|
|
|
executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf
|
2007-03-30 00:41:20 +02:00
|
|
|
gid=100
|
|
|
|
input=cin
|
2015-08-30 19:24:19 +02:00
|
|
|
kvmInSE=false
|
2007-11-29 09:00:02 +01:00
|
|
|
max_stack_size=67108864
|
2007-03-30 00:41:20 +02:00
|
|
|
output=cout
|
|
|
|
pid=100
|
|
|
|
ppid=99
|
2008-07-22 23:00:18 +02:00
|
|
|
simpoint=0
|
2007-03-30 00:41:20 +02:00
|
|
|
system=system
|
|
|
|
uid=100
|
2014-10-11 23:18:51 +02:00
|
|
|
useArchPT=false
|
2007-03-30 00:41:20 +02:00
|
|
|
|
2013-09-28 21:25:17 +02:00
|
|
|
[system.cpu_clk_domain]
|
|
|
|
type=SrcClockDomain
|
|
|
|
clock=500
|
2014-09-01 23:55:52 +02:00
|
|
|
domain_id=-1
|
2014-01-24 22:29:33 +01:00
|
|
|
eventq_index=0
|
2014-09-01 23:55:52 +02:00
|
|
|
init_perf_level=0
|
2013-09-28 21:25:17 +02:00
|
|
|
voltage_domain=system.voltage_domain
|
|
|
|
|
2014-09-01 23:55:52 +02:00
|
|
|
[system.dvfs_handler]
|
|
|
|
type=DVFSHandler
|
|
|
|
domains=
|
|
|
|
enable=false
|
|
|
|
eventq_index=0
|
|
|
|
sys_clk_domain=system.clk_domain
|
|
|
|
transition_latency=100000000
|
|
|
|
|
2007-03-30 00:41:20 +02:00
|
|
|
[system.membus]
|
2014-10-11 23:18:51 +02:00
|
|
|
type=CoherentXBar
|
2013-09-28 21:25:17 +02:00
|
|
|
clk_domain=system.clk_domain
|
2014-01-24 22:29:33 +01:00
|
|
|
eventq_index=0
|
2015-08-30 19:24:19 +02:00
|
|
|
forward_latency=4
|
|
|
|
frontend_latency=3
|
|
|
|
response_latency=2
|
2014-10-11 23:18:51 +02:00
|
|
|
snoop_filter=Null
|
2015-08-30 19:24:19 +02:00
|
|
|
snoop_response_latency=4
|
2013-09-28 21:25:17 +02:00
|
|
|
system=system
|
2010-08-17 14:06:22 +02:00
|
|
|
use_default_range=false
|
2015-08-30 19:24:19 +02:00
|
|
|
width=16
|
2012-08-15 16:38:05 +02:00
|
|
|
master=system.physmem.port
|
2012-05-09 20:52:14 +02:00
|
|
|
slave=system.system_port system.cpu.l2cache.mem_side
|
2007-03-30 00:41:20 +02:00
|
|
|
|
|
|
|
[system.physmem]
|
2012-05-09 20:52:14 +02:00
|
|
|
type=SimpleMemory
|
2013-01-24 19:29:00 +01:00
|
|
|
bandwidth=73.000000
|
2013-09-28 21:25:17 +02:00
|
|
|
clk_domain=system.clk_domain
|
|
|
|
conf_table_reported=true
|
2014-01-24 22:29:33 +01:00
|
|
|
eventq_index=0
|
2012-05-09 20:52:14 +02:00
|
|
|
in_addr_map=true
|
2008-08-04 00:13:29 +02:00
|
|
|
latency=30000
|
2008-07-22 23:00:18 +02:00
|
|
|
latency_var=0
|
|
|
|
null=false
|
2007-03-30 00:41:20 +02:00
|
|
|
range=0:134217727
|
2012-05-09 20:52:14 +02:00
|
|
|
port=system.membus.master[0]
|
2007-03-30 00:41:20 +02:00
|
|
|
|
2013-09-28 21:25:17 +02:00
|
|
|
[system.voltage_domain]
|
|
|
|
type=VoltageDomain
|
2014-01-24 22:29:33 +01:00
|
|
|
eventq_index=0
|
2013-09-28 21:25:17 +02:00
|
|
|
voltage=1.000000
|
|
|
|
|