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gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt

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Update ref stats. tests/test1/ref/alpha/atomic/stdout: tests/test1/ref/alpha/detailed/stderr: tests/test1/ref/alpha/detailed/stdout: tests/test1/ref/alpha/timing/stdout: Updated output. --HG-- extra : convert_revision : 3189564725ac4d2b3d63e6a71151a52326f8d416
2006-07-27 23:47:43 +02:00
---------- Begin Simulation Statistics ----------
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
sim_seconds 1.962845 # Number of seconds simulated
sim_ticks 1962844580000 # Number of ticks simulated
final_tick 1962844580000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
host_inst_rate 1184099 # Simulator instruction rate (inst/s)
host_op_rate 1184098 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 38148129943 # Simulator tick rate (ticks/s)
host_mem_usage 318172 # Number of bytes of host memory used
host_seconds 51.45 # Real time elapsed on the host
sim_insts 60925667 # Number of instructions simulated
sim_ops 60925667 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.bytes_read::cpu0.inst 823168 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 24882816 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 41728 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 386368 # Number of bytes read from this memory
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.bytes_read::total 26135040 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 823168 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 41728 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 864896 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7758336 # Number of bytes written to this memory
system.physmem.bytes_written::total 7758336 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst 12862 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 388794 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 652 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 6037 # Number of read requests responded to by this memory
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.num_reads::total 408360 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 121224 # Number of write requests responded to by this memory
system.physmem.num_writes::total 121224 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst 419375 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 12676916 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 21259 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 196841 # Total read bandwidth from this memory (bytes/s)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.bw_read::total 13314880 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 419375 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 21259 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 440634 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3952598 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3952598 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3952598 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 419375 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 12676916 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 21259 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 196841 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 17267478 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 408360 # Number of read requests accepted
system.physmem.writeReqs 162776 # Number of write requests accepted
system.physmem.readBursts 408360 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 162776 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 26127936 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue
system.physmem.bytesWritten 10271680 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 26135040 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 10417664 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2254 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 7048 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 25705 # Per bank write bursts
system.physmem.perBankRdBursts::1 25985 # Per bank write bursts
system.physmem.perBankRdBursts::2 25732 # Per bank write bursts
system.physmem.perBankRdBursts::3 25537 # Per bank write bursts
system.physmem.perBankRdBursts::4 24847 # Per bank write bursts
system.physmem.perBankRdBursts::5 24747 # Per bank write bursts
system.physmem.perBankRdBursts::6 25534 # Per bank write bursts
system.physmem.perBankRdBursts::7 25495 # Per bank write bursts
system.physmem.perBankRdBursts::8 25150 # Per bank write bursts
system.physmem.perBankRdBursts::9 25518 # Per bank write bursts
system.physmem.perBankRdBursts::10 25462 # Per bank write bursts
system.physmem.perBankRdBursts::11 25292 # Per bank write bursts
system.physmem.perBankRdBursts::12 25577 # Per bank write bursts
system.physmem.perBankRdBursts::13 25454 # Per bank write bursts
system.physmem.perBankRdBursts::14 26241 # Per bank write bursts
system.physmem.perBankRdBursts::15 25973 # Per bank write bursts
system.physmem.perBankWrBursts::0 10613 # Per bank write bursts
system.physmem.perBankWrBursts::1 10753 # Per bank write bursts
system.physmem.perBankWrBursts::2 9796 # Per bank write bursts
system.physmem.perBankWrBursts::3 9387 # Per bank write bursts
system.physmem.perBankWrBursts::4 8893 # Per bank write bursts
system.physmem.perBankWrBursts::5 9110 # Per bank write bursts
system.physmem.perBankWrBursts::6 9958 # Per bank write bursts
system.physmem.perBankWrBursts::7 9669 # Per bank write bursts
system.physmem.perBankWrBursts::8 9689 # Per bank write bursts
system.physmem.perBankWrBursts::9 9901 # Per bank write bursts
system.physmem.perBankWrBursts::10 9876 # Per bank write bursts
system.physmem.perBankWrBursts::11 10215 # Per bank write bursts
system.physmem.perBankWrBursts::12 10815 # Per bank write bursts
system.physmem.perBankWrBursts::13 10652 # Per bank write bursts
system.physmem.perBankWrBursts::14 10531 # Per bank write bursts
system.physmem.perBankWrBursts::15 10637 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 1962839541500 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.readPktSize::6 408360 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.writePktSize::6 162776 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 408168 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 68 # What read queue length does an incoming req see
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.wrQLenPdf::15 2297 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 4384 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 8312 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 9464 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 10119 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 10932 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 11465 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 12365 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 11871 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 11907 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 10784 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 10008 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 8529 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 8090 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 6890 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 6447 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 6307 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 6230 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 345 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 313 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 293 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 266 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 222 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 199 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 227 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 212 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 223 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 206 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 191 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 177 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 154 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 142 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 103 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 80 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 18 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 69162 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 526.295017 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 318.923666 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 416.254848 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 16035 23.18% 23.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 12178 17.61% 40.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 5186 7.50% 48.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3086 4.46% 52.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 3308 4.78% 57.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1800 2.60% 60.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1507 2.18% 62.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1316 1.90% 64.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 24746 35.78% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 69162 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 5880 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 69.428401 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 2107.963348 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-4095 5875 99.91% 99.91% # Reads before turning the bus around for writes
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.93% # Reads before turning the bus around for writes
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.97% # Reads before turning the bus around for writes
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.rdPerTurnAround::73728-77823 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::122880-126975 1 0.02% 100.00% # Reads before turning the bus around for writes
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.rdPerTurnAround::total 5880 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 5880 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 27.295068 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 20.802481 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 33.368634 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23 4837 82.26% 82.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31 186 3.16% 85.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39 281 4.78% 90.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47 57 0.97% 91.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55 98 1.67% 92.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63 42 0.71% 93.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71 21 0.36% 93.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79 12 0.20% 94.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87 21 0.36% 94.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95 6 0.10% 94.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103 10 0.17% 94.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111 8 0.14% 94.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119 13 0.22% 95.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127 5 0.09% 95.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135 22 0.37% 95.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143 44 0.75% 96.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151 23 0.39% 96.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159 6 0.10% 96.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167 80 1.36% 98.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175 40 0.68% 98.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183 14 0.24% 99.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191 24 0.41% 99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-199 14 0.24% 99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-207 2 0.03% 99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-215 5 0.09% 99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-223 1 0.02% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-231 2 0.03% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::232-239 1 0.02% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-247 4 0.07% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5880 # Writes before turning the bus around for reads
system.physmem.totQLat 2202002500 # Total ticks spent queuing
system.physmem.totMemAccLat 9856671250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2041245000 # Total ticks spent in databus transfers
system.physmem.avgQLat 5393.77 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.avgMemAccLat 24143.77 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 13.31 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 5.23 # Average achieved write bandwidth in MiByte/s
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.avgRdBWSys 13.31 # Average system read bandwidth in MiByte/s
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.avgWrBWSys 5.31 # Average system write bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.busUtil 0.14 # Data bus utilization in percentage
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.avgWrQLen 26.11 # Average write queue length when enqueuing
system.physmem.readRowHits 365785 # Number of row buffer hits during reads
system.physmem.writeRowHits 133797 # Number of row buffer hits during writes
system.physmem.readRowHitRate 89.60 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 83.35 # Row buffer hit rate for writes
system.physmem.avgGap 3436728.80 # Average gap between requests
system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 1840639787000 # Time in different power states
system.physmem.memoryStateTime::REF 65543660000 # Time in different power states
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.memoryStateTime::ACT 56660375500 # Time in different power states
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.actEnergy::0 257115600 # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1 265749120 # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0 140291250 # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1 145002000 # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0 1587939600 # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1 1596402600 # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0 506599920 # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1 533407680 # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0 128203398960 # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1 128203398960 # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0 65563204050 # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1 65997539775 # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0 1120194702750 # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1 1119813706500 # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0 1316453252130 # Total energy per rank (pJ)
system.physmem.totalEnergy::1 1316555206635 # Total energy per rank (pJ)
system.physmem.averagePower::0 670.686708 # Core power per rank (mW)
system.physmem.averagePower::1 670.738650 # Core power per rank (mW)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dtb.read_hits 7534386 # DTB read hits
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.dtb.read_misses 7765 # DTB read misses
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu0.dtb.read_acv 210 # DTB read access violations
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.dtb.read_accesses 524069 # DTB read accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dtb.write_hits 5126601 # DTB write hits
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.dtb.write_misses 910 # DTB write misses
system.cpu0.dtb.write_acv 133 # DTB write access violations
system.cpu0.dtb.write_accesses 202595 # DTB write accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dtb.data_hits 12660987 # DTB hits
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.dtb.data_misses 8675 # DTB misses
system.cpu0.dtb.data_acv 343 # DTB access violations
system.cpu0.dtb.data_accesses 726664 # DTB accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.itb.fetch_hits 3654300 # ITB hits
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.itb.fetch_misses 3984 # ITB misses
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu0.itb.fetch_acv 184 # ITB acv
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.itb.fetch_accesses 3658284 # ITB accesses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.write_acv 0 # DTB write access violations
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.data_hits 0 # DTB hits
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.numCycles 3925689160 # number of cpu cycles simulated
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.committedInsts 47974635 # Number of instructions committed
system.cpu0.committedOps 47974635 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 44501266 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 212945 # Number of float alu accesses
system.cpu0.num_func_calls 1202793 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 5632199 # number of instructions that are conditional controls
system.cpu0.num_int_insts 44501266 # number of integer instructions
system.cpu0.num_fp_insts 212945 # number of float instructions
system.cpu0.num_int_register_reads 61193579 # number of times the integer registers were read
system.cpu0.num_int_register_writes 33138119 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 104073 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 105864 # number of times the floating registers were written
system.cpu0.num_mem_refs 12702031 # number of memory refs
system.cpu0.num_load_insts 7562183 # Number of load instructions
system.cpu0.num_store_insts 5139848 # Number of store instructions
system.cpu0.num_idle_cycles 3702096779.998114 # Number of idle cycles
system.cpu0.num_busy_cycles 223592380.001886 # Number of busy cycles
system.cpu0.not_idle_fraction 0.056956 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.943044 # Percentage of idle cycles
system.cpu0.Branches 7223323 # Number of branches fetched
system.cpu0.op_class::No_OpClass 2734296 5.70% 5.70% # Class of executed instruction
system.cpu0.op_class::IntAlu 31541688 65.73% 71.43% # Class of executed instruction
system.cpu0.op_class::IntMult 52334 0.11% 71.54% # Class of executed instruction
system.cpu0.op_class::IntDiv 0 0.00% 71.54% # Class of executed instruction
system.cpu0.op_class::FloatAdd 26783 0.06% 71.60% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 71.60% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 71.60% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 71.60% # Class of executed instruction
system.cpu0.op_class::FloatDiv 1883 0.00% 71.60% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 71.60% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 71.60% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 71.60% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 71.60% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 71.60% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 71.60% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 71.60% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 71.60% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 71.60% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 71.60% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.60% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 71.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 71.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.60% # Class of executed instruction
system.cpu0.op_class::MemRead 7738218 16.13% 87.73% # Class of executed instruction
system.cpu0.op_class::MemWrite 5145965 10.72% 98.45% # Class of executed instruction
system.cpu0.op_class::IprAccess 742486 1.55% 100.00% # Class of executed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.op_class::total 47983653 # Class of executed instruction
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei 165589 # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0 56925 40.22% 40.22% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21 131 0.09% 40.31% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22 1976 1.40% 41.70% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30 424 0.30% 42.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31 82092 58.00% 100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total 141548 # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0 56392 49.08% 49.08% # number of times we switched to this ipl from a different ipl
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.kern.ipl_good::22 1976 1.72% 50.92% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30 424 0.37% 51.29% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 55969 48.71% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 114892 # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0 1903342573000 96.97% 96.97% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21 94358500 0.00% 96.97% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22 767882500 0.04% 97.01% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30 314406500 0.02% 97.03% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31 58324587500 2.97% 100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total 1962843808000 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0 0.990637 # fraction of swpipl calls that actually changed the ipl
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.kern.ipl_used::31 0.681784 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total 0.811682 # fraction of swpipl calls that actually changed the ipl
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed
system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed
system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed
system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed
system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed
system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed
system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed
system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed
system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed
system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed
system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed
system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed
system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed
system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed
system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed
system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed
system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed
system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed
system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed
system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed
system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed
system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed
system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed
system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed
system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed
system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed
system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed
system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 234 # number of syscalls executed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.kern.callpal::wripir 512 0.34% 0.34% # number of callpals executed
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed
system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.kern.callpal::swpctx 3097 2.07% 2.41% # number of callpals executed
system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed
system.cpu0.kern.callpal::swpipl 134593 89.81% 92.26% # number of callpals executed
system.cpu0.kern.callpal::rdps 6634 4.43% 96.68% # number of callpals executed
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.68% # number of callpals executed
system.cpu0.kern.callpal::wrusp 4 0.00% 96.69% # number of callpals executed
system.cpu0.kern.callpal::rdusp 9 0.01% 96.69% # number of callpals executed
system.cpu0.kern.callpal::whami 2 0.00% 96.69% # number of callpals executed
system.cpu0.kern.callpal::rti 4424 2.95% 99.64% # number of callpals executed
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.kern.callpal::callsys 394 0.26% 99.91% # number of callpals executed
system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.kern.callpal::total 149871 # number of callpals executed
system.cpu0.kern.mode_switch::kernel 7013 # number of protection mode switches
system.cpu0.kern.mode_switch::user 1370 # number of protection mode switches
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.kern.mode_good::kernel 1369
system.cpu0.kern.mode_good::user 1370
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.kern.mode_good::idle 0
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.kern.mode_switch_good::kernel 0.195209 # fraction of useful protection mode switches
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.kern.mode_switch_good::total 0.326733 # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel 1959059969000 99.81% 99.81% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user 3783834500 0.19% 100.00% # number of ticks spent at the given mode
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.kern.swap_context 3098 # number of times the context was actually changed
system.cpu0.dcache.tags.replacements 1190018 # number of replacements
system.cpu0.dcache.tags.tagsinuse 505.199068 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 11465472 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 1190530 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 9.630561 # Average number of references to valid blocks.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.dcache.tags.warmup_cycle 108210250 # Cycle when the warmup percentage was hit.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.199068 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986717 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.986717 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.tags.tag_accesses 51888213 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 51888213 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 6450398 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 6450398 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 4712072 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 4712072 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140773 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 140773 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148356 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 148356 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 11162470 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 11162470 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 11162470 # number of overall hits
system.cpu0.dcache.overall_hits::total 11162470 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 942246 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 942246 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 257610 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 257610 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13707 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 13707 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5575 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 5575 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 1199856 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 1199856 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 1199856 # number of overall misses
system.cpu0.dcache.overall_misses::total 1199856 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27226306250 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 27226306250 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10348541688 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 10348541688 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 149709000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 149709000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 42660894 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 42660894 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 37574847938 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 37574847938 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 37574847938 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 37574847938 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7392644 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 7392644 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4969682 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 4969682 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154480 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 154480 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153931 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 153931 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 12362326 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 12362326 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 12362326 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 12362326 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127457 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.127457 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051836 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.051836 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088730 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088730 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.036218 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.036218 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097057 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.097057 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097057 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.097057 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28895.114705 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 28895.114705 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40171.350833 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 40171.350833 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10922.083607 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10922.083607 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7652.178296 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7652.178296 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31316.131217 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 31316.131217 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31316.131217 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 31316.131217 # average overall miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.writebacks::writebacks 685854 # number of writebacks
system.cpu0.dcache.writebacks::total 685854 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 942246 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 942246 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 257610 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 257610 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13707 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13707 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5575 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 5575 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 1199856 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 1199856 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 1199856 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 1199856 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25216322750 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25216322750 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9780175312 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9780175312 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 122281000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 122281000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31509106 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31509106 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34996498062 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 34996498062 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34996498062 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 34996498062 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1461499500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1461499500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2267126500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2267126500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3728626000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3728626000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127457 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127457 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051836 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051836 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088730 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088730 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.036218 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.036218 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097057 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.097057 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097057 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.097057 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26761.931332 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26761.931332 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37965.045270 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37965.045270 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8921.062231 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8921.062231 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5651.857578 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5651.857578 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29167.248455 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29167.248455 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29167.248455 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29167.248455 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.icache.tags.replacements 699671 # number of replacements
system.cpu0.icache.tags.tagsinuse 508.391653 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 47283349 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 700182 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 67.530084 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 40276505250 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.391653 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992952 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.992952 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 436 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 48683959 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 48683959 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 47283349 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 47283349 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 47283349 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 47283349 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 47283349 # number of overall hits
system.cpu0.icache.overall_hits::total 47283349 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 700305 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 700305 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 700305 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 700305 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 700305 # number of overall misses
system.cpu0.icache.overall_misses::total 700305 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9967517496 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 9967517496 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 9967517496 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 9967517496 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 9967517496 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 9967517496 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 47983654 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 47983654 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 47983654 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 47983654 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 47983654 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 47983654 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014595 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.014595 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014595 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.014595 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014595 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.014595 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14233.109140 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14233.109140 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14233.109140 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14233.109140 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14233.109140 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14233.109140 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 700305 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 700305 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 700305 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 700305 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 700305 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 700305 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8561918504 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 8561918504 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8561918504 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 8561918504 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8561918504 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 8561918504 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014595 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.014595 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.014595 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12225.985112 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12225.985112 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12225.985112 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12225.985112 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12225.985112 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12225.985112 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.dtb.read_hits 2382379 # DTB read hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.dtb.read_misses 2620 # DTB read misses
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu1.dtb.read_acv 0 # DTB read access violations
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.dtb.read_accesses 205337 # DTB read accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.dtb.write_hits 1702197 # DTB write hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.dtb.write_misses 235 # DTB write misses
system.cpu1.dtb.write_acv 24 # DTB write access violations
system.cpu1.dtb.write_accesses 89739 # DTB write accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.dtb.data_hits 4084576 # DTB hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.dtb.data_misses 2855 # DTB misses
system.cpu1.dtb.data_acv 24 # DTB access violations
system.cpu1.dtb.data_accesses 295076 # DTB accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.itb.fetch_hits 1808740 # ITB hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.itb.fetch_misses 1064 # ITB misses
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu1.itb.fetch_acv 0 # ITB acv
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.itb.fetch_accesses 1809804 # ITB accesses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.write_acv 0 # DTB write access violations
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.data_hits 0 # DTB hits
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.numCycles 3923834014 # number of cpu cycles simulated
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.committedInsts 12951032 # Number of instructions committed
system.cpu1.committedOps 12951032 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 11936898 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 171199 # Number of float alu accesses
system.cpu1.num_func_calls 411532 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 1284277 # number of instructions that are conditional controls
system.cpu1.num_int_insts 11936898 # number of integer instructions
system.cpu1.num_fp_insts 171199 # number of float instructions
system.cpu1.num_int_register_reads 16412569 # number of times the integer registers were read
system.cpu1.num_int_register_writes 8783541 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 88996 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 90942 # number of times the floating registers were written
system.cpu1.num_mem_refs 4107226 # number of memory refs
system.cpu1.num_load_insts 2395961 # Number of load instructions
system.cpu1.num_store_insts 1711265 # Number of store instructions
system.cpu1.num_idle_cycles 3874307298.691787 # Number of idle cycles
system.cpu1.num_busy_cycles 49526715.308213 # Number of busy cycles
system.cpu1.not_idle_fraction 0.012622 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.987378 # Percentage of idle cycles
system.cpu1.Branches 1849703 # Number of branches fetched
system.cpu1.op_class::No_OpClass 699491 5.40% 5.40% # Class of executed instruction
system.cpu1.op_class::IntAlu 7680347 59.29% 64.69% # Class of executed instruction
system.cpu1.op_class::IntMult 22457 0.17% 64.86% # Class of executed instruction
system.cpu1.op_class::IntDiv 0 0.00% 64.86% # Class of executed instruction
system.cpu1.op_class::FloatAdd 13113 0.10% 64.96% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 64.96% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 64.96% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 64.96% # Class of executed instruction
system.cpu1.op_class::FloatDiv 1759 0.01% 64.98% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 64.98% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 64.98% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 64.98% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 64.98% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 64.98% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 64.98% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 64.98% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 64.98% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 64.98% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 64.98% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.98% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 64.98% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.98% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.98% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.98% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.98% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.98% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.98% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 64.98% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.98% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.98% # Class of executed instruction
system.cpu1.op_class::MemRead 2467292 19.05% 84.02% # Class of executed instruction
system.cpu1.op_class::MemWrite 1712246 13.22% 97.24% # Class of executed instruction
system.cpu1.op_class::IprAccess 357206 2.76% 100.00% # Class of executed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.op_class::total 12953911 # Class of executed instruction
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.kern.inst.quiesce 2765 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 77892 # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0 26462 38.26% 38.26% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22 1970 2.85% 41.11% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30 512 0.74% 41.85% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31 40213 58.15% 100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total 69157 # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0 25618 48.15% 48.15% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22 1970 3.70% 51.85% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30 512 0.96% 52.81% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31 25106 47.19% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total 53206 # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0 1910435586500 97.38% 97.38% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22 701157000 0.04% 97.41% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30 358940000 0.02% 97.43% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31 50421293500 2.57% 100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total 1961916977000 # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0 0.968105 # fraction of swpipl calls that actually changed the ipl
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.kern.ipl_used::31 0.624325 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total 0.769351 # fraction of swpipl calls that actually changed the ipl
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed
system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed
system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed
system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed
system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed
system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed
system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed
system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed
system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed
system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed
system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed
system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed
system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed
system.cpu1.kern.syscall::total 92 # number of syscalls executed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.kern.callpal::wripir 424 0.59% 0.59% # number of callpals executed
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed
system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.kern.callpal::swpctx 1967 2.75% 3.35% # number of callpals executed
system.cpu1.kern.callpal::tbi 3 0.00% 3.35% # number of callpals executed
system.cpu1.kern.callpal::wrent 7 0.01% 3.36% # number of callpals executed
system.cpu1.kern.callpal::swpipl 62982 88.13% 91.49% # number of callpals executed
system.cpu1.kern.callpal::rdps 2216 3.10% 94.59% # number of callpals executed
system.cpu1.kern.callpal::wrkgp 1 0.00% 94.60% # number of callpals executed
system.cpu1.kern.callpal::wrusp 3 0.00% 94.60% # number of callpals executed
system.cpu1.kern.callpal::whami 3 0.00% 94.60% # number of callpals executed
system.cpu1.kern.callpal::rti 3692 5.17% 99.77% # number of callpals executed
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed
system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.kern.callpal::total 71465 # number of callpals executed
system.cpu1.kern.mode_switch::kernel 1923 # number of protection mode switches
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu1.kern.mode_switch::user 367 # number of protection mode switches
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.kern.mode_switch::idle 2902 # number of protection mode switches
system.cpu1.kern.mode_good::kernel 803
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu1.kern.mode_good::user 367
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.kern.mode_good::idle 436
system.cpu1.kern.mode_switch_good::kernel 0.417577 # fraction of useful protection mode switches
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.kern.mode_switch_good::idle 0.150241 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total 0.309322 # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel 17997631500 0.92% 0.92% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user 1494992000 0.08% 0.99% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 1941547962000 99.01% 100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context 1968 # number of times the context was actually changed
system.cpu1.dcache.tags.replacements 157269 # number of replacements
system.cpu1.dcache.tags.tagsinuse 486.065602 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 3912422 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 157596 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 24.825643 # Average number of references to valid blocks.
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.dcache.tags.warmup_cycle 1048852145500 # Cycle when the warmup percentage was hit.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.065602 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949347 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.949347 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 327 # Occupied blocks per task id
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 295 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.638672 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 16561703 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 16561703 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 2221454 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 2221454 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 1590675 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 1590675 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47775 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 47775 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50240 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 50240 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 3812129 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 3812129 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 3812129 # number of overall hits
system.cpu1.dcache.overall_hits::total 3812129 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 115097 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 115097 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 57126 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 57126 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8902 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 8902 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5962 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 5962 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 172223 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 172223 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 172223 # number of overall misses
system.cpu1.dcache.overall_misses::total 172223 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1389994499 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 1389994499 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1079772299 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 1079772299 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80592000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 80592000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 43791416 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 43791416 # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 2469766798 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 2469766798 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 2469766798 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 2469766798 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 2336551 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 2336551 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 1647801 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 1647801 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 56677 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 56677 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56202 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 56202 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 3984352 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 3984352 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 3984352 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 3984352 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049259 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.049259 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034668 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.034668 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.157065 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.157065 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106082 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106082 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043225 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.043225 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043225 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.043225 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12076.722234 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 12076.722234 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18901.591202 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 18901.591202 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9053.246461 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9053.246461 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7345.088225 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7345.088225 # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14340.516644 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 14340.516644 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14340.516644 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 14340.516644 # average overall miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.dcache.writebacks::writebacks 107940 # number of writebacks
system.cpu1.dcache.writebacks::total 107940 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 115097 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 115097 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 57126 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 57126 # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8902 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8902 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5962 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 5962 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 172223 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 172223 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 172223 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 172223 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1159712501 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1159712501 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 962952701 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 962952701 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62788000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 62788000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31865584 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31865584 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2122665202 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 2122665202 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2122665202 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 2122665202 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 22446500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 22446500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 726758000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 726758000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 749204500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 749204500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049259 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049259 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034668 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034668 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.157065 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.157065 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106082 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106082 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043225 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.043225 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043225 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.043225 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10075.957679 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10075.957679 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16856.644978 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16856.644978 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7053.246461 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7053.246461 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5344.780946 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5344.780946 # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12325.097124 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12325.097124 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12325.097124 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12325.097124 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.icache.tags.replacements 318302 # number of replacements
system.cpu1.icache.tags.tagsinuse 446.541764 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 12635057 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 318814 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 39.631437 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 1956986830500 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.541764 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.872152 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.872152 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 72 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3 439 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 13272765 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 13272765 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 12635057 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 12635057 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 12635057 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 12635057 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 12635057 # number of overall hits
system.cpu1.icache.overall_hits::total 12635057 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 318854 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 318854 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 318854 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 318854 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 318854 # number of overall misses
system.cpu1.icache.overall_misses::total 318854 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4204550742 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 4204550742 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 4204550742 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 4204550742 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 4204550742 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 4204550742 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 12953911 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 12953911 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 12953911 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 12953911 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 12953911 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 12953911 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024614 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.024614 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024614 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.024614 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024614 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.024614 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13186.445025 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13186.445025 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13186.445025 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13186.445025 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13186.445025 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13186.445025 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 318854 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 318854 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 318854 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 318854 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 318854 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 318854 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3566590258 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 3566590258 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3566590258 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 3566590258 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3566590258 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 3566590258 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024614 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024614 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024614 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.024614 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024614 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.024614 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11185.653177 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11185.653177 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11185.653177 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11185.653177 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11185.653177 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11185.653177 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.iobus.trans_dist::ReadReq 7373 # Transaction distribution
system.iobus.trans_dist::ReadResp 7373 # Transaction distribution
system.iobus.trans_dist::WriteReq 55631 # Transaction distribution
system.iobus.trans_dist::WriteResp 14079 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13950 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 42552 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83456 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83456 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 126008 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55800 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 82034 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661632 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661632 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2743666 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 13305000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 2453000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer29.occupancy 406206788 # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 28473000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 42016500 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 41696 # number of replacements
system.iocache.tags.tagsinuse 0.577792 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 41712 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 1755504938000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide 0.577792 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide 0.036112 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.036112 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 375552 # Number of tag accesses
system.iocache.tags.data_accesses 375552 # Number of data accesses
system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses
system.iocache.ReadReq_misses::total 176 # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses
system.iocache.demand_misses::tsunami.ide 176 # number of demand (read+write) misses
system.iocache.demand_misses::total 176 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 176 # number of overall misses
system.iocache.overall_misses::total 176 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 21474383 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 21474383 # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13634244905 # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total 13634244905 # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 21474383 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 21474383 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 21474383 # number of overall miss cycles
system.iocache.overall_miss_latency::total 21474383 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide 176 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 176 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 176 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 176 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122013.539773 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 122013.539773 # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328124.877383 # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 328124.877383 # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 122013.539773 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 122013.539773 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 206283 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 23550 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 8.759363 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 41520 # number of writebacks
system.iocache.writebacks::total 41520 # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 176 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 176 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 176 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12321383 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 12321383 # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11473540905 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11473540905 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 12321383 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 12321383 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 12321383 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 12321383 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 70007.857955 # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276124.877383 # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276124.877383 # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 342754 # number of replacements
system.l2c.tags.tagsinuse 65220.433043 # Cycle average of tags in use
system.l2c.tags.total_refs 2449371 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 407927 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 6.004435 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 8652068750 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 55272.994922 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 4808.176589 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 4932.064474 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 162.933205 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 44.263854 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.843399 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.073367 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.075257 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.002486 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.000675 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.995185 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 65173 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 764 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 5225 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 7223 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 51853 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.994461 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 25998619 # Number of tag accesses
system.l2c.tags.data_accesses 25998619 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.inst 687419 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 668122 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 318193 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 105248 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1778982 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 793794 # number of Writeback hits
system.l2c.Writeback_hits::total 793794 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 182 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 544 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 726 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 43 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 23 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 66 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 129870 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 42509 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 172379 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst 687419 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 797992 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 318193 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 147757 # number of demand (read+write) hits
system.l2c.demand_hits::total 1951361 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 687419 # number of overall hits
system.l2c.overall_hits::cpu0.data 797992 # number of overall hits
system.l2c.overall_hits::cpu1.inst 318193 # number of overall hits
system.l2c.overall_hits::cpu1.data 147757 # number of overall hits
system.l2c.overall_hits::total 1951361 # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst 12865 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 271552 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 660 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 293 # number of ReadReq misses
system.l2c.ReadReq_misses::total 285370 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 2959 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 1779 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 4738 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 894 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 916 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1810 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 117973 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 5779 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 123752 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst 12865 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 389525 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 660 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 6072 # number of demand (read+write) misses
system.l2c.demand_misses::total 409122 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst 12865 # number of overall misses
system.l2c.overall_misses::cpu0.data 389525 # number of overall misses
system.l2c.overall_misses::cpu1.inst 660 # number of overall misses
system.l2c.overall_misses::cpu1.data 6072 # number of overall misses
system.l2c.overall_misses::total 409122 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst 945742500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 17666811750 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 48120250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 20711500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 18681386000 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 1125461 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 10172561 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 11298022 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 873463 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 255989 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 1129452 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 8144387768 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 426999979 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 8571387747 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst 945742500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 25811199518 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 48120250 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 447711479 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 27252773747 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst 945742500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 25811199518 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 48120250 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 447711479 # number of overall miss cycles
system.l2c.overall_miss_latency::total 27252773747 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst 700284 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 939674 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 318853 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 105541 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2064352 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 793794 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 793794 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 3141 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 2323 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 5464 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 937 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 939 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 1876 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 247843 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 48288 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 296131 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst 700284 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 1187517 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 318853 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 153829 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2360483 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 700284 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 1187517 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 318853 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 153829 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2360483 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.018371 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.288985 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.002070 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.002776 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.138237 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.942057 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.765820 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.867130 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.954109 # miss rate for SCUpgradeReq accesses
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system.l2c.SCUpgradeReq_miss_rate::total 0.964819 # miss rate for SCUpgradeReq accesses
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system.l2c.demand_miss_rate::cpu0.inst 0.018371 # miss rate for demand accesses
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system.l2c.demand_miss_rate::cpu1.data 0.039472 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.173321 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.018371 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.328016 # miss rate for overall accesses
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system.l2c.overall_miss_rate::cpu1.data 0.039472 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.173321 # miss rate for overall accesses
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system.l2c.ReadReq_avg_miss_latency::cpu0.data 65058.669242 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72909.469697 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 70687.713311 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 65463.734800 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 380.351808 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5718.134345 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 2384.555087 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 977.027964 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 279.463974 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 624.006630 # average SCUpgradeReq miss latency
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system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73888.212320 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 69262.619974 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 73512.825496 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 66263.268129 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 72909.469697 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 73733.774539 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 66612.828807 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 73512.825496 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 66263.268129 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 72909.469697 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 73733.774539 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 66612.828807 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 79704 # number of writebacks
system.l2c.writebacks::total 79704 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst 3 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits
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system.l2c.ReadReq_mshr_misses::cpu0.data 271552 # number of ReadReq MSHR misses
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system.l2c.ReadReq_mshr_misses::cpu1.data 293 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 285359 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 2959 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 1779 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 4738 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 894 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 916 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 1810 # number of SCUpgradeReq MSHR misses
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system.l2c.ReadExReq_mshr_misses::cpu1.data 5779 # number of ReadExReq MSHR misses
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system.l2c.demand_mshr_misses::cpu0.data 389525 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 652 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 6072 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 409111 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 12862 # number of overall MSHR misses
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system.l2c.overall_mshr_misses::cpu1.data 6072 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 409111 # number of overall MSHR misses
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system.l2c.ReadReq_mshr_miss_latency::cpu1.data 17065000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 15110011000 # number of ReadReq MSHR miss cycles
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system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 17805279 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 47553235 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 8971894 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 9173916 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 18145810 # number of SCUpgradeReq MSHR miss cycles
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system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 354144021 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 7016707253 # number of ReadExReq MSHR miss cycles
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system.l2c.demand_mshr_miss_latency::cpu0.data 20934306482 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 39270500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 371209021 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 22126718253 # number of demand (read+write) MSHR miss cycles
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system.l2c.overall_mshr_miss_latency::cpu0.data 20934306482 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 39270500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 371209021 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 22126718253 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1369396000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 20977500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 1390373500 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2137906500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 687013500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 2824920000 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3507302500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 707991000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 4215293500 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018367 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.288985 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.002045 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002776 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.138232 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.942057 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.765820 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.867130 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.954109 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.975506 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.964819 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.475999 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.119678 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.417896 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018367 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.328016 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002045 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.039472 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.173317 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018367 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.328016 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002045 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.039472 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.173317 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60793.986161 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52556.207467 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60230.828221 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 58242.320819 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 52950.882923 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10053.381548 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10008.588533 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10036.562896 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10035.675615 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.192140 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10025.309392 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56475.322591 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61281.194151 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 56699.748311 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60793.986161 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53743.165348 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60230.828221 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61134.555501 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 54084.877339 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60793.986161 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53743.165348 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60230.828221 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61134.555501 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 54084.877339 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 292732 # Transaction distribution
system.membus.trans_dist::ReadResp 292732 # Transaction distribution
system.membus.trans_dist::WriteReq 14079 # Transaction distribution
system.membus.trans_dist::WriteResp 14079 # Transaction distribution
system.membus.trans_dist::Writeback 121224 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
system.membus.trans_dist::UpgradeReq 16421 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 11471 # Transaction distribution
system.membus.trans_dist::UpgradeResp 7051 # Transaction distribution
system.membus.trans_dist::ReadExReq 124094 # Transaction distribution
system.membus.trans_dist::ReadExResp 123249 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42552 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 932442 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 974994 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124815 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 124815 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1099809 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82034 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31235136 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 31317170 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 36634738 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 22113 # Total snoops (count)
system.membus.snoop_fanout::samples 600297 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 600297 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 600297 # Request fanout histogram
system.membus.reqLayer0.occupancy 40801500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 1914880000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
system.membus.respLayer1.occupancy 3840416202 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.respLayer2.occupancy 43136500 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.toL2Bus.trans_dist::ReadReq 2106484 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2106469 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 14079 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 14079 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 793794 # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 16644 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 11537 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 28181 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 298092 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 298092 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1400589 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3132441 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 637707 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 458977 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 5629714 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44818176 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119962112 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20406592 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16779186 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 201966066 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 99450 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 3260906 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 3.012796 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.112395 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3 3219178 98.72% 98.72% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 41728 1.28% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 3260906 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 4802513358 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 3153866996 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 5532423832 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 1434969242 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 787756714 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
Update ref stats. tests/test1/ref/alpha/atomic/stdout: tests/test1/ref/alpha/detailed/stderr: tests/test1/ref/alpha/detailed/stdout: tests/test1/ref/alpha/timing/stdout: Updated output. --HG-- extra : convert_revision : 3189564725ac4d2b3d63e6a71151a52326f8d416
2006-07-27 23:47:43 +02:00
---------- End Simulation Statistics ----------
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