sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity
gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt

1352 lines
154 KiB
Plaintext
Raw Normal View History

Update ref stats. tests/test1/ref/alpha/atomic/stdout: tests/test1/ref/alpha/detailed/stderr: tests/test1/ref/alpha/detailed/stdout: tests/test1/ref/alpha/timing/stdout: Updated output. --HG-- extra : convert_revision : 3189564725ac4d2b3d63e6a71151a52326f8d416
2006-07-27 23:47:43 +02:00
---------- Begin Simulation Statistics ----------
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
sim_seconds 1.955749 # Number of seconds simulated
sim_ticks 1955749107000 # Number of ticks simulated
final_tick 1955749107000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
host_inst_rate 473674 # Simulator instruction rate (inst/s)
host_op_rate 473674 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 15599111797 # Simulator tick rate (ticks/s)
host_mem_usage 350548 # Number of bytes of host memory used
host_seconds 125.38 # Real time elapsed on the host
sim_insts 59387196 # Number of instructions simulated
sim_ops 59387196 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 829760 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 24747584 # Number of bytes read from this memory
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.physmem.bytes_read::cpu1.inst 34368 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 397760 # Number of bytes read from this memory
system.physmem.bytes_read::total 28660288 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 829760 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 34368 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 864128 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7682240 # Number of bytes written to this memory
system.physmem.bytes_written::total 7682240 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst 12965 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 386681 # Number of read requests responded to by this memory
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.physmem.num_reads::cpu1.inst 537 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 6215 # Number of read requests responded to by this memory
system.physmem.num_reads::total 447817 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 120035 # Number of write requests responded to by this memory
system.physmem.num_writes::total 120035 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst 424267 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 12653762 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 1355397 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 17573 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 203380 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14654379 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 424267 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 17573 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 441840 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3928029 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3928029 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3928029 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 424267 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 12653762 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1355397 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 17573 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 203380 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 18582408 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 447817 # Total number of read requests seen
system.physmem.writeReqs 120035 # Total number of write requests seen
system.physmem.cpureqs 571031 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 28660288 # Total number of bytes read from memory
system.physmem.bytesWritten 7682240 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 28660288 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 7682240 # bytesWritten derated as per pkt->getSize()
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.servicedByWrQ 69 # Number of read reqs serviced by write Q
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.physmem.neitherReadNorWrite 3170 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 28165 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 28096 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 28057 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 27780 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 28035 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 27969 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 27895 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 27905 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 28286 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 28089 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 28219 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 28029 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 27787 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 27999 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 27702 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 27735 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 7631 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 7483 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 7551 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 7343 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 7579 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 7442 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 7393 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 7470 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 7849 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 7658 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 7804 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 7534 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 7353 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 7502 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 7171 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 7272 # Track writes on a per bank basis
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.physmem.numWrRetry 9 # Number of times wr buffer was full causing retry
system.physmem.totGap 1955741979500 # Total gap between requests
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.physmem.readPktSize::6 447817 # Categorize read packet sizes
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.physmem.writePktSize::6 120035 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 407051 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 4718 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 3658 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 2202 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3124 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2939 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2694 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 2706 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 2651 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 2603 # What read queue length does an incoming req see
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.physmem.rdQLenPdf::10 1540 # What read queue length does an incoming req see
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.physmem.rdQLenPdf::11 1456 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1432 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1384 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1357 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 1403 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 1635 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 1524 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 905 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 760 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.physmem.wrQLenPdf::0 3699 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 3855 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 4286 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 4335 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 4844 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 5197 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 5204 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 5206 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 5207 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 5219 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 5219 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 5219 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 5219 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 5219 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 5219 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 5219 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 5219 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5219 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5219 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5219 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5219 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5218 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 5218 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 1520 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 1364 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 933 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 884 # What write queue length does an incoming req see
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.physmem.wrQLenPdf::27 375 # What write queue length does an incoming req see
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.physmem.wrQLenPdf::28 22 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 13 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see
system.physmem.totQLat 4786344500 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 13401468250 # Sum of mem lat for all requests
system.physmem.totBusLat 2238740000 # Total cycles spent in databus access
system.physmem.totBankLat 6376383750 # Total cycles spent in bank access
system.physmem.avgQLat 10689.82 # Average queueing delay per request
system.physmem.avgBankLat 14241.01 # Average bank access latency per request
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per request
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.physmem.avgMemAccLat 29930.83 # Average memory access latency
system.physmem.avgRdBW 14.65 # Average achieved read bandwidth in MB/s
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.avgWrBW 3.93 # Average achieved write bandwidth in MB/s
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.physmem.avgConsumedRdBW 14.65 # Average consumed read bandwidth in MB/s
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.avgConsumedWrBW 3.93 # Average consumed write bandwidth in MB/s
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.15 # Data bus utilization in percentage
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.avgRdQLen 0.01 # Average read queue length over time
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.physmem.avgWrQLen 6.57 # Average write queue length over time
system.physmem.readRowHits 419819 # Number of row buffer hits during reads
system.physmem.writeRowHits 92219 # Number of row buffer hits during writes
system.physmem.readRowHitRate 93.76 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 76.83 # Row buffer hit rate for writes
system.physmem.avgGap 3444105.12 # Average gap between requests
system.l2c.replacements 340805 # number of replacements
system.l2c.tagsinuse 65304.474621 # Cycle average of tags in use
system.l2c.total_refs 2495359 # Total number of references to valid blocks.
system.l2c.sampled_refs 405916 # Sample count of references to valid blocks.
system.l2c.avg_refs 6.147476 # Average number of references to valid blocks.
system.l2c.warmup_cycle 6939667751 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 55622.298055 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 4855.652105 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 4698.077679 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 117.035866 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 11.410916 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.848729 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst 0.074091 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.071687 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst 0.001786 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.000174 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.996467 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst 903439 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 772649 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 86404 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 33735 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1796227 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 821961 # number of Writeback hits
system.l2c.Writeback_hits::total 821961 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 169 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 54 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 223 # number of UpgradeReq hits
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.SCUpgradeReq_hits::cpu0.data 21 # number of SCUpgradeReq hits
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.SCUpgradeReq_hits::cpu1.data 21 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 42 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 172231 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 12736 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 184967 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst 903439 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 944880 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 86404 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 46471 # number of demand (read+write) hits
system.l2c.demand_hits::total 1981194 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 903439 # number of overall hits
system.l2c.overall_hits::cpu0.data 944880 # number of overall hits
system.l2c.overall_hits::cpu1.inst 86404 # number of overall hits
system.l2c.overall_hits::cpu1.data 46471 # number of overall hits
system.l2c.overall_hits::total 1981194 # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst 12965 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 271584 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 548 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 188 # number of ReadReq misses
system.l2c.ReadReq_misses::total 285285 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 2447 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 485 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 2932 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 28 # number of SCUpgradeReq misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.SCUpgradeReq_misses::cpu1.data 73 # number of SCUpgradeReq misses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.SCUpgradeReq_misses::total 101 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 115482 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 6045 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 121527 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst 12965 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 387066 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 548 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 6233 # number of demand (read+write) misses
system.l2c.demand_misses::total 406812 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst 12965 # number of overall misses
system.l2c.overall_misses::cpu0.data 387066 # number of overall misses
system.l2c.overall_misses::cpu1.inst 548 # number of overall misses
system.l2c.overall_misses::cpu1.data 6233 # number of overall misses
system.l2c.overall_misses::total 406812 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst 808064500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 11672931500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 35081000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 14352500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 12530429500 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 1060000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 227000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 1287000 # number of UpgradeReq miss cycles
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 22500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 115000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 137500 # number of SCUpgradeReq miss cycles
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.ReadExReq_miss_latency::cpu0.data 5534141500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 342947000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 5877088500 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst 808064500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 17207073000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 35081000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 357299500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 18407518000 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst 808064500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 17207073000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 35081000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 357299500 # number of overall miss cycles
system.l2c.overall_miss_latency::total 18407518000 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst 916404 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 1044233 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 86952 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 33923 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2081512 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 821961 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 821961 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 2616 # number of UpgradeReq accesses(hits+misses)
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.UpgradeReq_accesses::cpu1.data 539 # number of UpgradeReq accesses(hits+misses)
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.UpgradeReq_accesses::total 3155 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 49 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 94 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 143 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 287713 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 18781 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 306494 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst 916404 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 1331946 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 86952 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 52704 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2388006 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 916404 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 1331946 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 86952 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 52704 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2388006 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.014148 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.260080 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.006302 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.005542 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.137057 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935398 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.899814 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.929319 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.571429 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.776596 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.706294 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.401379 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.321868 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.396507 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.014148 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.290602 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.006302 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.118264 # miss rate for demand accesses
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.demand_miss_rate::total 0.170356 # miss rate for demand accesses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.overall_miss_rate::cpu0.inst 0.014148 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.290602 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.006302 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.118264 # miss rate for overall accesses
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.overall_miss_rate::total 0.170356 # miss rate for overall accesses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 62326.610104 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 42980.924870 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 64016.423358 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 76343.085106 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 43922.496801 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 433.183490 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 468.041237 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 438.949523 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 803.571429 # average SCUpgradeReq miss latency
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1575.342466 # average SCUpgradeReq miss latency
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.SCUpgradeReq_avg_miss_latency::total 1361.386139 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 47922.113403 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 56732.340778 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 48360.352021 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 62326.610104 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 44455.139434 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 64016.423358 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 57323.840847 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 45248.217850 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 62326.610104 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 44455.139434 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 64016.423358 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 57323.840847 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 45248.217850 # average overall miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.writebacks::writebacks 78515 # number of writebacks
system.l2c.writebacks::total 78515 # number of writebacks
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_mshr_hits::cpu1.inst 11 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.ReadReq_mshr_misses::cpu0.inst 12965 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 271584 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 537 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 188 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 285274 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 2447 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 485 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 2932 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 28 # number of SCUpgradeReq MSHR misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 73 # number of SCUpgradeReq MSHR misses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.SCUpgradeReq_mshr_misses::total 101 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 115482 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 6045 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 121527 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 12965 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 387066 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 537 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 6233 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 406801 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 12965 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 387066 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 537 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 6233 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 406801 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 644929955 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8338657576 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 27777281 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 12004183 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 9023368995 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 24640443 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4857984 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 29498427 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 280028 # number of SCUpgradeReq MSHR miss cycles
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 730073 # number of SCUpgradeReq MSHR miss cycles
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.SCUpgradeReq_mshr_miss_latency::total 1010101 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4108313953 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 267375786 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 4375689739 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 644929955 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 12446971529 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 27777281 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 279379969 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 13399058734 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 644929955 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 12446971529 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 27777281 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 279379969 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 13399058734 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1372993500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 18178500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 1391172000 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1972884000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 501380500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 2474264500 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3345877500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 519559000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 3865436500 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014148 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.260080 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.006176 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.005542 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.137051 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.935398 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.899814 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.929319 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.571429 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.776596 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.706294 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.401379 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.321868 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.396507 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014148 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.290602 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.006176 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.118264 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.170352 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014148 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.290602 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006176 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.118264 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.170352 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 49743.922484 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 30703.788058 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 51726.780261 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63852.037234 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 31630.534136 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10069.653862 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10016.461856 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10060.855048 # average UpgradeReq mshr miss latency
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 35575.361987 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 44230.899256 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 36005.906004 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 49743.922484 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32157.232950 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 51726.780261 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 44822.712819 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 32937.624868 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 49743.922484 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32157.232950 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 51726.780261 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 44822.712819 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 32937.624868 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.replacements 41694 # number of replacements
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.iocache.tagsinuse 0.572926 # Cycle average of tags in use
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.iocache.total_refs 0 # Total number of references to valid blocks.
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.sampled_refs 41710 # Sample count of references to valid blocks.
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.iocache.avg_refs 0 # Average number of references to valid blocks.
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.iocache.warmup_cycle 1747683301000 # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide 0.572926 # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide 0.035808 # Average percentage of cache occupancy
system.iocache.occ_percent::total 0.035808 # Average percentage of cache occupancy
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses
system.iocache.demand_misses::total 41726 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses
system.iocache.overall_misses::total 41726 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 21042998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 21042998 # number of ReadReq miss cycles
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.iocache.WriteReq_miss_latency::tsunami.ide 10655791911 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 10655791911 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 10676834909 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 10676834909 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 10676834909 # number of overall miss cycles
system.iocache.overall_miss_latency::total 10676834909 # number of overall miss cycles
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120936.770115 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 120936.770115 # average ReadReq miss latency
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256444.741793 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 256444.741793 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 255879.665173 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 255879.665173 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 255879.665173 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 255879.665173 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 285803 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.iocache.blocked::no_mshrs 27265 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 10.482413 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.iocache.writebacks::writebacks 41520 # number of writebacks
system.iocache.writebacks::total 41520 # number of writebacks
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11994249 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 11994249 # number of ReadReq MSHR miss cycles
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8493795674 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 8493795674 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 8505789923 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 8505789923 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 8505789923 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 8505789923 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68932.465517 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 68932.465517 # average ReadReq mshr miss latency
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204413.642520 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 204413.642520 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203848.677635 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 203848.677635 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203848.677635 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 203848.677635 # average overall mshr miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu0.dtb.read_hits 8641604 # DTB read hits
system.cpu0.dtb.read_misses 7443 # DTB read misses
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu0.dtb.read_acv 210 # DTB read access violations
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu0.dtb.read_accesses 490673 # DTB read accesses
system.cpu0.dtb.write_hits 6049321 # DTB write hits
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu0.dtb.write_misses 813 # DTB write misses
system.cpu0.dtb.write_acv 134 # DTB write access violations
system.cpu0.dtb.write_accesses 187452 # DTB write accesses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu0.dtb.data_hits 14690925 # DTB hits
system.cpu0.dtb.data_misses 8256 # DTB misses
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu0.dtb.data_acv 344 # DTB access violations
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu0.dtb.data_accesses 678125 # DTB accesses
system.cpu0.itb.fetch_hits 3853653 # ITB hits
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu0.itb.fetch_misses 3871 # ITB misses
system.cpu0.itb.fetch_acv 184 # ITB acv
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu0.itb.fetch_accesses 3857524 # ITB accesses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.write_acv 0 # DTB write access violations
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.data_hits 0 # DTB hits
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu0.numCycles 3910164768 # number of cpu cycles simulated
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu0.committedInsts 54125350 # Number of instructions committed
system.cpu0.committedOps 54125350 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 50093853 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 294168 # Number of float alu accesses
system.cpu0.num_func_calls 1428171 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 6241814 # number of instructions that are conditional controls
system.cpu0.num_int_insts 50093853 # number of integer instructions
system.cpu0.num_fp_insts 294168 # number of float instructions
system.cpu0.num_int_register_reads 68603455 # number of times the integer registers were read
system.cpu0.num_int_register_writes 37120934 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 143452 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 146554 # number of times the floating registers were written
system.cpu0.num_mem_refs 14736943 # number of memory refs
system.cpu0.num_load_insts 8672910 # Number of load instructions
system.cpu0.num_store_insts 6064033 # Number of store instructions
system.cpu0.num_idle_cycles 3679227117.452844 # Number of idle cycles
system.cpu0.num_busy_cycles 230937650.547156 # Number of busy cycles
system.cpu0.not_idle_fraction 0.059061 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.940939 # Percentage of idle cycles
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei 203014 # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0 72751 40.62% 40.62% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21 131 0.07% 40.69% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22 1976 1.10% 41.80% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30 7 0.00% 41.80% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31 104234 58.20% 100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total 179099 # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0 71384 49.27% 49.27% # number of times we switched to this ipl from a different ipl
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu0.kern.ipl_good::22 1976 1.36% 50.73% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30 7 0.00% 50.73% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 71377 49.27% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 144875 # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0 1898825619000 97.12% 97.12% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21 94636000 0.00% 97.13% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22 768885000 0.04% 97.17% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30 5899500 0.00% 97.17% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31 55387314500 2.83% 100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total 1955082354000 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0 0.981210 # fraction of swpipl calls that actually changed the ipl
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu0.kern.ipl_used::31 0.684777 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total 0.808910 # fraction of swpipl calls that actually changed the ipl
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed
system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed
system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed
system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed
system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed
system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed
system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed
system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed
system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed
system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed
system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed
system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed
system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed
system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed
system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed
system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed
system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed
system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed
system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed
system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed
system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed
system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed
system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed
system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed
system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed
system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed
system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed
system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 222 # number of syscalls executed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu0.kern.callpal::wripir 89 0.05% 0.05% # number of callpals executed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed
system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu0.kern.callpal::swpctx 3897 2.07% 2.12% # number of callpals executed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.kern.callpal::tbi 51 0.03% 2.15% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.00% 2.15% # number of callpals executed
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu0.kern.callpal::swpipl 172231 91.49% 93.64% # number of callpals executed
system.cpu0.kern.callpal::rdps 6679 3.55% 97.19% # number of callpals executed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.kern.callpal::wrkgp 1 0.00% 97.19% # number of callpals executed
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu0.kern.callpal::wrusp 3 0.00% 97.19% # number of callpals executed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.kern.callpal::rdusp 9 0.00% 97.20% # number of callpals executed
system.cpu0.kern.callpal::whami 2 0.00% 97.20% # number of callpals executed
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu0.kern.callpal::rti 4753 2.52% 99.73% # number of callpals executed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.kern.callpal::callsys 381 0.20% 99.93% # number of callpals executed
system.cpu0.kern.callpal::imb 136 0.07% 100.00% # number of callpals executed
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu0.kern.callpal::total 188243 # number of callpals executed
system.cpu0.kern.mode_switch::kernel 7307 # number of protection mode switches
system.cpu0.kern.mode_switch::user 1284 # number of protection mode switches
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu0.kern.mode_good::kernel 1284
system.cpu0.kern.mode_good::user 1284
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.kern.mode_good::idle 0
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu0.kern.mode_switch_good::kernel 0.175722 # fraction of useful protection mode switches
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu0.kern.mode_switch_good::total 0.298917 # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel 1951356000500 99.82% 99.82% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user 3486973000 0.18% 100.00% # number of ticks spent at the given mode
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu0.kern.swap_context 3898 # number of times the context was actually changed
Update ref stats. tests/test1/ref/alpha/atomic/stdout: tests/test1/ref/alpha/detailed/stderr: tests/test1/ref/alpha/detailed/stdout: tests/test1/ref/alpha/timing/stdout: Updated output. --HG-- extra : convert_revision : 3189564725ac4d2b3d63e6a71151a52326f8d416
2006-07-27 23:47:43 +02:00
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
Update ref stats. tests/test1/ref/alpha/atomic/stdout: tests/test1/ref/alpha/detailed/stderr: tests/test1/ref/alpha/detailed/stdout: tests/test1/ref/alpha/timing/stdout: Updated output. --HG-- extra : convert_revision : 3189564725ac4d2b3d63e6a71151a52326f8d416
2006-07-27 23:47:43 +02:00
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
Update ref stats. tests/test1/ref/alpha/atomic/stdout: tests/test1/ref/alpha/detailed/stderr: tests/test1/ref/alpha/detailed/stdout: tests/test1/ref/alpha/timing/stdout: Updated output. --HG-- extra : convert_revision : 3189564725ac4d2b3d63e6a71151a52326f8d416
2006-07-27 23:47:43 +02:00
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
Update ref stats. tests/test1/ref/alpha/atomic/stdout: tests/test1/ref/alpha/detailed/stderr: tests/test1/ref/alpha/detailed/stdout: tests/test1/ref/alpha/timing/stdout: Updated output. --HG-- extra : convert_revision : 3189564725ac4d2b3d63e6a71151a52326f8d416
2006-07-27 23:47:43 +02:00
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu0.icache.replacements 915791 # number of replacements
system.cpu0.icache.tagsinuse 509.170825 # Cycle average of tags in use
system.cpu0.icache.total_refs 53217526 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 916303 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 58.078524 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 32591402000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst 509.170825 # Average occupied blocks per requestor
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.icache.occ_percent::cpu0.inst 0.994474 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.994474 # Average percentage of cache occupancy
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu0.icache.ReadReq_hits::cpu0.inst 53217526 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 53217526 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 53217526 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 53217526 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 53217526 # number of overall hits
system.cpu0.icache.overall_hits::total 53217526 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 916424 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 916424 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 916424 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 916424 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 916424 # number of overall misses
system.cpu0.icache.overall_misses::total 916424 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12661489500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 12661489500 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 12661489500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 12661489500 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 12661489500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 12661489500 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 54133950 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 54133950 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 54133950 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 54133950 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 54133950 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 54133950 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016929 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.016929 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016929 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.016929 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016929 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.016929 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13816.191523 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13816.191523 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13816.191523 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13816.191523 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13816.191523 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13816.191523 # average overall miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 916424 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 916424 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 916424 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 916424 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 916424 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 916424 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10828641500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 10828641500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10828641500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 10828641500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10828641500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 10828641500 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016929 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016929 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016929 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.016929 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016929 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.016929 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11816.191523 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11816.191523 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11816.191523 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11816.191523 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11816.191523 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11816.191523 # average overall mshr miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu0.dcache.replacements 1338546 # number of replacements
system.cpu0.dcache.tagsinuse 506.515538 # Cycle average of tags in use
system.cpu0.dcache.total_refs 13360558 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 1338960 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 9.978310 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 94365000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data 506.515538 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.989288 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.989288 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 7428425 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 7428425 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 5564911 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 5564911 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 176719 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 176719 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191683 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 191683 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 12993336 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 12993336 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 12993336 # number of overall hits
system.cpu0.dcache.overall_hits::total 12993336 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 1036642 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 1036642 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 291308 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 291308 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16366 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 16366 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 435 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 435 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 1327950 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 1327950 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 1327950 # number of overall misses
system.cpu0.dcache.overall_misses::total 1327950 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 22380575500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 22380575500 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8193151000 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 8193151000 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 214111000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 214111000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 2551500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 2551500 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 30573726500 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 30573726500 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 30573726500 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 30573726500 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 8465067 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 8465067 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5856219 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 5856219 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 193085 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 193085 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192118 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 192118 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 14321286 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 14321286 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 14321286 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 14321286 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122461 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.122461 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049743 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.049743 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084761 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084761 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002264 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002264 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092726 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.092726 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092726 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.092726 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21589.493287 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 21589.493287 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 28125.389622 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 28125.389622 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13082.671392 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13082.671392 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5865.517241 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5865.517241 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23023.251252 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 23023.251252 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23023.251252 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 23023.251252 # average overall miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu0.dcache.writebacks::writebacks 791336 # number of writebacks
system.cpu0.dcache.writebacks::total 791336 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1036642 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 1036642 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 291308 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 291308 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16366 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16366 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 435 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 435 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 1327950 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 1327950 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 1327950 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 1327950 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 20307291500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 20307291500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7610535000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7610535000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 181379000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 181379000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1681500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1681500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 27917826500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 27917826500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 27917826500 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 27917826500 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465371000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465371000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2092831000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2092831000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3558202000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3558202000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122461 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122461 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049743 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049743 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.084761 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.084761 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002264 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002264 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092726 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.092726 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092726 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.092726 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 19589.493287 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19589.493287 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26125.389622 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26125.389622 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11082.671392 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11082.671392 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3865.517241 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3865.517241 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21023.251252 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21023.251252 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21023.251252 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21023.251252 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu1.dtb.read_hits 1047303 # DTB read hits
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu1.dtb.read_misses 2992 # DTB read misses
system.cpu1.dtb.read_acv 0 # DTB read access violations
system.cpu1.dtb.read_accesses 239363 # DTB read accesses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu1.dtb.write_hits 650380 # DTB write hits
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu1.dtb.write_misses 341 # DTB write misses
system.cpu1.dtb.write_acv 29 # DTB write access violations
system.cpu1.dtb.write_accesses 105247 # DTB write accesses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu1.dtb.data_hits 1697683 # DTB hits
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu1.dtb.data_misses 3333 # DTB misses
system.cpu1.dtb.data_acv 29 # DTB access violations
system.cpu1.dtb.data_accesses 344610 # DTB accesses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu1.itb.fetch_hits 1487846 # ITB hits
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu1.itb.fetch_misses 1216 # ITB misses
system.cpu1.itb.fetch_acv 0 # ITB acv
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu1.itb.fetch_accesses 1489062 # ITB accesses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.write_acv 0 # DTB write access violations
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.data_hits 0 # DTB hits
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu1.numCycles 3911498214 # number of cpu cycles simulated
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu1.committedInsts 5261846 # Number of instructions committed
system.cpu1.committedOps 5261846 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 4930311 # Number of integer alu accesses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.num_fp_alu_accesses 34031 # Number of float alu accesses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu1.num_func_calls 156775 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 508835 # number of instructions that are conditional controls
system.cpu1.num_int_insts 4930311 # number of integer instructions
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.num_fp_insts 34031 # number of float instructions
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu1.num_int_register_reads 6861337 # number of times the integer registers were read
system.cpu1.num_int_register_writes 3717514 # number of times the integer registers were written
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.num_fp_register_reads 22062 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 21862 # number of times the floating registers were written
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu1.num_mem_refs 1707139 # number of memory refs
system.cpu1.num_load_insts 1053310 # Number of load instructions
system.cpu1.num_store_insts 653829 # Number of store instructions
system.cpu1.num_idle_cycles 3891938527.998010 # Number of idle cycles
system.cpu1.num_busy_cycles 19559686.001990 # Number of busy cycles
system.cpu1.not_idle_fraction 0.005001 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.994999 # Percentage of idle cycles
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu1.kern.inst.quiesce 2300 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 35556 # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0 8967 31.73% 31.73% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22 1970 6.97% 38.70% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30 89 0.31% 39.02% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31 17234 60.98% 100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total 28260 # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0 8957 45.05% 45.05% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22 1970 9.91% 54.95% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30 89 0.45% 55.40% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31 8868 44.60% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total 19884 # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0 1918859770000 98.11% 98.11% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22 708002500 0.04% 98.15% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30 60314000 0.00% 98.15% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31 36120248500 1.85% 100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total 1955748335000 # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0 0.998885 # fraction of swpipl calls that actually changed the ipl
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu1.kern.ipl_used::31 0.514564 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total 0.703609 # fraction of swpipl calls that actually changed the ipl
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed
system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed
system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed
system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed
system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed
system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed
system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed
system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed
system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed
system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed
system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed
system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed
system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed
system.cpu1.kern.syscall::total 104 # number of syscalls executed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu1.kern.callpal::wripir 7 0.02% 0.03% # number of callpals executed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed
system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed
system.cpu1.kern.callpal::swpctx 337 1.17% 1.20% # number of callpals executed
system.cpu1.kern.callpal::tbi 3 0.01% 1.21% # number of callpals executed
system.cpu1.kern.callpal::wrent 7 0.02% 1.23% # number of callpals executed
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu1.kern.callpal::swpipl 23668 81.85% 83.08% # number of callpals executed
system.cpu1.kern.callpal::rdps 2171 7.51% 90.59% # number of callpals executed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.kern.callpal::wrkgp 1 0.00% 90.59% # number of callpals executed
system.cpu1.kern.callpal::wrusp 4 0.01% 90.61% # number of callpals executed
system.cpu1.kern.callpal::whami 3 0.01% 90.62% # number of callpals executed
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu1.kern.callpal::rti 2532 8.76% 99.37% # number of callpals executed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.kern.callpal::callsys 136 0.47% 99.84% # number of callpals executed
system.cpu1.kern.callpal::imb 44 0.15% 100.00% # number of callpals executed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu1.kern.callpal::total 28917 # number of callpals executed
system.cpu1.kern.mode_switch::kernel 802 # number of protection mode switches
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.kern.mode_switch::user 464 # number of protection mode switches
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu1.kern.mode_switch::idle 2068 # number of protection mode switches
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.kern.mode_good::kernel 477
system.cpu1.kern.mode_good::user 464
system.cpu1.kern.mode_good::idle 13
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu1.kern.mode_switch_good::kernel 0.594763 # fraction of useful protection mode switches
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu1.kern.mode_switch_good::idle 0.006286 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total 0.286143 # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel 3597793000 0.18% 0.18% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user 1722339500 0.09% 0.27% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 1950428198000 99.73% 100.00% # number of ticks spent at the given mode
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.kern.swap_context 338 # number of times the context was actually changed
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu1.icache.replacements 86405 # number of replacements
system.cpu1.icache.tagsinuse 422.462851 # Cycle average of tags in use
system.cpu1.icache.total_refs 5178256 # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs 86917 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 59.577022 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 1939963886500 # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst 422.462851 # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst 0.825123 # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total 0.825123 # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst 5178256 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 5178256 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 5178256 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 5178256 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 5178256 # number of overall hits
system.cpu1.icache.overall_hits::total 5178256 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 86953 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 86953 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 86953 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 86953 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 86953 # number of overall misses
system.cpu1.icache.overall_misses::total 86953 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1177160000 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 1177160000 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 1177160000 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 1177160000 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 1177160000 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 1177160000 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 5265209 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 5265209 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 5265209 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 5265209 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 5265209 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 5265209 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016515 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.016515 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016515 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.016515 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016515 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.016515 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13537.888284 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13537.888284 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13537.888284 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13537.888284 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13537.888284 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13537.888284 # average overall miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 86953 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 86953 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 86953 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 86953 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 86953 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 86953 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1003254000 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 1003254000 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1003254000 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 1003254000 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1003254000 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 1003254000 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016515 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016515 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016515 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.016515 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016515 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.016515 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11537.888284 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11537.888284 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11537.888284 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11537.888284 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11537.888284 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11537.888284 # average overall mshr miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu1.dcache.replacements 52787 # number of replacements
system.cpu1.dcache.tagsinuse 417.162104 # Cycle average of tags in use
system.cpu1.dcache.total_refs 1641435 # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs 53299 # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs 30.796732 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 1919955450000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data 417.162104 # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data 0.814770 # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total 0.814770 # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data 1001433 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 1001433 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 616401 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 616401 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 10836 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 10836 # number of LoadLockedReq hits
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11203 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 11203 # number of StoreCondReq hits
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu1.dcache.demand_hits::cpu1.data 1617834 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 1617834 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 1617834 # number of overall hits
system.cpu1.dcache.overall_hits::total 1617834 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 37022 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 37022 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 20409 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 20409 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 934 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 934 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 508 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 508 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 57431 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 57431 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 57431 # number of overall misses
system.cpu1.dcache.overall_misses::total 57431 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 462724500 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 462724500 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 544418500 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 544418500 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 10274000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 10274000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3750500 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 3750500 # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 1007143000 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 1007143000 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 1007143000 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 1007143000 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 1038455 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 1038455 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 636810 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 636810 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 11770 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 11770 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 11711 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 11711 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 1675265 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 1675265 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 1675265 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 1675265 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035651 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.035651 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032049 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.032049 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.079354 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.079354 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.043378 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.043378 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034282 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.034282 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034282 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.034282 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12498.635946 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 12498.635946 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26675.412808 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 26675.412808 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11000 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11000 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7382.874016 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7382.874016 # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17536.574324 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 17536.574324 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17536.574324 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 17536.574324 # average overall miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu1.dcache.writebacks::writebacks 30625 # number of writebacks
system.cpu1.dcache.writebacks::total 30625 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 37022 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 37022 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 20409 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 20409 # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 934 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 934 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 508 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 508 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 57431 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 57431 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 57431 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 57431 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 388680500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 388680500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 503600500 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 503600500 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8406000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 8406000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 2734500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 2734500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 892281000 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 892281000 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 892281000 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 892281000 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19387500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19387500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 530266500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 530266500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 549654000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 549654000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035651 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035651 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032049 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032049 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.079354 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.079354 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.043378 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.043378 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034282 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.034282 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034282 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.034282 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10498.635946 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10498.635946 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24675.412808 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24675.412808 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9000 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9000 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5382.874016 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5382.874016 # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15536.574324 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15536.574324 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15536.574324 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15536.574324 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
Update ref stats. tests/test1/ref/alpha/atomic/stdout: tests/test1/ref/alpha/detailed/stderr: tests/test1/ref/alpha/detailed/stdout: tests/test1/ref/alpha/timing/stdout: Updated output. --HG-- extra : convert_revision : 3189564725ac4d2b3d63e6a71151a52326f8d416
2006-07-27 23:47:43 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink