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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt

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Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
---------- Begin Simulation Statistics ----------
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
sim_seconds 2.526192 # Number of seconds simulated
sim_ticks 2526192217500 # Number of ticks simulated
final_tick 2526192217500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
host_inst_rate 45758 # Simulator instruction rate (inst/s)
host_op_rate 58877 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1916680323 # Simulator tick rate (ticks/s)
host_mem_usage 469072 # Number of bytes of host memory used
host_seconds 1318.00 # Real time elapsed on the host
sim_insts 60309034 # Number of instructions simulated
sim_ops 77600502 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.bytes_read::cpu.dtb.walker 3392 # Number of bytes read from this memory
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.bytes_read::cpu.inst 796992 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9095192 # Number of bytes read from this memory
system.physmem.bytes_read::total 129433368 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 796992 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 796992 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3784320 # Number of bytes written to this memory
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.bytes_written::total 6800392 # Number of bytes written to this memory
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.num_reads::cpu.dtb.walker 53 # Number of read requests responded to by this memory
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.num_reads::cpu.inst 12453 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 142148 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15096864 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 59130 # Number of write requests responded to by this memory
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.num_writes::total 813148 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47319307 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 1343 # Total read bandwidth from this memory (bytes/s)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.bw_read::cpu.inst 315491 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3600356 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 51236548 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 315491 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 315491 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1498033 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1193920 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2691954 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1498033 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47319307 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 1343 # Total bandwidth to/from this memory (bytes/s)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.bw_total::cpu.inst 315491 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4794277 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 53928501 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15096864 # Number of read requests accepted
system.physmem.writeReqs 813148 # Number of write requests accepted
system.physmem.readBursts 15096864 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 813148 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 961540928 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 4658368 # Total number of bytes read from write queue
system.physmem.bytesWritten 6820736 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 129433368 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 6800392 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 72787 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 706544 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 4695 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 943480 # Per bank write bursts
system.physmem.perBankRdBursts::1 937980 # Per bank write bursts
system.physmem.perBankRdBursts::2 937559 # Per bank write bursts
system.physmem.perBankRdBursts::3 937528 # Per bank write bursts
system.physmem.perBankRdBursts::4 943087 # Per bank write bursts
system.physmem.perBankRdBursts::5 937982 # Per bank write bursts
system.physmem.perBankRdBursts::6 937070 # Per bank write bursts
system.physmem.perBankRdBursts::7 936990 # Per bank write bursts
system.physmem.perBankRdBursts::8 943982 # Per bank write bursts
system.physmem.perBankRdBursts::9 938303 # Per bank write bursts
system.physmem.perBankRdBursts::10 937119 # Per bank write bursts
system.physmem.perBankRdBursts::11 936407 # Per bank write bursts
system.physmem.perBankRdBursts::12 943924 # Per bank write bursts
system.physmem.perBankRdBursts::13 938214 # Per bank write bursts
system.physmem.perBankRdBursts::14 937241 # Per bank write bursts
system.physmem.perBankRdBursts::15 937211 # Per bank write bursts
system.physmem.perBankWrBursts::0 6601 # Per bank write bursts
system.physmem.perBankWrBursts::1 6388 # Per bank write bursts
system.physmem.perBankWrBursts::2 6528 # Per bank write bursts
system.physmem.perBankWrBursts::3 6554 # Per bank write bursts
system.physmem.perBankWrBursts::4 6464 # Per bank write bursts
system.physmem.perBankWrBursts::5 6726 # Per bank write bursts
system.physmem.perBankWrBursts::6 6713 # Per bank write bursts
system.physmem.perBankWrBursts::7 6652 # Per bank write bursts
system.physmem.perBankWrBursts::8 7031 # Per bank write bursts
system.physmem.perBankWrBursts::9 6803 # Per bank write bursts
system.physmem.perBankWrBursts::10 6461 # Per bank write bursts
system.physmem.perBankWrBursts::11 6104 # Per bank write bursts
system.physmem.perBankWrBursts::12 7064 # Per bank write bursts
system.physmem.perBankWrBursts::13 6684 # Per bank write bursts
system.physmem.perBankWrBursts::14 6965 # Per bank write bursts
system.physmem.perBankWrBursts::15 6836 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.totGap 2526191083500 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.readPktSize::2 38 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::3 14942208 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.readPktSize::6 154618 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 754018 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.writePktSize::6 59130 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 1056388 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 996212 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 954030 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1063517 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 957350 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1019929 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2630220 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 2535649 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 3302007 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 132277 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 114408 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 104766 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 100921 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 19448 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 18562 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 18244 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 130 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.wrQLenPdf::15 2638 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2876 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4413 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 6283 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 6437 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6394 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6386 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 6781 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 6447 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 6429 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 6438 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 6326 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 6347 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 6741 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 6338 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 6345 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 6465 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 6247 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 132 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 86 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 35 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.bytesPerActivate::samples 995555 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 972.685250 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 907.127186 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 202.423056 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 22972 2.31% 2.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 19885 2.00% 4.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 8241 0.83% 5.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 2302 0.23% 5.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2369 0.24% 5.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1811 0.18% 5.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 8514 0.86% 6.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 964 0.10% 6.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 928497 93.26% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 995555 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6226 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 2413.115644 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 115125.420570 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-524287 6222 99.94% 99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.97% # Reads before turning the bus around for writes
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.rdPerTurnAround::total 6226 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6226 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.117571 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.060113 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 1.446555 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 3515 56.46% 56.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 41 0.66% 57.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 1615 25.94% 83.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 842 13.52% 96.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 76 1.22% 97.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 41 0.66% 98.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 38 0.61% 99.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 41 0.66% 99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24 16 0.26% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6226 # Writes before turning the bus around for reads
system.physmem.totQLat 389908010000 # Total ticks spent queuing
system.physmem.totMemAccLat 671609453750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 75120385000 # Total ticks spent in databus transfers
system.physmem.avgQLat 25952.21 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.avgMemAccLat 44702.21 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 380.63 # Average DRAM read bandwidth in MiByte/s
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.avgWrBW 2.70 # Average achieved write bandwidth in MiByte/s
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.avgRdBWSys 51.24 # Average system read bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.busUtil 2.99 # Data bus utilization in percentage
system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.avgRdQLen 6.80 # Average read queue length when enqueuing
system.physmem.avgWrQLen 27.01 # Average write queue length when enqueuing
system.physmem.readRowHits 14044000 # Number of row buffer hits during reads
system.physmem.writeRowHits 91096 # Number of row buffer hits during writes
system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 85.45 # Row buffer hit rate for writes
system.physmem.avgGap 158779.96 # Average gap between requests
system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 2186359463750 # Time in different power states
system.physmem.memoryStateTime::REF 84354920000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 255472398750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.throughput 54877773 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 16149486 # Transaction distribution
system.membus.trans_dist::ReadResp 16149486 # Transaction distribution
arm: Bump stats after FS config script update This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
2014-02-19 13:59:46 +01:00
system.membus.trans_dist::WriteReq 763349 # Transaction distribution
system.membus.trans_dist::WriteResp 763349 # Transaction distribution
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.trans_dist::Writeback 59130 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4692 # Transaction distribution
arm: Bump stats after FS config script update This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
2014-02-19 13:59:46 +01:00
system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.trans_dist::UpgradeResp 4695 # Transaction distribution
system.membus.trans_dist::ReadExReq 131451 # Transaction distribution
system.membus.trans_dist::ReadExResp 131451 # Transaction distribution
arm: Bump stats after FS config script update This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
2014-02-19 13:59:46 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383044 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885868 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272676 # Packet count per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.pkt_count::total 34157092 # Packet count per connected master and slave (bytes)
arm: Bump stats after FS config script update This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
2014-02-19 13:59:46 +01:00
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390454 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16696096 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19094138 # Cumulative packet size per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.tot_pkt_size::total 138631802 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 138631802 # Total data (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.reqLayer0.occupancy 1486816000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.reqLayer2.occupancy 3620500 # Layer occupancy (ticks)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.reqLayer6.occupancy 17362899000 # Layer occupancy (ticks)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.respLayer1.occupancy 4734189076 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.respLayer2.occupancy 36898450149 # Layer occupancy (ticks)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.membus.respLayer2.utilization 1.5 # Layer utilization (%)
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iobus.throughput 48265574 # Throughput (bytes/s)
arm: Bump stats after FS config script update This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
2014-02-19 13:59:46 +01:00
system.iobus.trans_dist::ReadReq 16125556 # Transaction distribution
system.iobus.trans_dist::ReadResp 16125556 # Transaction distribution
system.iobus.trans_dist::WriteReq 8174 # Transaction distribution
system.iobus.trans_dist::WriteResp 8174 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
arm: Bump stats after FS config script update This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
2014-02-19 13:59:46 +01:00
system.iobus.pkt_count_system.bridge.master::total 2383044 # Packet count per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes)
arm: Bump stats after FS config script update This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
2014-02-19 13:59:46 +01:00
system.iobus.pkt_count::total 32267460 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
arm: Bump stats after FS config script update This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
2014-02-19 13:59:46 +01:00
system.iobus.tot_pkt_size_system.bridge.master::total 2390454 # Cumulative packet size per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes)
arm: Bump stats after FS config script update This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
2014-02-19 13:59:46 +01:00
system.iobus.tot_pkt_size::total 121928118 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 121928118 # Total data (bytes)
system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.reqLayer3.occupancy 518000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
arm: Bump stats after FS config script update This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
2014-02-19 13:59:46 +01:00
system.iobus.respLayer0.occupancy 2374870000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iobus.respLayer1.occupancy 37675624851 # Layer occupancy (ticks)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.branchPred.lookups 14753661 # Number of BP lookups
system.cpu.branchPred.condPredicted 11836576 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 705670 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 9513727 # Number of BTB lookups
system.cpu.branchPred.BTBHits 7668660 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.branchPred.BTBHitPct 80.606265 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1399145 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 72578 # Number of incorrect RAS predictions.
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.checker.dtb.read_hits 14987453 # DTB read hits
system.cpu.checker.dtb.read_misses 7308 # DTB read misses
system.cpu.checker.dtb.write_hits 11227597 # DTB write hits
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.checker.dtb.write_misses 2191 # DTB write misses
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.checker.dtb.flush_entries 3398 # Number of entries that have been flushed from TLB
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.checker.dtb.prefetch_faults 180 # Number of TLB faults due to prefetch
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.checker.dtb.read_accesses 14994761 # DTB read accesses
system.cpu.checker.dtb.write_accesses 11229788 # DTB write accesses
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.checker.dtb.hits 26215050 # DTB hits
system.cpu.checker.dtb.misses 9499 # DTB misses
system.cpu.checker.dtb.accesses 26224549 # DTB accesses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.checker.itb.inst_hits 61483008 # ITB inst hits
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.checker.itb.inst_misses 4473 # ITB inst misses
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.write_hits 0 # DTB write hits
system.cpu.checker.itb.write_misses 0 # DTB write misses
system.cpu.checker.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.checker.itb.flush_entries 2372 # Number of entries that have been flushed from TLB
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.checker.itb.inst_accesses 61487481 # ITB inst accesses
system.cpu.checker.itb.hits 61483008 # DTB hits
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.checker.itb.misses 4473 # DTB misses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.checker.itb.accesses 61487481 # DTB accesses
system.cpu.checker.numCycles 77886295 # number of cpu cycles simulated
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.dtb.read_hits 51183231 # DTB read hits
system.cpu.dtb.read_misses 65223 # DTB read misses
system.cpu.dtb.write_hits 11700953 # DTB write hits
system.cpu.dtb.write_misses 15725 # DTB write misses
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.dtb.flush_entries 3479 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 2504 # Number of TLB faults due to alignment restrictions
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dtb.prefetch_faults 408 # Number of TLB faults due to prefetch
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.dtb.perms_faults 1339 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 51248454 # DTB read accesses
system.cpu.dtb.write_accesses 11716678 # DTB write accesses
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.dtb.hits 62884184 # DTB hits
system.cpu.dtb.misses 80948 # DTB misses
system.cpu.dtb.accesses 62965132 # DTB accesses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.itb.inst_hits 11525561 # ITB inst hits
system.cpu.itb.inst_misses 11159 # ITB inst misses
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.itb.flush_entries 2509 # Number of entries that have been flushed from TLB
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.itb.perms_faults 2978 # Number of TLB faults due to permissions restrictions
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.itb.inst_accesses 11536720 # ITB inst accesses
system.cpu.itb.hits 11525561 # DTB hits
system.cpu.itb.misses 11159 # DTB misses
system.cpu.itb.accesses 11536720 # DTB accesses
system.cpu.numCycles 477128882 # number of cpu cycles simulated
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.fetch.icacheStallCycles 29759197 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 90327124 # Number of instructions fetch has processed
system.cpu.fetch.Branches 14753661 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 9067805 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 20158177 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 4657193 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 122600 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles 98301886 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 2694 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 86268 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 2686675 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 550 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 11522069 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 710692 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 5197 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 154327188 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.729776 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.081128 # Number of instructions fetched each cycle (Total)
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.fetch.rateDist::0 134184573 86.95% 86.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1304702 0.85% 87.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1713961 1.11% 88.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 2295969 1.49% 90.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 2111581 1.37% 91.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1105061 0.72% 92.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 2556088 1.66% 94.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 746376 0.48% 94.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 8308877 5.38% 100.00% # Number of instructions fetched each cycle (Total)
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.fetch.rateDist::total 154327188 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.030922 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.189314 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 31784305 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 100158613 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 18079626 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 1265080 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 3039564 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 1958546 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 172069 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 107310478 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 569843 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 3039564 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 33522780 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 38730372 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 55131073 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 17590016 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 6313383 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 102310347 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 498 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 999968 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 4068660 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 821 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 106387059 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 473967662 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 432826370 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 10390 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 78726997 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 27660061 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1170574 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 1076856 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 12635163 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 19719056 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 13304976 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1944651 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 2472247 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 95130107 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 1987847 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 122918672 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 165693 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 18947879 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 47268855 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 505540 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 154327188 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.796481 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.515149 # Number of insts issued each cycle
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.iq.issued_per_cycle::0 109964387 71.25% 71.25% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 14401004 9.33% 80.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 6880878 4.46% 85.04% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 5675452 3.68% 88.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 12310168 7.98% 96.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 2806019 1.82% 98.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1694480 1.10% 99.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 466491 0.30% 99.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 128309 0.08% 100.00% # Number of insts issued each cycle
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.iq.issued_per_cycle::total 154327188 # Number of insts issued each cycle
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.iq.fu_full::IntAlu 61903 0.70% 0.70% # attempts to use FU when none available
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.iq.fu_full::IntMult 4 0.00% 0.70% # attempts to use FU when none available
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.iq.fu_full::MemRead 8364845 94.62% 95.32% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 413343 4.68% 100.00% # attempts to use FU when none available
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.iq.FU_type_0::No_OpClass 28518 0.02% 0.02% # Type of FU issued
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.iq.FU_type_0::IntAlu 57967032 47.16% 47.18% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 93290 0.08% 47.26% # Type of FU issued
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.26% # Type of FU issued
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.26% # Type of FU issued
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.26% # Type of FU issued
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.26% # Type of FU issued
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.26% # Type of FU issued
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.26% # Type of FU issued
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.26% # Type of FU issued
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.iq.FU_type_0::MemRead 52507324 42.72% 89.98% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 12320347 10.02% 100.00% # Type of FU issued
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.iq.FU_type_0::total 122918672 # Type of FU issued
system.cpu.iq.rate 0.257622 # Inst issue rate
system.cpu.iq.fu_busy_cnt 8840095 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.071918 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 409227562 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 116082546 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 85482417 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 23345 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 12482 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 10295 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 131717793 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 12456 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 625155 # Number of loads that had data forwarded from stores
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 4064409 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 6818 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 30381 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1573005 # Number of stores squashed
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 34107982 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 680619 # Number of times an access to memory failed due to the cache being blocked
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.iew.iewSquashCycles 3039564 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 30259815 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 434333 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 97340803 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 205354 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 19719056 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 13304976 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1415400 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 113322 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 3328 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 30381 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 350453 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 269952 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 620405 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 120843569 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 51870507 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 2075103 # Number of squashed instructions skipped in execute
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.iew.exec_nop 222849 # number of nop insts executed
system.cpu.iew.exec_refs 64083354 # number of memory reference insts executed
system.cpu.iew.exec_branches 11822089 # Number of branches executed
system.cpu.iew.exec_stores 12212847 # Number of stores executed
system.cpu.iew.exec_rate 0.253272 # Inst execution rate
system.cpu.iew.wb_sent 119902421 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 85492712 # cumulative count of insts written-back
system.cpu.iew.wb_producers 47017508 # num instructions producing a value
system.cpu.iew.wb_consumers 87566112 # num instructions consuming a value
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.iew.wb_rate 0.179182 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.536937 # average fanout of values written-back
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.commitSquashedInsts 18682974 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1482307 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 536093 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 151287624 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.513928 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.489816 # Number of insts commited each cycle
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.committed_per_cycle::0 122817908 81.18% 81.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 14643914 9.68% 90.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 3918754 2.59% 93.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 2134639 1.41% 94.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 1621396 1.07% 95.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 973729 0.64% 96.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 1595383 1.05% 97.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 716191 0.47% 98.11% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 2865710 1.89% 100.00% # Number of insts commited each cycle
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.committed_per_cycle::total 151287624 # Number of insts commited each cycle
system.cpu.commit.committedInsts 60459415 # Number of instructions committed
system.cpu.commit.committedOps 77750883 # Number of ops (including micro ops) committed
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.refs 27386618 # Number of memory references committed
system.cpu.commit.loads 15654647 # Number of loads committed
system.cpu.commit.membars 403571 # Number of memory barriers committed
system.cpu.commit.branches 10306311 # Number of branches committed
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.int_insts 69190973 # Number of committed integer instructions.
system.cpu.commit.function_calls 991245 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 50274217 64.66% 64.66% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 87935 0.11% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 2113 0.00% 64.78% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.78% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.78% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.78% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 15654647 20.13% 84.91% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 11731971 15.09% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 77750883 # Class of committed instruction
system.cpu.commit.bw_lim_events 2865710 # number cycles where commit BW limit reached
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.rob.rob_reads 243007370 # The number of ROB reads
system.cpu.rob.rob_writes 195993770 # The number of ROB writes
system.cpu.timesIdled 1776375 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 322801694 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 4575172520 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 60309034 # Number of Instructions Simulated
system.cpu.committedOps 77600502 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 7.911400 # CPI: Cycles Per Instruction
system.cpu.cpi_total 7.911400 # CPI: Total CPI of All Threads
system.cpu.ipc 0.126400 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.126400 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 548643018 # number of integer regfile reads
system.cpu.int_regfile_writes 87545925 # number of integer regfile writes
system.cpu.fp_regfile_reads 8332 # number of floating regfile reads
system.cpu.fp_regfile_writes 2902 # number of floating regfile writes
system.cpu.misc_regfile_reads 268108891 # number of misc regfile reads
system.cpu.misc_regfile_writes 1173224 # number of misc regfile writes
system.cpu.toL2Bus.throughput 58876928 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 2658786 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2658785 # Transaction distribution
arm: Bump stats after FS config script update This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
2014-02-19 13:59:46 +01:00
system.cpu.toL2Bus.trans_dist::WriteReq 763349 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 763349 # Transaction distribution
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.toL2Bus.trans_dist::Writeback 607456 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2978 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 246178 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 246178 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1963155 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5795994 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30467 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128822 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 7918438 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62783488 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85496634 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 41888 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215832 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 148537842 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 148537842 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 196596 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 3128822166 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 1475557763 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 2549946762 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.toL2Bus.respLayer2.occupancy 19999491 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.toL2Bus.respLayer3.occupancy 74967796 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.icache.tags.replacements 981488 # number of replacements
system.cpu.icache.tags.tagsinuse 511.574363 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 10460581 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 982000 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 10.652323 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 6957426250 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.574363 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.999169 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.999169 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 222 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 155 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.icache.tags.tag_accesses 12503981 # Number of tag accesses
system.cpu.icache.tags.data_accesses 12503981 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 10460581 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 10460581 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 10460581 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 10460581 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 10460581 # number of overall hits
system.cpu.icache.overall_hits::total 10460581 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1061360 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1061360 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1061360 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1061360 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1061360 # number of overall misses
system.cpu.icache.overall_misses::total 1061360 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 14265779687 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 14265779687 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 14265779687 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 14265779687 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 14265779687 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 14265779687 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 11521941 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 11521941 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 11521941 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 11521941 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 11521941 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 11521941 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092116 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.092116 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.092116 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.092116 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.092116 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.092116 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13441.037619 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13441.037619 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13441.037619 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13441.037619 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13441.037619 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13441.037619 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 7028 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.icache.blocked::no_mshrs 352 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 19.965909 # average number of cycles each access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79319 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 79319 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 79319 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 79319 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 79319 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 79319 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 982041 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 982041 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 982041 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 982041 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 982041 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 982041 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11583712225 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 11583712225 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11583712225 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 11583712225 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11583712225 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 11583712225 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8965500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8965500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8965500 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 8965500 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085232 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085232 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085232 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.085232 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085232 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.085232 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11795.548480 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11795.548480 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11795.548480 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11795.548480 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11795.548480 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11795.548480 # average overall mshr miss latency
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.tags.replacements 64387 # number of replacements
system.cpu.l2cache.tags.tagsinuse 51384.068329 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1888247 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 129781 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 14.549487 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 2490875317000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 36937.693378 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 37.347999 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000373 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 8175.789418 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 6233.237161 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.563624 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000570 # Average percentage of cache occupancy
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124753 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.095112 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.784059 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023 27 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65367 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 26 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 353 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3046 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6928 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54999 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000412 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997421 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 18797143 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 18797143 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53905 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10470 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 968525 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 386928 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1419828 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 607456 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 607456 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 45 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 45 # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 9 # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 112956 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 112956 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 53905 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 10470 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 968525 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 499884 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1532784 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 53905 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 10470 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 968525 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 499884 # number of overall hits
system.cpu.l2cache.overall_hits::total 1532784 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 53 # number of ReadReq misses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.inst 12346 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 10726 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 23127 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2921 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 2921 # number of UpgradeReq misses
arm: Bump stats after FS config script update This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
2014-02-19 13:59:46 +01:00
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 133222 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 133222 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 53 # number of demand (read+write) misses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.demand_misses::cpu.inst 12346 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 143948 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 156349 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 53 # number of overall misses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.overall_misses::cpu.inst 12346 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 143948 # number of overall misses
system.cpu.l2cache.overall_misses::total 156349 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4489500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 430000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 894766750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 805694000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1705380250 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 465480 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 465480 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9848665479 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 9848665479 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4489500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 430000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 894766750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 10654359479 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 11554045729 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4489500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 430000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 894766750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 10654359479 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 11554045729 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53958 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10472 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 980871 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 397654 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1442955 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 607456 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 607456 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2966 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2966 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 12 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 246178 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 246178 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53958 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 10472 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 980871 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 643832 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1689133 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53958 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 10472 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 980871 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 643832 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1689133 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000982 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000191 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012587 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026973 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.016028 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984828 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984828 # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541161 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.541161 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000982 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000191 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012587 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.223580 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.092562 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000982 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000191 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012587 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.223580 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.092562 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 84707.547170 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 215000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72474.222420 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75115.979862 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 73739.795477 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 159.356385 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 159.356385 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73926.719904 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73926.719904 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 84707.547170 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 215000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72474.222420 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74015.335253 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 73899.070215 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 84707.547170 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 215000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72474.222420 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74015.335253 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 73899.070215 # average overall miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.writebacks::writebacks 59130 # number of writebacks
system.cpu.l2cache.writebacks::total 59130 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 14 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 14 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 67 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 67 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 81 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 53 # number of ReadReq MSHR misses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12332 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10659 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 23046 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2921 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2921 # number of UpgradeReq MSHR misses
arm: Bump stats after FS config script update This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
2014-02-19 13:59:46 +01:00
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133222 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 133222 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 53 # number of demand (read+write) MSHR misses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 12332 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 143881 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 156268 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 53 # number of overall MSHR misses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.overall_mshr_misses::cpu.inst 12332 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 143881 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 156268 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3834000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 405500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 738779500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 668273250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1411292250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29213921 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29213921 # number of UpgradeReq MSHR miss cycles
arm: Bump stats after FS config script update This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
2014-02-19 13:59:46 +01:00
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8190370021 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8190370021 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3834000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 405500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 738779500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8858643271 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 9601662271 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3834000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 405500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 738779500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8858643271 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 9601662271 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6434999 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166942201250 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166948636249 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17456853479 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17456853479 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6434999 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184399054729 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184405489728 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012572 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026805 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015971 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.984828 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.984828 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541161 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541161 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012572 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223476 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.092514 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012572 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223476 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.092514 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 202750 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59907.517029 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62695.679707 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61238.056496 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.342349 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.342349 # average UpgradeReq mshr miss latency
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61479.110215 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61479.110215 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 202750 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59907.517029 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61569.236181 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61443.560236 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 202750 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59907.517029 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61569.236181 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61443.560236 # average overall mshr miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.dcache.tags.replacements 643320 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.993245 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 21508532 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 643832 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 33.407056 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 42989250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.993245 # Average occupied blocks per requestor
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.dcache.tags.tag_accesses 101516564 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 101516564 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 13756930 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 13756930 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 7258142 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 7258142 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 242767 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 242767 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 247595 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 247595 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 21015072 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 21015072 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 21015072 # number of overall hits
system.cpu.dcache.overall_hits::total 21015072 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 735153 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 735153 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2964059 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2964059 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 13525 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 13525 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data 3699212 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3699212 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3699212 # number of overall misses
system.cpu.dcache.overall_misses::total 3699212 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 9975087313 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 9975087313 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 139822431498 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 139822431498 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185099999 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 185099999 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 193503 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 193503 # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 149797518811 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 149797518811 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 149797518811 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 149797518811 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 14492083 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 14492083 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 10222201 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 10222201 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256292 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 256292 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 24714284 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 24714284 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 24714284 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 24714284 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050728 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.050728 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289963 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.289963 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052772 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052772 # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.149679 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.149679 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.149679 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.149679 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13568.722855 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13568.722855 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47172.620888 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 47172.620888 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13685.767024 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13685.767024 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 40494.440116 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 40494.440116 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 40494.440116 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 40494.440116 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 32269 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 24322 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 2609 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 289 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.368340 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 84.159170 # average number of cycles each access was blocked
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.dcache.writebacks::writebacks 607456 # number of writebacks
system.cpu.dcache.writebacks::total 607456 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 349595 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 349595 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2715007 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 2715007 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1337 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 1337 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 3064602 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 3064602 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 3064602 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 3064602 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385558 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 385558 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249052 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 249052 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12188 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 12188 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 634610 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 634610 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 634610 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 634610 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4962813125 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4962813125 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11330760273 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 11330760273 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145614251 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145614251 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169497 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169497 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16293573398 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 16293573398 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16293573398 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 16293573398 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335819750 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335819750 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26860394736 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26860394736 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209196214486 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 209196214486 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026605 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026605 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024364 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024364 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047555 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047555 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025678 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.025678 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025678 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.025678 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12871.767996 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12871.767996 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45495.560256 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45495.560256 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11947.345832 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11947.345832 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25674.939566 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25674.939566 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25674.939566 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 25674.939566 # average overall mshr miss latency
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iocache.tags.replacements 0 # number of replacements
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.iocache.tags.tag_accesses 0 # Number of tag accesses
system.iocache.tags.data_accesses 0 # Number of data accesses
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1712402234851 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1712402234851 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1712402234851 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1712402234851 # number of overall MSHR uncacheable cycles
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.kern.inst.quiesce 83034 # number of quiesce instructions executed
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
---------- End Simulation Statistics ----------
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