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gem5/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini

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X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[root]
type=Root
children=system
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
full_system=true
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sim_quantum=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=LinuxX86System
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
children=acpi_description_table_pointer apicbridge bridge clk_domain cpu cpu_clk_domain dvfs_handler e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache membus pc physmem smbios_table voltage_domain
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
acpi_description_table_pointer=system.acpi_description_table_pointer
boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
cache_line_size=64
clk_domain=system.clk_domain
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
e820_table=system.e820_table
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: update stats to after GPU checkin
2016-01-22 16:42:13 +01:00
exit_on_work_items=false
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
stats: bump stats to reflect ruby tester changes
2015-12-12 23:27:38 +01:00
kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
kernel_addr_check=true
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
load_addr_mask=18446744073709551615
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
load_offset=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
mem_mode=timing
x86 regressions: updates due to new instructions and cpuid
2013-01-15 14:43:23 +01:00
mem_ranges=0:134217727
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
memories=system.physmem
stats: changes to due to recent set of patches
2015-03-09 15:39:09 +01:00
mmap_using_noreserve=false
stats: Update for UDelayEvent quiesce change
2015-10-10 23:45:41 +02:00
multi_thread=false
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
num_work_ids=16
stats: update stats to after GPU checkin
2016-01-22 16:42:13 +01:00
readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
smbios_table=system.smbios_table
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system_port=system.membus.slave[1]
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.acpi_description_table_pointer]
type=X86ACPIRSDP
children=xsdt
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
oem_id=
revision=2
rsdt=Null
xsdt=system.acpi_description_table_pointer.xsdt
[system.acpi_description_table_pointer.xsdt]
type=X86ACPIXSDT
creator_id=
creator_revision=0
entries=
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
oem_id=
oem_revision=0
oem_table_id=
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
[system.apicbridge]
type=Bridge
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
delay=50000
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
ranges=11529215046068469760:11529215046068473855
req_size=16
resp_size=16
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
master=system.membus.slave[0]
slave=system.iobus.master[0]
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.bridge]
type=Bridge
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
delay=50000
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
ranges=3221225472:4294901760 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
req_size=16
resp_size=16
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
master=system.iobus.slave[0]
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
slave=system.membus.master[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
domain_id=-1
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
init_perf_level=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
voltage_domain=system.voltage_domain
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.cpu]
type=TimingSimpleCPU
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=apic_clk_domain dcache dtb dtb_walker_cache icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
branchPred=Null
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
checker=Null
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
x86 regressions: updates due to new instructions and cpuid
2013-01-15 14:43:23 +01:00
isa=system.cpu.isa
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
simpoint_start_insts=
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
socket_id=0
x86 regressions: updates due to new instructions and cpuid
2013-01-15 14:43:23 +01:00
switched_out=false
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
system=system
tracer=system.cpu.tracer
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
workload=
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu.apic_clk_domain]
type=DerivedClockDomain
clk_divider=16
clk_domain=system.cpu_clk_domain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.cpu.dcache]
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
type=Cache
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=tags
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
addr_ranges=0:18446744073709551615
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
assoc=4
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
clusivity=mostly_incl
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
demand_mshr_reserve=1
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
forward_snoops=true
regression test: update a couple of config.ini files
2012-12-06 17:26:12 +01:00
hit_latency=2
stats: x86: update stats missed out on in preivous changeset
2015-07-06 03:26:18 +02:00
is_read_only=false
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
max_miss_count=0
mshrs=4
prefetch_on_access=false
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
prefetcher=Null
regression test: update a couple of config.ini files
2012-12-06 17:26:12 +01:00
response_latency=2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
size=32768
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
tags=system.cpu.dcache.tags
regression test: update a couple of config.ini files
2012-12-06 17:26:12 +01:00
tgts_per_mshr=20
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
write_buffers=8
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
writeback_clean=false
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
cpu_side=system.cpu.dcache_port
regression test: update a couple of config.ini files
2012-12-06 17:26:12 +01:00
mem_side=system.cpu.toL2Bus.slave[1]
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu.dcache.tags]
type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
hit_latency=2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
size=32768
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.cpu.dtb]
type=X86TLB
children=walker
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=X86PagetableWalker
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
num_squash_per_cycle=4
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
system=system
port=system.cpu.dtb_walker_cache.cpu_side
[system.cpu.dtb_walker_cache]
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
type=Cache
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=tags
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
addr_ranges=0:18446744073709551615
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
assoc=2
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
clusivity=mostly_incl
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
demand_mshr_reserve=1
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: x86: update stats missed out on in preivous changeset
2015-07-06 03:26:18 +02:00
forward_snoops=false
regression test: update a couple of config.ini files
2012-12-06 17:26:12 +01:00
hit_latency=2
stats: x86: update stats missed out on in preivous changeset
2015-07-06 03:26:18 +02:00
is_read_only=false
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
max_miss_count=0
mshrs=10
prefetch_on_access=false
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
prefetcher=Null
regression test: update a couple of config.ini files
2012-12-06 17:26:12 +01:00
response_latency=2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
size=1024
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
tags=system.cpu.dtb_walker_cache.tags
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
tgts_per_mshr=12
write_buffers=8
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
writeback_clean=false
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
cpu_side=system.cpu.dtb.walker.port
regression test: update a couple of config.ini files
2012-12-06 17:26:12 +01:00
mem_side=system.cpu.toL2Bus.slave[3]
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu.dtb_walker_cache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
hit_latency=2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
size=1024
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.cpu.icache]
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
type=Cache
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=tags
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
addr_ranges=0:18446744073709551615
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
assoc=1
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
clusivity=mostly_incl
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
demand_mshr_reserve=1
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
forward_snoops=true
regression test: update a couple of config.ini files
2012-12-06 17:26:12 +01:00
hit_latency=2
stats: x86: update stats missed out on in preivous changeset
2015-07-06 03:26:18 +02:00
is_read_only=true
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
max_miss_count=0
mshrs=4
prefetch_on_access=false
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
prefetcher=Null
regression test: update a couple of config.ini files
2012-12-06 17:26:12 +01:00
response_latency=2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
size=32768
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
tags=system.cpu.icache.tags
regression test: update a couple of config.ini files
2012-12-06 17:26:12 +01:00
tgts_per_mshr=20
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
write_buffers=8
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
writeback_clean=true
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
cpu_side=system.cpu.icache_port
regression test: update a couple of config.ini files
2012-12-06 17:26:12 +01:00
mem_side=system.cpu.toL2Bus.slave[0]
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu.icache.tags]
type=LRU
assoc=1
block_size=64
clk_domain=system.cpu_clk_domain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
hit_latency=2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
size=32768
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.cpu.interrupts]
type=X86LocalApic
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu.apic_clk_domain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
int_latency=1000
pio_addr=2305843009213693952
x86 Regressions: Update stats due to register predication
2012-09-11 16:34:40 +02:00
pio_latency=100000
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
system=system
x86 regressions: updates due to new instructions and cpuid
2013-01-15 14:43:23 +01:00
int_master=system.membus.slave[3]
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
int_slave=system.membus.master[2]
pio=system.membus.master[1]
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
x86 regressions: updates due to new instructions and cpuid
2013-01-15 14:43:23 +01:00
[system.cpu.isa]
type=X86ISA
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
x86 regressions: updates due to new instructions and cpuid
2013-01-15 14:43:23 +01:00
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.cpu.itb]
type=X86TLB
children=walker
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=X86PagetableWalker
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
num_squash_per_cycle=4
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
system=system
port=system.cpu.itb_walker_cache.cpu_side
[system.cpu.itb_walker_cache]
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
type=Cache
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=tags
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
addr_ranges=0:18446744073709551615
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
assoc=2
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
clusivity=mostly_incl
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
demand_mshr_reserve=1
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: x86: update stats missed out on in preivous changeset
2015-07-06 03:26:18 +02:00
forward_snoops=false
regression test: update a couple of config.ini files
2012-12-06 17:26:12 +01:00
hit_latency=2
stats: x86: update stats missed out on in preivous changeset
2015-07-06 03:26:18 +02:00
is_read_only=false
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
max_miss_count=0
mshrs=10
prefetch_on_access=false
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
prefetcher=Null
regression test: update a couple of config.ini files
2012-12-06 17:26:12 +01:00
response_latency=2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
size=1024
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
tags=system.cpu.itb_walker_cache.tags
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
tgts_per_mshr=12
write_buffers=8
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
writeback_clean=false
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
cpu_side=system.cpu.itb.walker.port
regression test: update a couple of config.ini files
2012-12-06 17:26:12 +01:00
mem_side=system.cpu.toL2Bus.slave[2]
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu.itb_walker_cache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
hit_latency=2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
size=1024
regression test: update a couple of config.ini files
2012-12-06 17:26:12 +01:00
[system.cpu.l2cache]
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
type=Cache
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=tags
regression test: update a couple of config.ini files
2012-12-06 17:26:12 +01:00
addr_ranges=0:18446744073709551615
assoc=8
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
clusivity=mostly_incl
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
demand_mshr_reserve=1
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
regression test: update a couple of config.ini files
2012-12-06 17:26:12 +01:00
forward_snoops=true
hit_latency=20
stats: x86: update stats missed out on in preivous changeset
2015-07-06 03:26:18 +02:00
is_read_only=false
regression test: update a couple of config.ini files
2012-12-06 17:26:12 +01:00
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
response_latency=20
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
regression test: update a couple of config.ini files
2012-12-06 17:26:12 +01:00
size=4194304
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
tags=system.cpu.l2cache.tags
regression test: update a couple of config.ini files
2012-12-06 17:26:12 +01:00
tgts_per_mshr=12
write_buffers=8
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
writeback_clean=false
regression test: update a couple of config.ini files
2012-12-06 17:26:12 +01:00
cpu_side=system.cpu.toL2Bus.master[0]
x86 regressions: updates due to new instructions and cpuid
2013-01-15 14:43:23 +01:00
mem_side=system.membus.slave[2]
regression test: update a couple of config.ini files
2012-12-06 17:26:12 +01:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
hit_latency=20
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
size=4194304
regression test: update a couple of config.ini files
2012-12-06 17:26:12 +01:00
[system.cpu.toL2Bus]
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
type=CoherentXBar
stats: Update for UDelayEvent quiesce change
2015-10-10 23:45:41 +02:00
children=snoop_filter
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: changes to due to recent set of patches
2015-03-09 15:39:09 +01:00
forward_latency=0
frontend_latency=1
response_latency=1
stats: Update for UDelayEvent quiesce change
2015-10-10 23:45:41 +02:00
snoop_filter=system.cpu.toL2Bus.snoop_filter
stats: changes to due to recent set of patches
2015-03-09 15:39:09 +01:00
snoop_response_latency=1
regressions: updates due to changes to o3 cpu, x86 memory map
2013-03-29 20:05:36 +01:00
system=system
regression test: update a couple of config.ini files
2012-12-06 17:26:12 +01:00
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
stats: Update for UDelayEvent quiesce change
2015-10-10 23:45:41 +02:00
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.cpu.tracer]
type=ExeTracer
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
domain_id=-1
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
init_perf_level=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
voltage_domain=system.voltage_domain
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.e820_table]
type=X86E820Table
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
children=entries0 entries1 entries2 entries3 entries4
entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 system.e820_table.entries4
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.e820_table.entries0]
type=X86E820Entry
addr=0
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
regressions: updates due to changes to o3 cpu, x86 memory map
2013-03-29 20:05:36 +01:00
range_type=1
size=654336
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.e820_table.entries1]
type=X86E820Entry
regressions: updates due to changes to o3 cpu, x86 memory map
2013-03-29 20:05:36 +01:00
addr=654336
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
regressions: updates due to changes to o3 cpu, x86 memory map
2013-03-29 20:05:36 +01:00
range_type=2
size=394240
[system.e820_table.entries2]
type=X86E820Entry
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
addr=1048576
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
range_type=1
size=133169152
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
[system.e820_table.entries3]
type=X86E820Entry
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
addr=134217728
eventq_index=0
range_type=2
size=3087007744
[system.e820_table.entries4]
type=X86E820Entry
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
addr=4294901760
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
range_type=2
size=65536
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.intel_mp_pointer]
type=X86IntelMPFloatingPointer
default_config=0
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
imcr_present=true
spec_rev=4
[system.intel_mp_table]
type=X86IntelMPConfigTable
children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 ext_entries
base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
ext_entries=system.intel_mp_table.ext_entries
local_apic=4276092928
oem_id=
oem_table_addr=0
oem_table_size=0
product_id=
spec_rev=4
[system.intel_mp_table.base_entries00]
type=X86IntelMPProcessor
bootstrap=true
enable=true
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
family=0
feature_flags=0
local_apic_id=0
local_apic_version=20
model=0
stepping=0
[system.intel_mp_table.base_entries01]
type=X86IntelMPIOAPIC
address=4273995776
enable=true
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
id=1
version=17
[system.intel_mp_table.base_entries02]
type=X86IntelMPBus
bus_id=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
bus_type=PCI
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.intel_mp_table.base_entries03]
type=X86IntelMPBus
bus_id=1
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
bus_type=ISA
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.intel_mp_table.base_entries04]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=16
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
interrupt_type=INT
polarity=ConformPolarity
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
source_bus_id=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
source_bus_irq=16
trigger=ConformTrigger
[system.intel_mp_table.base_entries05]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=0
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
interrupt_type=ExtInt
polarity=ConformPolarity
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
source_bus_id=1
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
source_bus_irq=0
trigger=ConformTrigger
[system.intel_mp_table.base_entries06]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
interrupt_type=INT
polarity=ConformPolarity
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
source_bus_id=1
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
source_bus_irq=0
trigger=ConformTrigger
[system.intel_mp_table.base_entries07]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=0
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
interrupt_type=ExtInt
polarity=ConformPolarity
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
source_bus_id=1
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
source_bus_irq=1
trigger=ConformTrigger
[system.intel_mp_table.base_entries08]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=1
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
interrupt_type=INT
polarity=ConformPolarity
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
source_bus_id=1
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
source_bus_irq=1
trigger=ConformTrigger
[system.intel_mp_table.base_entries09]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=0
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
interrupt_type=ExtInt
polarity=ConformPolarity
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
source_bus_id=1
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
source_bus_irq=3
trigger=ConformTrigger
[system.intel_mp_table.base_entries10]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=3
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
interrupt_type=INT
polarity=ConformPolarity
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
source_bus_id=1
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
source_bus_irq=3
trigger=ConformTrigger
[system.intel_mp_table.base_entries11]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=0
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
interrupt_type=ExtInt
polarity=ConformPolarity
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
source_bus_id=1
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
source_bus_irq=4
trigger=ConformTrigger
[system.intel_mp_table.base_entries12]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=4
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
interrupt_type=INT
polarity=ConformPolarity
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
source_bus_id=1
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
source_bus_irq=4
trigger=ConformTrigger
[system.intel_mp_table.base_entries13]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=0
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
interrupt_type=ExtInt
polarity=ConformPolarity
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
source_bus_id=1
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
source_bus_irq=5
trigger=ConformTrigger
[system.intel_mp_table.base_entries14]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=5
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
interrupt_type=INT
polarity=ConformPolarity
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
source_bus_id=1
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
source_bus_irq=5
trigger=ConformTrigger
[system.intel_mp_table.base_entries15]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=0
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
interrupt_type=ExtInt
polarity=ConformPolarity
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
source_bus_id=1
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
source_bus_irq=6
trigger=ConformTrigger
[system.intel_mp_table.base_entries16]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=6
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
interrupt_type=INT
polarity=ConformPolarity
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
source_bus_id=1
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
source_bus_irq=6
trigger=ConformTrigger
[system.intel_mp_table.base_entries17]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=0
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
interrupt_type=ExtInt
polarity=ConformPolarity
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
source_bus_id=1
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
source_bus_irq=7
trigger=ConformTrigger
[system.intel_mp_table.base_entries18]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=7
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
interrupt_type=INT
polarity=ConformPolarity
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
source_bus_id=1
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
source_bus_irq=7
trigger=ConformTrigger
[system.intel_mp_table.base_entries19]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=0
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
interrupt_type=ExtInt
polarity=ConformPolarity
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
source_bus_id=1
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
source_bus_irq=8
trigger=ConformTrigger
[system.intel_mp_table.base_entries20]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=8
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
interrupt_type=INT
polarity=ConformPolarity
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
source_bus_id=1
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
source_bus_irq=8
trigger=ConformTrigger
[system.intel_mp_table.base_entries21]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=0
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
interrupt_type=ExtInt
polarity=ConformPolarity
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
source_bus_id=1
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
source_bus_irq=9
trigger=ConformTrigger
[system.intel_mp_table.base_entries22]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=9
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
interrupt_type=INT
polarity=ConformPolarity
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
source_bus_id=1
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
source_bus_irq=9
trigger=ConformTrigger
[system.intel_mp_table.base_entries23]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=0
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
interrupt_type=ExtInt
polarity=ConformPolarity
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
source_bus_id=1
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
source_bus_irq=10
trigger=ConformTrigger
[system.intel_mp_table.base_entries24]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=10
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
interrupt_type=INT
polarity=ConformPolarity
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
source_bus_id=1
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
source_bus_irq=10
trigger=ConformTrigger
[system.intel_mp_table.base_entries25]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=0
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
interrupt_type=ExtInt
polarity=ConformPolarity
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
source_bus_id=1
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
source_bus_irq=11
trigger=ConformTrigger
[system.intel_mp_table.base_entries26]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=11
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
interrupt_type=INT
polarity=ConformPolarity
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
source_bus_id=1
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
source_bus_irq=11
trigger=ConformTrigger
[system.intel_mp_table.base_entries27]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=0
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
interrupt_type=ExtInt
polarity=ConformPolarity
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
source_bus_id=1
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
source_bus_irq=12
trigger=ConformTrigger
[system.intel_mp_table.base_entries28]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=12
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
interrupt_type=INT
polarity=ConformPolarity
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
source_bus_id=1
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
source_bus_irq=12
trigger=ConformTrigger
[system.intel_mp_table.base_entries29]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=0
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
interrupt_type=ExtInt
polarity=ConformPolarity
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
source_bus_id=1
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
source_bus_irq=13
trigger=ConformTrigger
[system.intel_mp_table.base_entries30]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=13
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
interrupt_type=INT
polarity=ConformPolarity
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
source_bus_id=1
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
source_bus_irq=13
trigger=ConformTrigger
[system.intel_mp_table.base_entries31]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=0
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
interrupt_type=ExtInt
polarity=ConformPolarity
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
source_bus_id=1
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
source_bus_irq=14
trigger=ConformTrigger
[system.intel_mp_table.base_entries32]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=14
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
interrupt_type=INT
polarity=ConformPolarity
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
source_bus_id=1
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
source_bus_irq=14
trigger=ConformTrigger
[system.intel_mp_table.ext_entries]
type=X86IntelMPBusHierarchy
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
bus_id=1
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
parent_bus=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
subtractive_decode=true
[system.intrctrl]
type=IntrControl
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
sys=system
[system.iobus]
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
type=NoncoherentXBar
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: changes to due to recent set of patches
2015-03-09 15:39:09 +01:00
forward_latency=1
frontend_latency=2
response_latency=2
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
use_default_range=false
stats: changes to due to recent set of patches
2015-03-09 15:39:09 +01:00
width=16
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
default=system.pc.pci_host.pio
master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.iocache]
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
type=Cache
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=tags
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
addr_ranges=0:134217727
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
assoc=8
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
clusivity=mostly_incl
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
demand_mshr_reserve=1
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
forward_snoops=false
regression test: update a couple of config.ini files
2012-12-06 17:26:12 +01:00
hit_latency=50
stats: x86: update stats missed out on in preivous changeset
2015-07-06 03:26:18 +02:00
is_read_only=false
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
max_miss_count=0
mshrs=20
prefetch_on_access=false
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
prefetcher=Null
regression test: update a couple of config.ini files
2012-12-06 17:26:12 +01:00
response_latency=50
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
size=1024
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
tags=system.iocache.tags
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
tgts_per_mshr=12
write_buffers=8
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
writeback_clean=false
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
cpu_side=system.iobus.master[18]
x86 regressions: updates due to new instructions and cpuid
2013-01-15 14:43:23 +01:00
mem_side=system.membus.slave[4]
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.iocache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.clk_domain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
hit_latency=50
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
size=1024
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.membus]
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
type=CoherentXBar
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
children=badaddr_responder
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: changes to due to recent set of patches
2015-03-09 15:39:09 +01:00
forward_latency=4
frontend_latency=3
response_latency=2
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
snoop_filter=Null
stats: changes to due to recent set of patches
2015-03-09 15:39:09 +01:00
snoop_response_latency=4
regressions: updates due to changes to o3 cpu, x86 memory map
2013-03-29 20:05:36 +01:00
system=system
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
use_default_range=false
stats: changes to due to recent set of patches
2015-03-09 15:39:09 +01:00
width=16
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
default=system.membus.badaddr_responder.pio
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
master=system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.physmem.port
x86 regressions: updates due to new instructions and cpuid
2013-01-15 14:43:23 +01:00
slave=system.apicbridge.master system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master system.iocache.mem_side
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.membus.badaddr_responder]
type=IsaFake
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
fake_mem=false
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
pio_addr=0
x86 Regressions: Update stats due to register predication
2012-09-11 16:34:40 +02:00
pio_latency=100000
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
pio_size=8
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.membus.default
[system.pc]
type=Pc
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist1 i_dont_exist2 pci_host south_bridge
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
intrctrl=system.intrctrl
system=system
[system.pc.behind_pci]
type=IsaFake
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
fake_mem=false
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
pio_addr=9223372036854779128
x86 Regressions: Update stats due to register predication
2012-09-11 16:34:40 +02:00
pio_latency=100000
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
pio=system.iobus.master[12]
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.pc.com_1]
type=Uart8250
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
children=terminal
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
pio_addr=9223372036854776824
x86 Regressions: Update stats due to register predication
2012-09-11 16:34:40 +02:00
pio_latency=100000
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
platform=system.pc
system=system
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
terminal=system.pc.com_1.terminal
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
pio=system.iobus.master[13]
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
[system.pc.com_1.terminal]
type=Terminal
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
intr_control=system.intrctrl
number=0
output=true
port=3456
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.pc.fake_com_2]
type=IsaFake
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
fake_mem=false
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
pio_addr=9223372036854776568
x86 Regressions: Update stats due to register predication
2012-09-11 16:34:40 +02:00
pio_latency=100000
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
pio=system.iobus.master[14]
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.pc.fake_com_3]
type=IsaFake
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
fake_mem=false
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
pio_addr=9223372036854776808
x86 Regressions: Update stats due to register predication
2012-09-11 16:34:40 +02:00
pio_latency=100000
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
pio=system.iobus.master[15]
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.pc.fake_com_4]
type=IsaFake
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
fake_mem=false
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
pio_addr=9223372036854776552
x86 Regressions: Update stats due to register predication
2012-09-11 16:34:40 +02:00
pio_latency=100000
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
pio=system.iobus.master[16]
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.pc.fake_floppy]
type=IsaFake
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
fake_mem=false
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
pio_addr=9223372036854776818
x86 Regressions: Update stats due to register predication
2012-09-11 16:34:40 +02:00
pio_latency=100000
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
pio_size=2
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
pio=system.iobus.master[17]
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
x86: Update stats for the new Linux delay port.
2014-11-22 02:22:19 +01:00
[system.pc.i_dont_exist1]
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
type=IsaFake
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
fake_mem=false
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
pio_addr=9223372036854775936
x86 Regressions: Update stats due to register predication
2012-09-11 16:34:40 +02:00
pio_latency=100000
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
pio_size=1
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
pio=system.iobus.master[10]
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
x86: Update stats for the new Linux delay port.
2014-11-22 02:22:19 +01:00
[system.pc.i_dont_exist2]
type=IsaFake
clk_domain=system.clk_domain
eventq_index=0
fake_mem=false
pio_addr=9223372036854776045
pio_latency=100000
pio_size=1
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
pio=system.iobus.master[11]
x86: Update stats for the new Linux delay port.
2014-11-22 02:22:19 +01:00
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
[system.pc.pci_host]
type=GenericPciHost
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
conf_base=13835058055282163712
conf_device_bits=8
conf_size=16777216
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
pci_dma_base=0
pci_mem_base=0
pci_pio_base=9223372036854775808
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
platform=system.pc
system=system
pio=system.iobus.default
[system.pc.south_bridge]
type=SouthBridge
children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker
cmos=system.pc.south_bridge.cmos
dma1=system.pc.south_bridge.dma1
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
io_apic=system.pc.south_bridge.io_apic
keyboard=system.pc.south_bridge.keyboard
pic1=system.pc.south_bridge.pic1
pic2=system.pc.south_bridge.pic2
pit=system.pc.south_bridge.pit
platform=system.pc
speaker=system.pc.south_bridge.speaker
[system.pc.south_bridge.cmos]
type=Cmos
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
children=int_pin
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
int_pin=system.pc.south_bridge.cmos.int_pin
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
pio_addr=9223372036854775920
x86 Regressions: Update stats due to register predication
2012-09-11 16:34:40 +02:00
pio_latency=100000
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
system=system
time=Sun Jan 1 00:00:00 2012
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
pio=system.iobus.master[1]
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
[system.pc.south_bridge.cmos.int_pin]
type=X86IntSourcePin
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.pc.south_bridge.dma1]
type=I8237
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
pio_addr=9223372036854775808
x86 Regressions: Update stats due to register predication
2012-09-11 16:34:40 +02:00
pio_latency=100000
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
system=system
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
pio=system.iobus.master[2]
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.pc.south_bridge.ide]
type=IdeController
children=disks0 disks1
BAR0=496
BAR0LegacyIO=true
BAR0Size=8
BAR1=1012
BAR1LegacyIO=true
BAR1Size=3
BAR2=368
BAR2LegacyIO=true
BAR2Size=8
BAR3=884
BAR3LegacyIO=true
BAR3Size=3
BAR4=1
BAR4LegacyIO=false
BAR4Size=16
BAR5=1
BAR5LegacyIO=false
BAR5Size=0
BIST=0
CacheLineSize=0
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
CapabilityPtr=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
CardbusCIS=0
ClassCode=1
Command=0
DeviceID=28945
ExpansionROM=0
HeaderType=0
InterruptLine=14
InterruptPin=1
LatencyTimer=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
LegacyIOBase=9223372036854775808
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
MSICAPMsgAddr=0
MSICAPMsgCtrl=0
MSICAPMsgData=0
MSICAPMsgUpperAddr=0
MSICAPNextCapability=0
MSICAPPendingBits=0
MSIXCAPBaseOffset=0
MSIXCAPCapId=0
MSIXCAPNextCapability=0
MSIXMsgCtrl=0
MSIXPbaOffset=0
MSIXTableOffset=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
MaximumLatency=0
MinimumGrant=0
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
PMCAPBaseOffset=0
PMCAPCapId=0
PMCAPCapabilities=0
PMCAPCtrlStatus=0
PMCAPNextCapability=0
PXCAPBaseOffset=0
PXCAPCapId=0
PXCAPCapabilities=0
PXCAPDevCap2=0
PXCAPDevCapabilities=0
PXCAPDevCtrl=0
PXCAPDevCtrl2=0
PXCAPDevStatus=0
PXCAPLinkCap=0
PXCAPLinkCtrl=0
PXCAPLinkStatus=0
PXCAPNextCapability=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
ProgIF=128
Revision=0
Status=640
SubClassCode=1
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
config_latency=20000
ctrl_offset=0
disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
host=system.pc.pci_host
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
io_shift=0
pci_bus=0
pci_dev=4
pci_func=0
x86 Regressions: Update stats due to register predication
2012-09-11 16:34:40 +02:00
pio_latency=30000
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
system=system
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
dma=system.iobus.slave[1]
pio=system.iobus.master[3]
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.pc.south_bridge.ide.disks0]
type=IdeDisk
children=image
delay=1000000
driveID=master
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
image=system.pc.south_bridge.ide.disks0.image
[system.pc.south_bridge.ide.disks0.image]
type=CowDiskImage
children=child
child=system.pc.south_bridge.ide.disks0.image.child
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
image_file=
read_only=false
table_size=65536
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: bump stats to reflect ruby tester changes
2015-12-12 23:27:38 +01:00
image_file=/dist/m5/system/disks/linux-x86.img
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
read_only=true
[system.pc.south_bridge.ide.disks1]
type=IdeDisk
children=image
delay=1000000
driveID=master
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
image=system.pc.south_bridge.ide.disks1.image
[system.pc.south_bridge.ide.disks1.image]
type=CowDiskImage
children=child
child=system.pc.south_bridge.ide.disks1.image.child
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
image_file=
read_only=false
table_size=65536
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: bump stats to reflect ruby tester changes
2015-12-12 23:27:38 +01:00
image_file=/dist/m5/system/disks/linux-bigswap2.img
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
read_only=true
[system.pc.south_bridge.int_lines0]
type=X86IntLine
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
children=sink
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
sink=system.pc.south_bridge.int_lines0.sink
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
source=system.pc.south_bridge.pic1.output
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.pc.south_bridge.int_lines0.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.io_apic
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
number=0
[system.pc.south_bridge.int_lines1]
type=X86IntLine
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
children=sink
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
sink=system.pc.south_bridge.int_lines1.sink
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
source=system.pc.south_bridge.pic2.output
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.pc.south_bridge.int_lines1.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.pic1
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
number=2
[system.pc.south_bridge.int_lines2]
type=X86IntLine
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
children=sink
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
sink=system.pc.south_bridge.int_lines2.sink
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
source=system.pc.south_bridge.cmos.int_pin
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.pc.south_bridge.int_lines2.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.pic2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
number=0
[system.pc.south_bridge.int_lines3]
type=X86IntLine
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
children=sink
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
sink=system.pc.south_bridge.int_lines3.sink
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
source=system.pc.south_bridge.pit.int_pin
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.pc.south_bridge.int_lines3.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.pic1
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
number=0
[system.pc.south_bridge.int_lines4]
type=X86IntLine
children=sink
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
sink=system.pc.south_bridge.int_lines4.sink
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
source=system.pc.south_bridge.pit.int_pin
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.pc.south_bridge.int_lines4.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.io_apic
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
number=2
[system.pc.south_bridge.int_lines5]
type=X86IntLine
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
children=sink
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
sink=system.pc.south_bridge.int_lines5.sink
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
source=system.pc.south_bridge.keyboard.keyboard_int_pin
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.pc.south_bridge.int_lines5.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.io_apic
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
number=1
[system.pc.south_bridge.int_lines6]
type=X86IntLine
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
children=sink
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
sink=system.pc.south_bridge.int_lines6.sink
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
source=system.pc.south_bridge.keyboard.mouse_int_pin
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.pc.south_bridge.int_lines6.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.io_apic
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
number=12
[system.pc.south_bridge.io_apic]
type=I82094AA
apic_id=1
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
external_int_pic=system.pc.south_bridge.pic1
int_latency=1000
pio_addr=4273995776
x86 Regressions: Update stats due to register predication
2012-09-11 16:34:40 +02:00
pio_latency=100000
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
system=system
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
int_master=system.iobus.slave[2]
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
pio=system.iobus.master[9]
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.pc.south_bridge.keyboard]
type=I8042
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
children=keyboard_int_pin mouse_int_pin
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
command_port=9223372036854775908
data_port=9223372036854775904
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
pio_addr=0
x86 Regressions: Update stats due to register predication
2012-09-11 16:34:40 +02:00
pio_latency=100000
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
system=system
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
pio=system.iobus.master[4]
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
[system.pc.south_bridge.keyboard.keyboard_int_pin]
type=X86IntSourcePin
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
[system.pc.south_bridge.keyboard.mouse_int_pin]
type=X86IntSourcePin
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.pc.south_bridge.pic1]
type=I8259
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
children=output
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
mode=I8259Master
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
output=system.pc.south_bridge.pic1.output
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
pio_addr=9223372036854775840
x86 Regressions: Update stats due to register predication
2012-09-11 16:34:40 +02:00
pio_latency=100000
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
slave=system.pc.south_bridge.pic2
system=system
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
pio=system.iobus.master[5]
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
[system.pc.south_bridge.pic1.output]
type=X86IntSourcePin
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.pc.south_bridge.pic2]
type=I8259
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
children=output
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
mode=I8259Slave
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
output=system.pc.south_bridge.pic2.output
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
pio_addr=9223372036854775968
x86 Regressions: Update stats due to register predication
2012-09-11 16:34:40 +02:00
pio_latency=100000
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
slave=Null
system=system
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
pio=system.iobus.master[6]
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
[system.pc.south_bridge.pic2.output]
type=X86IntSourcePin
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.pc.south_bridge.pit]
type=I8254
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
children=int_pin
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
int_pin=system.pc.south_bridge.pit.int_pin
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
pio_addr=9223372036854775872
x86 Regressions: Update stats due to register predication
2012-09-11 16:34:40 +02:00
pio_latency=100000
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
system=system
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
pio=system.iobus.master[7]
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
[system.pc.south_bridge.pit.int_pin]
type=X86IntSourcePin
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.pc.south_bridge.speaker]
type=PcSpeaker
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
i8254=system.pc.south_bridge.pit
pio_addr=9223372036854775905
x86 Regressions: Update stats due to register predication
2012-09-11 16:34:40 +02:00
pio_latency=100000
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
system=system
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
pio=system.iobus.master[8]
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.physmem]
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
type=DRAMCtrl
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
IDD0=0.075000
IDD02=0.000000
IDD2N=0.050000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
IDD2P1=0.000000
IDD2P12=0.000000
IDD3N=0.057000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
IDD3P1=0.000000
IDD3P12=0.000000
IDD4R=0.187000
IDD4R2=0.000000
IDD4W=0.165000
IDD4W2=0.000000
IDD5=0.220000
IDD52=0.000000
IDD6=0.000000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
regressions: updates due to changes to o3 cpu, x86 memory map
2013-03-29 20:05:36 +01:00
activation_limit=4
stats: changes to due to recent set of patches
2015-03-09 15:39:09 +01:00
addr_mapping=RoRaBaCoCh
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
bank_groups_per_rank=0
regression test: update a couple of config.ini files
2012-12-06 17:26:12 +01:00
banks_per_rank=8
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
burst_length=8
regressions: updates due to changes to o3 cpu, x86 memory map
2013-03-29 20:05:36 +01:00
channels=1
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
device_size=536870912
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
devices_per_rank=8
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
dll=true
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
in_addr_map=true
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
max_accesses_per_row=16
regressions: updates due to changes to o3 cpu, x86 memory map
2013-03-29 20:05:36 +01:00
mem_sched_policy=frfcfs
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
min_writes_per_switch=16
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
null=false
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
page_policy=open_adaptive
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
range=0:134217727
regression test: update a couple of config.ini files
2012-12-06 17:26:12 +01:00
ranks_per_channel=2
read_buffer_size=32
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
static_backend_latency=10000
static_frontend_latency=10000
regressions: updates due to changes to o3 cpu, x86 memory map
2013-03-29 20:05:36 +01:00
tBURST=5000
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
tCCD_L=0
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
tCK=1250
regressions: updates due to changes to o3 cpu, x86 memory map
2013-03-29 20:05:36 +01:00
tCL=13750
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
tCS=2500
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
tRAS=35000
regressions: updates due to changes to o3 cpu, x86 memory map
2013-03-29 20:05:36 +01:00
tRCD=13750
regression test: update a couple of config.ini files
2012-12-06 17:26:12 +01:00
tREFI=7800000
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
tRFC=260000
regressions: updates due to changes to o3 cpu, x86 memory map
2013-03-29 20:05:36 +01:00
tRP=13750
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
tRRD=6000
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
tRRD_L=0
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
tRTP=7500
tRTW=2500
tWR=15000
regressions: updates due to changes to o3 cpu, x86 memory map
2013-03-29 20:05:36 +01:00
tWTR=7500
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
tXAW=30000
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
tXP=0
tXPDLL=0
tXS=0
tXSDLL=0
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
port=system.membus.master[3]
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
[system.smbios_table]
type=X86SMBiosSMBiosTable
children=structures
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
major_version=2
minor_version=5
structures=system.smbios_table.structures
[system.smbios_table.structures]
type=X86SMBiosBiosInformation
characteristic_ext_bytes=
characteristics=
emb_cont_firmware_major=0
emb_cont_firmware_minor=0
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
major=0
minor=0
release_date=06/08/2008
rom_size=0
starting_addr_segment=0
vendor=
version=
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.voltage_domain]
type=VoltageDomain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
voltage=1.000000
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