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stats: x86: update stats missed out on in preivous changeset

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This commit is contained in:
Nilay Vaish 2015-07-05 20:26:18 -05:00
parent 9954eb74df
commit 381e9191dd
22 changed files with 1136 additions and 1139 deletions
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92
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
View file

@ -211,7 +211,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
is_read_only=false
max_miss_count=0
mshrs=4
prefetch_on_access=false
@ -222,7 +222,6 @@ size=32768
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@ -260,9 +259,9 @@ assoc=2
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
forward_snoops=false
hit_latency=2
is_top_level=true
is_read_only=false
max_miss_count=0
mshrs=10
prefetch_on_access=false
@ -273,7 +272,6 @@ size=1024
system=system
tags=system.cpu.dtb_walker_cache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.dtb.walker.port
mem_side=system.cpu.toL2Bus.slave[3]
@ -304,9 +302,9 @@ opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=IntAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList1]
type=FUDesc
@ -318,16 +316,16 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=IntMult
opLat=3
pipelined=true
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
issueLat=19
opClass=IntDiv
opLat=20
opLat=1
pipelined=false
[system.cpu.fuPool.FUList2]
type=FUDesc
@ -339,23 +337,23 @@ opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 syste
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatAdd
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatCmp
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatCvt
opLat=2
pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
@ -367,23 +365,23 @@ opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 syste
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatMult
opLat=4
pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
issueLat=12
opClass=FloatDiv
opLat=12
pipelined=false
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
eventq_index=0
issueLat=24
opClass=FloatSqrt
opLat=24
pipelined=false
[system.cpu.fuPool.FUList4]
type=FUDesc
@ -395,9 +393,9 @@ opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5]
type=FUDesc
@ -409,142 +407,142 @@ opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 sys
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAdd
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAddAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCmp
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCvt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMisc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMult
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMultAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShift
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShiftAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdSqrt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAdd
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCmp
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCvt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatDiv
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMisc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMult
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatSqrt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList6]
type=FUDesc
@ -556,9 +554,9 @@ opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7]
type=FUDesc
@ -570,16 +568,16 @@ opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList8]
type=FUDesc
@ -591,9 +589,9 @@ opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
eventq_index=0
issueLat=3
opClass=IprAccess
opLat=3
pipelined=false
[system.cpu.icache]
type=BaseCache
@ -605,7 +603,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
is_read_only=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
@ -616,7 +614,6 @@ size=32768
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@ -670,9 +667,9 @@ assoc=2
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
forward_snoops=false
hit_latency=2
is_top_level=true
is_read_only=false
max_miss_count=0
mshrs=10
prefetch_on_access=false
@ -683,7 +680,6 @@ size=1024
system=system
tags=system.cpu.itb_walker_cache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.itb.walker.port
mem_side=system.cpu.toL2Bus.slave[2]
@ -708,7 +704,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_top_level=false
is_read_only=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
@ -719,7 +715,6 @@ size=4194304
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[2]
@ -1216,7 +1211,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
is_top_level=true
is_read_only=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
@ -1227,7 +1222,6 @@ size=1024
system=system
tags=system.iocache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[19]
mem_side=system.membus.slave[4]

4
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
View file

@ -29,7 +29,7 @@ Built 1 zonelists. Total pages: 30610
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
Initializing CPU#0
PID hash table entries: 512 (order: 9, 4096 bytes)
time.c: Detected 2000.006 MHz processor.
time.c: Detected 2000.000 MHz processor.
Console: colour dummy device 80x25
console handover: boot [earlyser0] -> real [ttyS0]
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
@ -46,7 +46,7 @@ ACPI: Core revision 20070126
ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
ACPI: Unable to load the System Description Tables
Using local APIC timer interrupts.
result 7812552
result 7812528
Detected 7.812 MHz APIC timer.
NET: Registered protocol family 16
PCI: Using configuration type 1

82
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
View file

@ -143,7 +143,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
is_read_only=false
max_miss_count=0
mshrs=4
prefetch_on_access=false
@ -154,7 +154,6 @@ size=32768
system=system
tags=system.cpu0.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
mem_side=system.toL2Bus.slave[1]
@ -194,7 +193,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
is_read_only=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
@ -205,7 +204,6 @@ size=32768
system=system
tags=system.cpu0.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
mem_side=system.toL2Bus.slave[0]
@ -455,9 +453,9 @@ opList=system.cpu2.fuPool.FUList0.opList
[system.cpu2.fuPool.FUList0.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=IntAlu
opLat=1
pipelined=true
[system.cpu2.fuPool.FUList1]
type=FUDesc
@ -469,16 +467,16 @@ opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1
[system.cpu2.fuPool.FUList1.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=IntMult
opLat=3
pipelined=true
[system.cpu2.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
issueLat=19
opClass=IntDiv
opLat=20
opLat=1
pipelined=false
[system.cpu2.fuPool.FUList2]
type=FUDesc
@ -490,23 +488,23 @@ opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 sys
[system.cpu2.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatAdd
opLat=2
pipelined=true
[system.cpu2.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatCmp
opLat=2
pipelined=true
[system.cpu2.fuPool.FUList2.opList2]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatCvt
opLat=2
pipelined=true
[system.cpu2.fuPool.FUList3]
type=FUDesc
@ -518,23 +516,23 @@ opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 sys
[system.cpu2.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatMult
opLat=4
pipelined=true
[system.cpu2.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
issueLat=12
opClass=FloatDiv
opLat=12
pipelined=false
[system.cpu2.fuPool.FUList3.opList2]
type=OpDesc
eventq_index=0
issueLat=24
opClass=FloatSqrt
opLat=24
pipelined=false
[system.cpu2.fuPool.FUList4]
type=FUDesc
@ -546,9 +544,9 @@ opList=system.cpu2.fuPool.FUList4.opList
[system.cpu2.fuPool.FUList4.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
pipelined=true
[system.cpu2.fuPool.FUList5]
type=FUDesc
@ -560,142 +558,142 @@ opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 s
[system.cpu2.fuPool.FUList5.opList00]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAdd
opLat=1
pipelined=true
[system.cpu2.fuPool.FUList5.opList01]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAddAcc
opLat=1
pipelined=true
[system.cpu2.fuPool.FUList5.opList02]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAlu
opLat=1
pipelined=true
[system.cpu2.fuPool.FUList5.opList03]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCmp
opLat=1
pipelined=true
[system.cpu2.fuPool.FUList5.opList04]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCvt
opLat=1
pipelined=true
[system.cpu2.fuPool.FUList5.opList05]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMisc
opLat=1
pipelined=true
[system.cpu2.fuPool.FUList5.opList06]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMult
opLat=1
pipelined=true
[system.cpu2.fuPool.FUList5.opList07]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMultAcc
opLat=1
pipelined=true
[system.cpu2.fuPool.FUList5.opList08]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShift
opLat=1
pipelined=true
[system.cpu2.fuPool.FUList5.opList09]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShiftAcc
opLat=1
pipelined=true
[system.cpu2.fuPool.FUList5.opList10]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdSqrt
opLat=1
pipelined=true
[system.cpu2.fuPool.FUList5.opList11]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAdd
opLat=1
pipelined=true
[system.cpu2.fuPool.FUList5.opList12]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAlu
opLat=1
pipelined=true
[system.cpu2.fuPool.FUList5.opList13]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCmp
opLat=1
pipelined=true
[system.cpu2.fuPool.FUList5.opList14]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCvt
opLat=1
pipelined=true
[system.cpu2.fuPool.FUList5.opList15]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatDiv
opLat=1
pipelined=true
[system.cpu2.fuPool.FUList5.opList16]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMisc
opLat=1
pipelined=true
[system.cpu2.fuPool.FUList5.opList17]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMult
opLat=1
pipelined=true
[system.cpu2.fuPool.FUList5.opList18]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
pipelined=true
[system.cpu2.fuPool.FUList5.opList19]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatSqrt
opLat=1
pipelined=true
[system.cpu2.fuPool.FUList6]
type=FUDesc
@ -707,9 +705,9 @@ opList=system.cpu2.fuPool.FUList6.opList
[system.cpu2.fuPool.FUList6.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu2.fuPool.FUList7]
type=FUDesc
@ -721,16 +719,16 @@ opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
[system.cpu2.fuPool.FUList7.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
pipelined=true
[system.cpu2.fuPool.FUList7.opList1]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu2.fuPool.FUList8]
type=FUDesc
@ -742,9 +740,9 @@ opList=system.cpu2.fuPool.FUList8.opList
[system.cpu2.fuPool.FUList8.opList]
type=OpDesc
eventq_index=0
issueLat=3
opClass=IprAccess
opLat=3
pipelined=false
[system.cpu2.isa]
type=X86ISA
@ -1231,7 +1229,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
is_top_level=true
is_read_only=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
@ -1242,7 +1240,6 @@ size=1024
system=system
tags=system.iocache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[19]
mem_side=system.membus.slave[4]
@ -1267,7 +1264,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_top_level=false
is_read_only=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
@ -1278,7 +1275,6 @@ size=4194304
system=system
tags=system.l2c.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[2]

42
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr
View file

@ -19,24 +19,28 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: Bank is already active!
Command: 0, Timestamp: 6448, Bank: 0
WARNING: Bank is already active!
Command: 0, Timestamp: 11155, Bank: 3
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: Bank is already active!
Command: 0, Timestamp: 8139, Bank: 7
Command: 0, Timestamp: 6448, Bank: 6
WARNING: Bank is already active!
Command: 0, Timestamp: 7107, Bank: 0
WARNING: Bank is already active!
Command: 0, Timestamp: 12359, Bank: 3
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: Bank is already active!
Command: 0, Timestamp: 7686, Bank: 3
Command: 0, Timestamp: 10918, Bank: 5
WARNING: Bank is already active!
Command: 0, Timestamp: 7932, Bank: 1
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: Bank is already active!
Command: 0, Timestamp: 6831, Bank: 2
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
@ -50,11 +54,9 @@ Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: Bank is already active!
Command: 0, Timestamp: 10283, Bank: 3
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
Command: 0, Timestamp: 6838, Bank: 1
WARNING: Bank is already active!
Command: 0, Timestamp: 12183, Bank: 4
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
@ -80,25 +82,23 @@ Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
warn: Tried to clear PCI interrupt 14
WARNING: Bank is already active!
Command: 0, Timestamp: 7809, Bank: 2
WARNING: Bank is already active!
Command: 0, Timestamp: 12253, Bank: 7
WARNING: Bank is already active!
Command: 0, Timestamp: 7886, Bank: 4
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
warn: Unknown mouse command 0xe1.
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
warn: instruction 'wbinvd' unimplemented
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: Bank is already active!
Command: 0, Timestamp: 6448, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: Bank is not active!
Command: 1, Timestamp: 1481, Bank: 4
WARNING: Bank is not active!
Command: 1, Timestamp: 2142, Bank: 4
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0

4
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal
View file

@ -29,7 +29,7 @@ Built 1 zonelists. Total pages: 30610
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
Initializing CPU#0
PID hash table entries: 512 (order: 9, 4096 bytes)
time.c: Detected 2000.007 MHz processor.
time.c: Detected 2000.005 MHz processor.
Console: colour dummy device 80x25
console handover: boot [earlyser0] -> real [ttyS0]
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
@ -46,7 +46,7 @@ ACPI: Core revision 20070126
ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
ACPI: Unable to load the System Description Tables
Using local APIC timer interrupts.
result 7812546
result 7812519
Detected 7.812 MHz APIC timer.
NET: Registered protocol family 16
PCI: Using configuration type 1

79
tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
View file

@ -165,7 +165,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
is_read_only=false
max_miss_count=0
mshrs=4
prefetch_on_access=false
@ -176,7 +176,6 @@ size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@ -222,9 +221,9 @@ opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=IntAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList1]
type=FUDesc
@ -236,16 +235,16 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=IntMult
opLat=3
pipelined=true
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
issueLat=19
opClass=IntDiv
opLat=20
opLat=1
pipelined=false
[system.cpu.fuPool.FUList2]
type=FUDesc
@ -257,23 +256,23 @@ opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 syste
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatAdd
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatCmp
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatCvt
opLat=2
pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
@ -285,23 +284,23 @@ opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 syste
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatMult
opLat=4
pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
issueLat=12
opClass=FloatDiv
opLat=12
pipelined=false
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
eventq_index=0
issueLat=24
opClass=FloatSqrt
opLat=24
pipelined=false
[system.cpu.fuPool.FUList4]
type=FUDesc
@ -313,9 +312,9 @@ opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5]
type=FUDesc
@ -327,142 +326,142 @@ opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 sys
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAdd
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAddAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCmp
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCvt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMisc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMult
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMultAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShift
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShiftAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdSqrt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAdd
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCmp
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCvt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatDiv
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMisc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMult
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatSqrt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList6]
type=FUDesc
@ -474,9 +473,9 @@ opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7]
type=FUDesc
@ -488,16 +487,16 @@ opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList8]
type=FUDesc
@ -509,9 +508,9 @@ opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
eventq_index=0
issueLat=3
opClass=IprAccess
opLat=3
pipelined=false
[system.cpu.icache]
type=BaseCache
@ -523,7 +522,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
is_read_only=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
@ -534,7 +533,6 @@ size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@ -590,7 +588,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_top_level=false
is_read_only=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
@ -601,7 +599,6 @@ size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]

22
tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
View file

@ -23,6 +23,7 @@ load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
@ -92,7 +93,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
is_read_only=false
max_miss_count=0
mshrs=4
prefetch_on_access=false
@ -103,7 +104,6 @@ size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@ -143,7 +143,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
is_read_only=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
@ -154,7 +154,6 @@ size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@ -210,7 +209,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_top_level=false
is_read_only=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
@ -221,7 +220,6 @@ size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
@ -240,8 +238,11 @@ size=2097152
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
forward_latency=0
frontend_latency=1
response_latency=1
snoop_filter=Null
snoop_response_latency=1
system=system
use_default_range=false
width=32
@ -295,11 +296,14 @@ transition_latency=100000000
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
forward_latency=4
frontend_latency=3
response_latency=2
snoop_filter=Null
snoop_response_latency=4
system=system
use_default_range=false
width=8
width=16
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master

79
tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
View file

@ -165,7 +165,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
is_read_only=false
max_miss_count=0
mshrs=4
prefetch_on_access=false
@ -176,7 +176,6 @@ size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@ -222,9 +221,9 @@ opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=IntAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList1]
type=FUDesc
@ -236,16 +235,16 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=IntMult
opLat=3
pipelined=true
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
issueLat=19
opClass=IntDiv
opLat=20
opLat=1
pipelined=false
[system.cpu.fuPool.FUList2]
type=FUDesc
@ -257,23 +256,23 @@ opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 syste
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatAdd
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatCmp
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatCvt
opLat=2
pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
@ -285,23 +284,23 @@ opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 syste
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatMult
opLat=4
pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
issueLat=12
opClass=FloatDiv
opLat=12
pipelined=false
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
eventq_index=0
issueLat=24
opClass=FloatSqrt
opLat=24
pipelined=false
[system.cpu.fuPool.FUList4]
type=FUDesc
@ -313,9 +312,9 @@ opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5]
type=FUDesc
@ -327,142 +326,142 @@ opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 sys
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAdd
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAddAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCmp
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCvt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMisc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMult
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMultAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShift
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShiftAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdSqrt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAdd
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCmp
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCvt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatDiv
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMisc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMult
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatSqrt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList6]
type=FUDesc
@ -474,9 +473,9 @@ opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7]
type=FUDesc
@ -488,16 +487,16 @@ opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList8]
type=FUDesc
@ -509,9 +508,9 @@ opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
eventq_index=0
issueLat=3
opClass=IprAccess
opLat=3
pipelined=false
[system.cpu.icache]
type=BaseCache
@ -523,7 +522,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
is_read_only=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
@ -534,7 +533,6 @@ size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@ -590,7 +588,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_top_level=false
is_read_only=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
@ -601,7 +599,6 @@ size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]

36
tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
View file

@ -1,17 +1,19 @@
Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simout
Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Apr 22 2015 08:10:29
gem5 started Apr 22 2015 09:35:25
gem5 executing on phenom
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
gem5 compiled Jul 5 2015 17:24:59
gem5 started Jul 5 2015 17:25:16
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Reading the dictionary files: *******info: Increasing stack size by one page.
**info: Increasing stack size by one page.
**************************************info: Increasing stack size by one page.
Reading the dictionary files: *********info: Increasing stack size by one page.
info: Increasing stack size by one page.
**********************************info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
@ -23,7 +25,7 @@ info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
**
******
58924 words stored in 3784810 bytes
@ -35,16 +37,16 @@ Processing sentences in batch mode
Echoing of input sentence turned on.
* as had expected the party to be a success , it was a success
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
* do you know where John 's
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
* how fast the program is it
* I am wondering whether to invite to the party
* I gave him for his birthday it
@ -89,4 +91,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 455715234500 because target called exit()
Exiting @ tick 417250627500 because target called exit()

1520
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

8
tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
View file

@ -23,6 +23,7 @@ load_offset=0
mem_mode=atomic
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
@ -179,11 +180,14 @@ transition_latency=100000000
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
forward_latency=4
frontend_latency=3
response_latency=2
snoop_filter=Null
snoop_response_latency=4
system=system
use_default_range=false
width=8
width=16
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master

22
tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
View file

@ -23,6 +23,7 @@ load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
@ -92,7 +93,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
is_read_only=false
max_miss_count=0
mshrs=4
prefetch_on_access=false
@ -103,7 +104,6 @@ size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@ -143,7 +143,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
is_read_only=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
@ -154,7 +154,6 @@ size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@ -210,7 +209,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_top_level=false
is_read_only=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
@ -221,7 +220,6 @@ size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
@ -240,8 +238,11 @@ size=2097152
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
forward_latency=0
frontend_latency=1
response_latency=1
snoop_filter=Null
snoop_response_latency=1
system=system
use_default_range=false
width=32
@ -295,11 +296,14 @@ transition_latency=100000000
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
forward_latency=4
frontend_latency=3
response_latency=2
snoop_filter=Null
snoop_response_latency=4
system=system
use_default_range=false
width=8
width=16
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master

8
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
View file

@ -23,6 +23,7 @@ load_offset=0
mem_mode=atomic
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
@ -179,11 +180,14 @@ transition_latency=100000000
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
forward_latency=4
frontend_latency=3
response_latency=2
snoop_filter=Null
snoop_response_latency=4
system=system
use_default_range=false
width=8
width=16
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master

22
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
View file

@ -23,6 +23,7 @@ load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
@ -92,7 +93,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
is_read_only=false
max_miss_count=0
mshrs=4
prefetch_on_access=false
@ -103,7 +104,6 @@ size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@ -143,7 +143,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
is_read_only=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
@ -154,7 +154,6 @@ size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@ -210,7 +209,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_top_level=false
is_read_only=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
@ -221,7 +220,6 @@ size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
@ -240,8 +238,11 @@ size=2097152
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
forward_latency=0
frontend_latency=1
response_latency=1
snoop_filter=Null
snoop_response_latency=1
system=system
use_default_range=false
width=32
@ -295,11 +296,14 @@ transition_latency=100000000
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
forward_latency=4
frontend_latency=3
response_latency=2
snoop_filter=Null
snoop_response_latency=4
system=system
use_default_range=false
width=8
width=16
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master

79
tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
View file

@ -165,7 +165,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
is_read_only=false
max_miss_count=0
mshrs=4
prefetch_on_access=false
@ -176,7 +176,6 @@ size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@ -222,9 +221,9 @@ opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=IntAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList1]
type=FUDesc
@ -236,16 +235,16 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=IntMult
opLat=3
pipelined=true
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
issueLat=19
opClass=IntDiv
opLat=20
opLat=1
pipelined=false
[system.cpu.fuPool.FUList2]
type=FUDesc
@ -257,23 +256,23 @@ opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 syste
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatAdd
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatCmp
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatCvt
opLat=2
pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
@ -285,23 +284,23 @@ opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 syste
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatMult
opLat=4
pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
issueLat=12
opClass=FloatDiv
opLat=12
pipelined=false
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
eventq_index=0
issueLat=24
opClass=FloatSqrt
opLat=24
pipelined=false
[system.cpu.fuPool.FUList4]
type=FUDesc
@ -313,9 +312,9 @@ opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5]
type=FUDesc
@ -327,142 +326,142 @@ opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 sys
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAdd
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAddAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCmp
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCvt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMisc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMult
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMultAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShift
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShiftAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdSqrt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAdd
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCmp
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCvt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatDiv
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMisc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMult
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatSqrt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList6]
type=FUDesc
@ -474,9 +473,9 @@ opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7]
type=FUDesc
@ -488,16 +487,16 @@ opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList8]
type=FUDesc
@ -509,9 +508,9 @@ opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
eventq_index=0
issueLat=3
opClass=IprAccess
opLat=3
pipelined=false
[system.cpu.icache]
type=BaseCache
@ -523,7 +522,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
is_read_only=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
@ -534,7 +533,6 @@ size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@ -590,7 +588,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_top_level=false
is_read_only=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
@ -601,7 +599,6 @@ size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]

22
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
View file

@ -143,7 +143,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
is_read_only=false
max_miss_count=0
mshrs=4
prefetch_on_access=false
@ -154,7 +154,6 @@ size=32768
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@ -192,9 +191,9 @@ assoc=2
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
forward_snoops=false
hit_latency=2
is_top_level=true
is_read_only=false
max_miss_count=0
mshrs=10
prefetch_on_access=false
@ -205,7 +204,6 @@ size=1024
system=system
tags=system.cpu.dtb_walker_cache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.dtb.walker.port
mem_side=system.cpu.toL2Bus.slave[3]
@ -230,7 +228,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
is_read_only=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
@ -241,7 +239,6 @@ size=32768
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@ -295,9 +292,9 @@ assoc=2
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
forward_snoops=false
hit_latency=2
is_top_level=true
is_read_only=false
max_miss_count=0
mshrs=10
prefetch_on_access=false
@ -308,7 +305,6 @@ size=1024
system=system
tags=system.cpu.itb_walker_cache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.itb.walker.port
mem_side=system.cpu.toL2Bus.slave[2]
@ -333,7 +329,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_top_level=false
is_read_only=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
@ -344,7 +340,6 @@ size=4194304
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[2]
@ -841,7 +836,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
is_top_level=true
is_read_only=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
@ -852,7 +847,6 @@ size=1024
system=system
tags=system.iocache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[19]
mem_side=system.membus.slave[4]

22
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
View file

@ -139,7 +139,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
is_read_only=false
max_miss_count=0
mshrs=4
prefetch_on_access=false
@ -150,7 +150,6 @@ size=32768
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@ -188,9 +187,9 @@ assoc=2
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
forward_snoops=false
hit_latency=2
is_top_level=true
is_read_only=false
max_miss_count=0
mshrs=10
prefetch_on_access=false
@ -201,7 +200,6 @@ size=1024
system=system
tags=system.cpu.dtb_walker_cache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.dtb.walker.port
mem_side=system.cpu.toL2Bus.slave[3]
@ -226,7 +224,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
is_read_only=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
@ -237,7 +235,6 @@ size=32768
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@ -291,9 +288,9 @@ assoc=2
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
forward_snoops=false
hit_latency=2
is_top_level=true
is_read_only=false
max_miss_count=0
mshrs=10
prefetch_on_access=false
@ -304,7 +301,6 @@ size=1024
system=system
tags=system.cpu.itb_walker_cache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.itb.walker.port
mem_side=system.cpu.toL2Bus.slave[2]
@ -329,7 +325,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_top_level=false
is_read_only=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
@ -340,7 +336,6 @@ size=4194304
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[2]
@ -837,7 +832,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
is_top_level=true
is_read_only=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
@ -848,7 +843,6 @@ size=1024
system=system
tags=system.iocache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[19]
mem_side=system.membus.slave[4]

79
tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
View file

@ -165,7 +165,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
is_read_only=false
max_miss_count=0
mshrs=4
prefetch_on_access=false
@ -176,7 +176,6 @@ size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@ -222,9 +221,9 @@ opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=IntAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList1]
type=FUDesc
@ -236,16 +235,16 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=IntMult
opLat=3
pipelined=true
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
issueLat=19
opClass=IntDiv
opLat=20
opLat=1
pipelined=false
[system.cpu.fuPool.FUList2]
type=FUDesc
@ -257,23 +256,23 @@ opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 syste
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatAdd
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatCmp
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatCvt
opLat=2
pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
@ -285,23 +284,23 @@ opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 syste
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatMult
opLat=4
pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
issueLat=12
opClass=FloatDiv
opLat=12
pipelined=false
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
eventq_index=0
issueLat=24
opClass=FloatSqrt
opLat=24
pipelined=false
[system.cpu.fuPool.FUList4]
type=FUDesc
@ -313,9 +312,9 @@ opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5]
type=FUDesc
@ -327,142 +326,142 @@ opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 sys
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAdd
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAddAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCmp
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCvt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMisc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMult
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMultAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShift
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShiftAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdSqrt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAdd
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCmp
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCvt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatDiv
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMisc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMult
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatSqrt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList6]
type=FUDesc
@ -474,9 +473,9 @@ opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7]
type=FUDesc
@ -488,16 +487,16 @@ opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList8]
type=FUDesc
@ -509,9 +508,9 @@ opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
eventq_index=0
issueLat=3
opClass=IprAccess
opLat=3
pipelined=false
[system.cpu.icache]
type=BaseCache
@ -523,7 +522,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
is_read_only=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
@ -534,7 +533,6 @@ size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@ -590,7 +588,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_top_level=false
is_read_only=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
@ -601,7 +599,6 @@ size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]

9
tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
View file

@ -93,7 +93,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
is_read_only=false
max_miss_count=0
mshrs=4
prefetch_on_access=false
@ -104,7 +104,6 @@ size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@ -144,7 +143,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
is_read_only=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
@ -155,7 +154,6 @@ size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@ -211,7 +209,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_top_level=false
is_read_only=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
@ -222,7 +220,6 @@ size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]

10
tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
View file

@ -23,6 +23,7 @@ load_offset=0
mem_mode=atomic
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
@ -139,7 +140,7 @@ eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic
cwd=build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic
drivers=
egid=100
env=
@ -179,11 +180,14 @@ transition_latency=100000000
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
forward_latency=4
frontend_latency=3
response_latency=2
snoop_filter=Null
snoop_response_latency=4
system=system
use_default_range=false
width=8
width=16
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master

10
tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
View file

@ -23,6 +23,7 @@ load_offset=0
mem_mode=atomic
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
@ -139,7 +140,7 @@ eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic
cwd=build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic
drivers=
egid=100
env=
@ -179,11 +180,14 @@ transition_latency=100000000
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
forward_latency=4
frontend_latency=3
response_latency=2
snoop_filter=Null
snoop_response_latency=4
system=system
use_default_range=false
width=8
width=16
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master

24
tests/quick/se/70.twolf/ref/x86/linux/simple-timing/config.ini
View file

@ -23,6 +23,7 @@ load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
@ -92,7 +93,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
is_read_only=false
max_miss_count=0
mshrs=4
prefetch_on_access=false
@ -103,7 +104,6 @@ size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@ -143,7 +143,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
is_read_only=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
@ -154,7 +154,6 @@ size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@ -210,7 +209,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_top_level=false
is_read_only=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
@ -221,7 +220,6 @@ size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
@ -240,8 +238,11 @@ size=2097152
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
forward_latency=0
frontend_latency=1
response_latency=1
snoop_filter=Null
snoop_response_latency=1
system=system
use_default_range=false
width=32
@ -255,7 +256,7 @@ eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing
cwd=build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing
drivers=
egid=100
env=
@ -295,11 +296,14 @@ transition_latency=100000000
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
forward_latency=4
frontend_latency=3
response_latency=2
snoop_filter=Null
snoop_response_latency=4
system=system
use_default_range=false
width=8
width=16
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master