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gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt

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x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
---------- Begin Simulation Statistics ----------
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
sim_seconds 5.134211 # Number of seconds simulated
sim_ticks 5134211428000 # Number of ticks simulated
final_tick 5134211428000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
host_inst_rate 263536 # Simulator instruction rate (inst/s)
host_op_rate 523907 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5540037627 # Simulator tick rate (ticks/s)
host_mem_usage 1021876 # Number of bytes of host memory used
host_seconds 926.75 # Real time elapsed on the host
sim_insts 244230745 # Number of instructions simulated
sim_ops 485529516 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bytes_read::cpu0.inst 393536 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 5140544 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 149632 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 1859072 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker 2496 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 422208 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 3469952 # Number of bytes read from this memory
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bytes_read::total 11466176 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 393536 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 149632 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 422208 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 965376 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 9230336 # Number of bytes written to this memory
system.physmem.bytes_written::total 9230336 # Number of bytes written to this memory
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.num_reads::cpu0.inst 6149 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 80321 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 2338 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 29048 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker 39 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 6597 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 54218 # Number of read requests responded to by this memory
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.num_reads::total 179159 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 144224 # Number of write requests responded to by this memory
system.physmem.num_writes::total 144224 # Number of write requests responded to by this memory
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bw_read::cpu0.inst 76650 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1001233 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 29144 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 362095 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker 486 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.itb.walker 12 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 82234 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 675849 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::pc.south_bridge.ide 5522 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2233289 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 76650 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 29144 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 82234 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 188028 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1797810 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1797810 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1797810 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bw_total::cpu0.inst 76650 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 1001233 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 29144 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 362095 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker 486 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.itb.walker 12 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 82234 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 675849 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 5522 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4031099 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 92684 # Number of read requests accepted
system.physmem.writeReqs 79104 # Number of write requests accepted
system.physmem.readBursts 92684 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 79104 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 5924224 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue
system.physmem.bytesWritten 5060672 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 5931776 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 5062656 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 20933 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 6439 # Per bank write bursts
system.physmem.perBankRdBursts::1 5501 # Per bank write bursts
system.physmem.perBankRdBursts::2 5319 # Per bank write bursts
system.physmem.perBankRdBursts::3 5591 # Per bank write bursts
system.physmem.perBankRdBursts::4 5862 # Per bank write bursts
system.physmem.perBankRdBursts::5 5383 # Per bank write bursts
system.physmem.perBankRdBursts::6 5425 # Per bank write bursts
system.physmem.perBankRdBursts::7 4840 # Per bank write bursts
system.physmem.perBankRdBursts::8 6025 # Per bank write bursts
system.physmem.perBankRdBursts::9 5959 # Per bank write bursts
system.physmem.perBankRdBursts::10 5660 # Per bank write bursts
system.physmem.perBankRdBursts::11 5754 # Per bank write bursts
system.physmem.perBankRdBursts::12 5715 # Per bank write bursts
system.physmem.perBankRdBursts::13 6523 # Per bank write bursts
system.physmem.perBankRdBursts::14 5966 # Per bank write bursts
system.physmem.perBankRdBursts::15 6604 # Per bank write bursts
system.physmem.perBankWrBursts::0 5842 # Per bank write bursts
system.physmem.perBankWrBursts::1 5111 # Per bank write bursts
system.physmem.perBankWrBursts::2 4865 # Per bank write bursts
system.physmem.perBankWrBursts::3 5025 # Per bank write bursts
system.physmem.perBankWrBursts::4 5489 # Per bank write bursts
system.physmem.perBankWrBursts::5 4924 # Per bank write bursts
system.physmem.perBankWrBursts::6 4816 # Per bank write bursts
system.physmem.perBankWrBursts::7 4154 # Per bank write bursts
system.physmem.perBankWrBursts::8 4431 # Per bank write bursts
system.physmem.perBankWrBursts::9 4666 # Per bank write bursts
system.physmem.perBankWrBursts::10 4446 # Per bank write bursts
system.physmem.perBankWrBursts::11 4728 # Per bank write bursts
system.physmem.perBankWrBursts::12 4725 # Per bank write bursts
system.physmem.perBankWrBursts::13 5504 # Per bank write bursts
system.physmem.perBankWrBursts::14 4686 # Per bank write bursts
system.physmem.perBankWrBursts::15 5661 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.numWrRetry 3 # Number of times write queue was full causing retry
system.physmem.totGap 5133211221000 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.readPktSize::6 92684 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.writePktSize::6 79104 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 86281 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 4975 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 810 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 180 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 46 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 34 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.rdQLenPdf::7 35 # What read queue length does an incoming req see
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 30 # What read queue length does an incoming req see
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 23 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 23 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.wrQLenPdf::0 124 # What write queue length does an incoming req see
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.wrQLenPdf::1 65 # What write queue length does an incoming req see
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.wrQLenPdf::2 60 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 57 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 54 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 52 # What write queue length does an incoming req see
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.wrQLenPdf::7 53 # What write queue length does an incoming req see
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.wrQLenPdf::8 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 50 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 50 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 1288 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 1628 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4195 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4230 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 4194 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 4217 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 4200 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 4925 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 5092 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 5826 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 5258 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 5070 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 4491 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 4712 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 4886 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 4188 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 4126 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 4113 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 137 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 93 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 98 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 66 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 67 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 82 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 61 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 79 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 71 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 42 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 49 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 54 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 43 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 75 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 51 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 67 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 36 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 37 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 68 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 34 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 21 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 36 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 11 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 11 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 21 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 9 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 40692 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 269.949081 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 163.456020 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 296.352111 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 16538 40.64% 40.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 10119 24.87% 65.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 4173 10.26% 75.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 2507 6.16% 81.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 1551 3.81% 85.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1073 2.64% 88.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 750 1.84% 90.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 656 1.61% 91.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 3325 8.17% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 40692 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 4120 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 22.462136 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 184.101810 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511 4117 99.93% 99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1535 1 0.02% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-6655 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::9728-10239 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 4120 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 4120 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 19.192476 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.355155 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 11.050068 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3 67 1.63% 1.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7 6 0.15% 1.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15 4 0.10% 1.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 3537 85.85% 87.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 61 1.48% 89.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 102 2.48% 91.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 51 1.24% 92.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 38 0.92% 93.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 95 2.31% 96.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 16 0.39% 96.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 6 0.15% 96.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 9 0.22% 96.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 2 0.05% 96.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 2 0.05% 96.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 2 0.05% 97.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 98 2.38% 99.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 2 0.05% 99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 5 0.12% 99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 2 0.05% 99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 2 0.05% 99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 3 0.07% 99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 1 0.02% 99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 1 0.02% 99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.02% 99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 6 0.15% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 4120 # Writes before turning the bus around for reads
system.physmem.totQLat 1055441928 # Total ticks spent queuing
system.physmem.totMemAccLat 2791054428 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 462830000 # Total ticks spent in databus transfers
system.physmem.avgQLat 11402.05 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.avgMemAccLat 30152.05 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.15 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.16 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.99 # Average system write bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.physmem.busUtil 0.02 # Data bus utilization in percentage
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing
system.physmem.avgWrQLen 9.29 # Average write queue length when enqueuing
system.physmem.readRowHits 74063 # Number of row buffer hits during reads
system.physmem.writeRowHits 56883 # Number of row buffer hits during writes
system.physmem.readRowHitRate 80.01 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 71.91 # Row buffer hit rate for writes
system.physmem.avgGap 29881081.46 # Average gap between requests
system.physmem.pageHitRate 76.28 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 149294880 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 81184125 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 345992400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 260664480 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 250017250080 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 94809930840 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 2241062736000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 2586727052805 # Total energy per rank (pJ)
system.physmem_0.averagePower 667.763806 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 3682666821734 # Time in different power states
system.physmem_0.memoryStateTime::REF 127820680000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem_0.memoryStateTime::ACT 17822753766 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem_1.actEnergy 158336640 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 86183625 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 376006800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 251728560 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 250017250080 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 95265143955 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 2233496235000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 2579650884660 # Total energy per rank (pJ)
system.physmem_1.averagePower 667.996985 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 3682005807728 # Time in different power states
system.physmem_1.memoryStateTime::REF 127820680000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem_1.memoryStateTime::ACT 18463901522 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.numCycles 814812843 # number of cpu cycles simulated
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.committedInsts 70855773 # Number of instructions committed
system.cpu0.committedOps 144639705 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 132581707 # Number of integer alu accesses
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.num_func_calls 911803 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 14069363 # number of instructions that are conditional controls
system.cpu0.num_int_insts 132581707 # number of integer instructions
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.num_fp_insts 0 # number of float instructions
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.num_int_register_reads 242934374 # number of times the integer registers were read
system.cpu0.num_int_register_writes 114063964 # number of times the integer registers were written
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.num_cc_register_reads 82574901 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 55200628 # number of times the CC registers were written
system.cpu0.num_mem_refs 13389972 # number of memory refs
system.cpu0.num_load_insts 9966183 # Number of load instructions
system.cpu0.num_store_insts 3423789 # Number of store instructions
system.cpu0.num_idle_cycles 774643417.179050 # Number of idle cycles
system.cpu0.num_busy_cycles 40169425.820950 # Number of busy cycles
system.cpu0.not_idle_fraction 0.049299 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.950701 # Percentage of idle cycles
system.cpu0.Branches 15322983 # Number of branches fetched
system.cpu0.op_class::No_OpClass 87668 0.06% 0.06% # Class of executed instruction
system.cpu0.op_class::IntAlu 131058913 90.61% 90.67% # Class of executed instruction
system.cpu0.op_class::IntMult 57724 0.04% 90.71% # Class of executed instruction
system.cpu0.op_class::IntDiv 47555 0.03% 90.74% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 90.74% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 90.74% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 90.74% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 90.74% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 90.74% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 90.74% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 90.74% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 90.74% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 90.74% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 90.74% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 90.74% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 90.74% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 90.74% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 90.74% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 90.74% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.74% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 90.74% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.74% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.74% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.74% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.74% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.74% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.74% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 90.74% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.74% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.74% # Class of executed instruction
system.cpu0.op_class::MemRead 9964546 6.89% 97.63% # Class of executed instruction
system.cpu0.op_class::MemWrite 3423789 2.37% 100.00% # Class of executed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.op_class::total 144640195 # Class of executed instruction
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.tags.replacements 1639692 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.999446 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 19677629 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 1640204 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 11.997062 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 231.527826 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 256.098734 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data 24.372886 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.452203 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.500193 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.047603 # Average percentage of cache occupancy
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 163 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.tags.tag_accesses 88605943 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 88605943 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 4782117 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 2413671 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 4330956 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 11526744 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3296356 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 1699008 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data 3093469 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 8088833 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 19899 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 9911 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data 30439 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 60249 # number of SoftPFReq hits
system.cpu0.dcache.demand_hits::cpu0.data 8078473 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 4112679 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data 7424425 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 19615577 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 8098372 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 4122590 # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data 7454864 # number of overall hits
system.cpu0.dcache.overall_hits::total 19675826 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 346307 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 159141 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data 827752 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 1333200 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 123952 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 63357 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data 139093 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 326402 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 144703 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 63873 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data 197428 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 406004 # number of SoftPFReq misses
system.cpu0.dcache.demand_misses::cpu0.data 470259 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 222498 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data 966845 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 1659602 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 614962 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 286371 # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data 1164273 # number of overall misses
system.cpu0.dcache.overall_misses::total 2065606 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2189850500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 12100176000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 14290026500 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2530090000 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 4783086364 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 7313176364 # number of WriteReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 4719940500 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data 16883262364 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 21603202864 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 4719940500 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data 16883262364 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 21603202864 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 5128424 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 2572812 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data 5158708 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 12859944 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 3420308 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 1762365 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 3232562 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 8415235 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 164602 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 73784 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 227867 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 466253 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 8548732 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 4335177 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data 8391270 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 21275179 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 8713334 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 4408961 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 8619137 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 21741432 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.067527 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.061855 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.160457 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.103671 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.036240 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.035950 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.043029 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.038787 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.879108 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.865675 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.866418 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.870780 # miss rate for SoftPFReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.055009 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.051324 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.115220 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.078006 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.070577 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.064952 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.135080 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.095008 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13760.441998 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14618.117504 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 10718.591734 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39933.866818 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 34387.685678 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 22405.427553 # average WriteReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21213.406413 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17462.222346 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 13017.098596 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16481.908084 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14501.119895 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 10458.530264 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 191338 # number of cycles access was blocked
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.blocked::no_mshrs 22795 # number of cycles access was blocked
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.393858 # average number of cycles each access was blocked
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.writebacks::writebacks 1548927 # number of writebacks
system.cpu0.dcache.writebacks::total 1548927 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 51 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 386553 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 386604 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1542 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 32157 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 33699 # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 1593 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data 418710 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 420303 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 1593 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data 418710 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 420303 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 159090 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 441199 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 600289 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 61815 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 106936 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 168751 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 63873 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 194014 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 257887 # number of SoftPFReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 220905 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data 548135 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 769040 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 284778 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data 742149 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 1026927 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 185834 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 205183 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 391017 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 3059 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 4433 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 7492 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 188893 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 209616 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 398509 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2030358500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5964591000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7994949500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2384524000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 4092527864 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6477051864 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 931095000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2819292000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3750387000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4414882500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 10057118864 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 14472001364 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 5345977500 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 12876410864 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 18222388364 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30572400500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33247121500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63819522000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 547435500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 878869500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1426305000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31119836000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 34125991000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65245827000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.061835 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.085525 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.046679 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.035075 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.033081 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.020053 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.865675 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.851435 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.553105 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.050956 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.065322 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.036147 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.064591 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.086105 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.047234 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12762.326356 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13519.049227 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13318.500755 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38575.167840 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 38270.814917 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38382.302114 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14577.286177 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14531.384333 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14542.753221 # average SoftPFReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19985.434915 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18347.886678 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18818.268704 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18772.438531 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17350.169392 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17744.580057 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164514.569454 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 162036.433330 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 163214.187618 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178958.973521 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 198256.147079 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 190377.068873 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 164748.487239 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 162802.414892 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 163724.851885 # average overall mshr uncacheable latency
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.icache.tags.replacements 881776 # number of replacements
system.cpu0.icache.tags.tagsinuse 510.250144 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 127955824 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 882288 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 145.027275 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 149037485500 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 260.904392 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 141.200601 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst 108.145151 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.509579 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.275782 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.211221 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.996582 # Average percentage of cache occupancy
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.icache.tags.tag_accesses 129749175 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 129749175 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 86200122 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 38494727 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 3260975 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 127955824 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 86200122 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 38494727 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 3260975 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 127955824 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 86200122 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 38494727 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 3260975 # number of overall hits
system.cpu0.icache.overall_hits::total 127955824 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 293889 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 163550 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 453609 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 911048 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 293889 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 163550 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst 453609 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 911048 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 293889 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 163550 # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst 453609 # number of overall misses
system.cpu0.icache.overall_misses::total 911048 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2290465000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 6298842980 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 8589307980 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 2290465000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst 6298842980 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 8589307980 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 2290465000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst 6298842980 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 8589307980 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 86494011 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 38658277 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 3714584 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 128866872 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 86494011 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 38658277 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 3714584 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 128866872 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 86494011 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 38658277 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 3714584 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 128866872 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003398 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004231 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122116 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.007070 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003398 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004231 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122116 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.007070 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003398 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004231 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122116 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.007070 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14004.677469 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13886.062622 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 9427.942304 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14004.677469 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13886.062622 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 9427.942304 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14004.677469 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13886.062622 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 9427.942304 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 6492 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 22 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 290 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 22.386207 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets 22 # average number of cycles each access was blocked
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 28745 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 28745 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst 28745 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 28745 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst 28745 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 28745 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 163550 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 424864 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 588414 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 163550 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst 424864 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 588414 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 163550 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst 424864 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 588414 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2126915000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 5601122480 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 7728037480 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2126915000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 5601122480 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 7728037480 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2126915000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 5601122480 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 7728037480 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004231 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.114377 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004566 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004231 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.114377 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.004566 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004231 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.114377 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.004566 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13004.677469 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13183.330383 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13133.673706 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13004.677469 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13183.330383 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13133.673706 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13004.677469 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13183.330383 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13133.673706 # average overall mshr miss latency
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.numCycles 2606017483 # number of cpu cycles simulated
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.committedInsts 35137560 # Number of instructions committed
system.cpu1.committedOps 68325691 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 63404843 # Number of integer alu accesses
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.num_func_calls 475454 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 6463819 # number of instructions that are conditional controls
system.cpu1.num_int_insts 63404843 # number of integer instructions
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu1.num_fp_insts 0 # number of float instructions
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.num_int_register_reads 117292769 # number of times the integer registers were read
system.cpu1.num_int_register_writes 54636862 # number of times the integer registers were written
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.num_cc_register_reads 35859650 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 26723526 # number of times the CC registers were written
system.cpu1.num_mem_refs 4592942 # number of memory refs
system.cpu1.num_load_insts 2829969 # Number of load instructions
system.cpu1.num_store_insts 1762973 # Number of store instructions
system.cpu1.num_idle_cycles 2483716878.762911 # Number of idle cycles
system.cpu1.num_busy_cycles 122300604.237089 # Number of busy cycles
system.cpu1.not_idle_fraction 0.046930 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.953070 # Percentage of idle cycles
system.cpu1.Branches 7109683 # Number of branches fetched
system.cpu1.op_class::No_OpClass 33619 0.05% 0.05% # Class of executed instruction
system.cpu1.op_class::IntAlu 63651336 93.16% 93.21% # Class of executed instruction
system.cpu1.op_class::IntMult 27621 0.04% 93.25% # Class of executed instruction
system.cpu1.op_class::IntDiv 22176 0.03% 93.28% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 93.28% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 93.28% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 93.28% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 93.28% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 93.28% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 93.28% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 93.28% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 93.28% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 93.28% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 93.28% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 93.28% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 93.28% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 93.28% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 93.28% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 93.28% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.28% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 93.28% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.28% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.28% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.28% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.28% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.28% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.28% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 93.28% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.28% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.28% # Class of executed instruction
system.cpu1.op_class::MemRead 2828254 4.14% 97.42% # Class of executed instruction
system.cpu1.op_class::MemWrite 1762973 2.58% 100.00% # Class of executed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.op_class::total 68325979 # Class of executed instruction
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu2.branchPred.lookups 29728292 # Number of BP lookups
system.cpu2.branchPred.condPredicted 29728292 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 354491 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 26875418 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 26145153 # Number of BTB hits
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu2.branchPred.BTBHitPct 97.282777 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 627673 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 71339 # Number of incorrect RAS predictions.
system.cpu2.numCycles 156747191 # number of cpu cycles simulated
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu2.fetch.icacheStallCycles 11575217 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 146531331 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 29728292 # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches 26772826 # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles 143455759 # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles 740896 # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles 117693 # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.MiscStallCycles 8882 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles 9184 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles 67495 # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles 36 # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles 614 # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines 3714591 # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes 185121 # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.ItlbSquashes 4402 # Number of outstanding ITLB misses that were squashed
system.cpu2.fetch.rateDist::samples 155604677 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean 1.852545 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev 3.032784 # Number of instructions fetched each cycle (Total)
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu2.fetch.rateDist::0 99528214 63.96% 63.96% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1 894883 0.58% 64.54% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2 23827863 15.31% 79.85% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3 616054 0.40% 80.25% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4 865023 0.56% 80.80% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5 874152 0.56% 81.36% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6 593045 0.38% 81.75% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7 766815 0.49% 82.24% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8 27638628 17.76% 100.00% # Number of instructions fetched each cycle (Total)
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu2.fetch.rateDist::total 155604677 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate 0.189658 # Number of branch fetches per cycle
system.cpu2.fetch.rate 0.934826 # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles 10653655 # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles 94438460 # Number of cycles decode is blocked
system.cpu2.decode.RunCycles 23846115 # Number of cycles decode is running
system.cpu2.decode.UnblockCycles 5077401 # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles 371099 # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts 285226302 # Number of instructions handled by decode
system.cpu2.rename.SquashCycles 371099 # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles 12813669 # Number of cycles rename is idle
system.cpu2.rename.BlockCycles 77065666 # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles 4747202 # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles 26484696 # Number of cycles rename is running
system.cpu2.rename.UnblockCycles 12904465 # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts 283889044 # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents 204785 # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents 5893747 # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents 54074 # Number of times rename has blocked due to LQ full
system.cpu2.rename.SQFullEvents 4792782 # Number of times rename has blocked due to SQ full
system.cpu2.rename.RenamedOperands 339006774 # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups 620283621 # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups 380802622 # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups 280 # Number of floating rename lookups
system.cpu2.rename.CommittedMaps 325933868 # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps 13072904 # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts 167839 # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts 169378 # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts 24708176 # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads 6969767 # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores 3922969 # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads 416514 # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores 341941 # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded 281777756 # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded 433047 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 279489336 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 112446 # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined 9646678 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 14520235 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 68066 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 155604677 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean 1.796150 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev 2.396491 # Number of insts issued each cycle
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu2.iq.issued_per_cycle::0 92126087 59.21% 59.21% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1 5408193 3.48% 62.68% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2 3871909 2.49% 65.17% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3 3896687 2.50% 67.67% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4 22645736 14.55% 82.23% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5 2817206 1.81% 84.04% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6 24121295 15.50% 99.54% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7 489992 0.31% 99.85% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8 227572 0.15% 100.00% # Number of insts issued each cycle
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu2.iq.issued_per_cycle::total 155604677 # Number of insts issued each cycle
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu2.iq.fu_full::IntAlu 1782744 86.25% 86.25% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult 0 0.00% 86.25% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv 0 0.00% 86.25% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 86.25% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 86.25% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt 2 0.00% 86.25% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult 0 0.00% 86.25% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 86.25% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 86.25% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 86.25% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 86.25% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 86.25% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 86.25% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 86.25% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 86.25% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult 0 0.00% 86.25% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 86.25% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift 0 0.00% 86.25% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 86.25% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 86.25% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 86.25% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 86.25% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 86.25% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 86.25% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 86.25% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 86.25% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 86.25% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 86.25% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 86.25% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead 219490 10.62% 96.87% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite 64665 3.13% 100.00% # attempts to use FU when none available
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu2.iq.FU_type_0::No_OpClass 84223 0.03% 0.03% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu 268409283 96.04% 96.07% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult 60791 0.02% 96.09% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv 54867 0.02% 96.11% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.11% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.11% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt 128 0.00% 96.11% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.11% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.11% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.11% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.11% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.11% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.11% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.11% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.11% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.11% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.11% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.11% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.11% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.11% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.11% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.11% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.11% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.11% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.11% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.11% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.11% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.11% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.11% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.11% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead 7262488 2.60% 98.71% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite 3617556 1.29% 100.00% # Type of FU issued
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu2.iq.FU_type_0::total 279489336 # Type of FU issued
system.cpu2.iq.rate 1.783058 # Inst issue rate
system.cpu2.iq.fu_busy_cnt 2066901 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.007395 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 716762296 # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes 291861984 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 277802443 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 399 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 402 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 161 # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses 281471819 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 195 # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads 741069 # Number of loads that had data forwarded from stores
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu2.iew.lsq.thread0.squashedLoads 1314442 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 6549 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation 5531 # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores 685228 # Number of stores squashed
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu2.iew.lsq.thread0.rescheduledLoads 750208 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 28435 # Number of times an access to memory failed due to the cache being blocked
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu2.iew.iewSquashCycles 371099 # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles 70840326 # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles 3147966 # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts 282210803 # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts 45613 # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts 6969767 # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts 3922969 # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts 254598 # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents 166407 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 2652713 # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents 5531 # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect 201920 # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect 210112 # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts 412032 # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts 278837771 # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts 7102995 # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts 592219 # Number of squashed instructions skipped in execute
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iew.exec_swp 0 # number of swp insts executed
system.cpu2.iew.exec_nop 0 # number of nop insts executed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu2.iew.exec_refs 10623704 # number of memory reference insts executed
system.cpu2.iew.exec_branches 28332312 # Number of branches executed
system.cpu2.iew.exec_stores 3520709 # Number of stores executed
system.cpu2.iew.exec_rate 1.778901 # Inst execution rate
system.cpu2.iew.wb_sent 278631802 # cumulative count of insts sent to commit
system.cpu2.iew.wb_count 277802604 # cumulative count of insts written-back
system.cpu2.iew.wb_producers 216492114 # num instructions producing a value
system.cpu2.iew.wb_consumers 355079818 # num instructions consuming a value
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu2.iew.wb_rate 1.772297 # insts written-back per cycle
system.cpu2.iew.wb_fanout 0.609700 # average fanout of values written-back
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu2.commit.commitSquashedInsts 9642578 # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls 364981 # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts 357554 # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples 154160156 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean 1.768058 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev 2.650606 # Number of insts commited each cycle
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu2.commit.committed_per_cycle::0 95860610 62.18% 62.18% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1 4461430 2.89% 65.08% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2 1337416 0.87% 65.94% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3 24820120 16.10% 82.04% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4 1009976 0.66% 82.70% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5 732580 0.48% 83.17% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6 443548 0.29% 83.46% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7 23352402 15.15% 98.61% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8 2142074 1.39% 100.00% # Number of insts commited each cycle
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu2.commit.committed_per_cycle::total 154160156 # Number of insts commited each cycle
system.cpu2.commit.committedInsts 138237412 # Number of instructions committed
system.cpu2.commit.committedOps 272564120 # Number of ops (including micro ops) committed
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu2.commit.refs 8893065 # Number of memory references committed
system.cpu2.commit.loads 5655324 # Number of loads committed
system.cpu2.commit.membars 162767 # Number of memory barriers committed
system.cpu2.commit.branches 27901240 # Number of branches committed
stats: changes due to recent changesets.
2015-01-11 01:06:43 +01:00
system.cpu2.commit.fp_insts 48 # Number of committed floating point instructions.
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu2.commit.int_insts 249166189 # Number of committed integer instructions.
system.cpu2.commit.function_calls 462772 # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass 50638 0.02% 0.02% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu 263510022 96.68% 96.70% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult 58397 0.02% 96.72% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv 52041 0.02% 96.74% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.74% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.74% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.74% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.74% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.74% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.74% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.74% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.74% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.74% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.74% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.74% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.74% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.74% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.74% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.74% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.74% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.74% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.74% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.74% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.74% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.74% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.74% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.74% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.74% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.74% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.74% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead 5655265 2.07% 98.81% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite 3237741 1.19% 100.00% # Class of committed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu2.commit.op_class_0::total 272564120 # Class of committed instruction
system.cpu2.commit.bw_lim_events 2142074 # number cycles where commit BW limit reached
system.cpu2.rob.rob_reads 434194585 # The number of ROB reads
system.cpu2.rob.rob_writes 565865422 # The number of ROB writes
system.cpu2.timesIdled 127222 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles 1142514 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 4899644826 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts 138237412 # Number of Instructions Simulated
system.cpu2.committedOps 272564120 # Number of Ops (including micro ops) Simulated
system.cpu2.cpi 1.133898 # CPI: Cycles Per Instruction
system.cpu2.cpi_total 1.133898 # CPI: Total CPI of All Threads
system.cpu2.ipc 0.881913 # IPC: Instructions Per Cycle
system.cpu2.ipc_total 0.881913 # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads 371610814 # number of integer regfile reads
system.cpu2.int_regfile_writes 222643670 # number of integer regfile writes
system.cpu2.fp_regfile_reads 73073 # number of floating regfile reads
system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes
system.cpu2.cc_regfile_reads 141701796 # number of cc regfile reads
system.cpu2.cc_regfile_writes 108796323 # number of cc regfile writes
system.cpu2.misc_regfile_reads 90941344 # number of misc regfile reads
system.cpu2.misc_regfile_writes 144983 # number of misc regfile writes
system.iobus.trans_dist::ReadReq 3552121 # Transaction distribution
system.iobus.trans_dist::ReadResp 3552121 # Transaction distribution
system.iobus.trans_dist::WriteReq 57703 # Transaction distribution
system.iobus.trans_dist::WriteResp 57703 # Transaction distribution
system.iobus.trans_dist::MessageReq 1657 # Transaction distribution
system.iobus.trans_dist::MessageResp 1657 # Transaction distribution
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11042 # Packet count per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7080216 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1182 # Packet count per connected master and slave (bytes)
x86: Update stats for the new Linux delay port.
2014-11-22 02:22:19 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27854 # Packet count per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.pkt_count_system.bridge.master::total 7124404 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3314 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3314 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 7222962 # Packet count per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6660 # Cumulative packet size per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3540108 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2364 # Cumulative packet size per connected master and slave (bytes)
x86: Update stats for the new Linux delay port.
2014-11-22 02:22:19 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13927 # Cumulative packet size per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.pkt_size_system.bridge.master::total 3568437 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027760 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027760 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6628 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6628 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 6602825 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 2786496 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.reqLayer3.occupancy 5677000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.reqLayer6.occupancy 34000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.iobus.reqLayer7.occupancy 18000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.reqLayer9.occupancy 140109000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.reqLayer10.occupancy 441000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.reqLayer14.occupancy 11327000 # Layer occupancy (ticks)
x86: Update stats for the new Linux delay port.
2014-11-22 02:22:19 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.reqLayer18.occupancy 4000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.reqLayer19.occupancy 104116682 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
x86: Update stats for the new Linux delay port.
2014-11-22 02:22:19 +01:00
system.iobus.reqLayer20.occupancy 1032000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.respLayer0.occupancy 300127000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.respLayer1.occupancy 23084000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.respLayer2.occupancy 1172000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.tags.replacements 47567 # number of replacements
system.iocache.tags.tagsinuse 0.081431 # Cycle average of tags in use
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.tags.sampled_refs 47583 # Sample count of references to valid blocks.
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.tags.warmup_cycle 5000591236509 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.081431 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005089 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.005089 # Average percentage of cache occupancy
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.tags.tag_accesses 428598 # Number of tag accesses
system.iocache.tags.data_accesses 428598 # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide 902 # number of ReadReq misses
system.iocache.ReadReq_misses::total 902 # number of ReadReq misses
system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses
system.iocache.demand_misses::pc.south_bridge.ide 902 # number of demand (read+write) misses
system.iocache.demand_misses::total 902 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 902 # number of overall misses
system.iocache.overall_misses::total 902 # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 121586746 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 121586746 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 2354972936 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 2354972936 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide 121586746 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 121586746 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide 121586746 # number of overall miss cycles
system.iocache.overall_miss_latency::total 121586746 # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide 902 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 902 # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide 902 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 902 # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide 902 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 902 # number of overall (read+write) accesses
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 134796.835920 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 134796.835920 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 50406.098801 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 50406.098801 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 134796.835920 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 134796.835920 # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 134796.835920 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 134796.835920 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 552 # number of cycles access was blocked
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.blocked::no_mshrs 46 # number of cycles access was blocked
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.avg_blocked_cycles::no_mshrs 12 # average number of cycles each access was blocked
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 746 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 746 # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 19960 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 19960 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide 746 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 746 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 746 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 746 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 84286746 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 84286746 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 1356972936 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 1356972936 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 84286746 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 84286746 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 84286746 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 84286746 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.827051 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.827051 # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 0.427226 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 0.427226 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.827051 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 0.827051 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.827051 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 0.827051 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 112984.914209 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 112984.914209 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 67984.616032 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67984.616032 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 112984.914209 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 112984.914209 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 112984.914209 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 112984.914209 # average overall mshr miss latency
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.tags.replacements 105904 # number of replacements
system.l2c.tags.tagsinuse 64832.216142 # Cycle average of tags in use
system.l2c.tags.total_refs 4698304 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 170185 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 27.607039 # Average number of references to valid blocks.
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.tags.occ_blocks::writebacks 50894.263020 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.125303 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 1602.122983 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 5170.967993 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 244.936624 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 1566.576743 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.469260 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.itb.walker 0.003420 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 1245.636306 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 4101.114491 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.776585 # Average percentage of cache occupancy
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.tags.occ_percent::cpu0.inst 0.024446 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.078903 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.003737 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.023904 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000099 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.019007 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.062578 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.989261 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 64281 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 679 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 3076 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 7407 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 53037 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.980850 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 41908906 # Number of tag accesses
system.l2c.tags.data_accesses 41908906 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 18995 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 10333 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 12983 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 7660 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker 68713 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker 15994 # number of ReadReq hits
system.l2c.ReadReq_hits::total 134678 # number of ReadReq hits
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits
system.l2c.WriteReq_hits::total 2 # number of WriteReq hits
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.Writeback_hits::writebacks 1548927 # number of Writeback hits
system.l2c.Writeback_hits::total 1548927 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 114 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 55 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data 87 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 256 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 58015 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 36167 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data 65709 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 159891 # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst 287726 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst 161212 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst 418246 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total 867184 # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 475648 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 219061 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data 621112 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 1315821 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker 18995 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 10335 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 287726 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 533663 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 12983 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 7660 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 161212 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 255228 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker 68713 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker 15994 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 418246 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 686821 # number of demand (read+write) hits
system.l2c.demand_hits::total 2477576 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 18995 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 10335 # number of overall hits
system.l2c.overall_hits::cpu0.inst 287726 # number of overall hits
system.l2c.overall_hits::cpu0.data 533663 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 12983 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 7660 # number of overall hits
system.l2c.overall_hits::cpu1.inst 161212 # number of overall hits
system.l2c.overall_hits::cpu1.data 255228 # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker 68713 # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker 15994 # number of overall hits
system.l2c.overall_hits::cpu2.inst 418246 # number of overall hits
system.l2c.overall_hits::cpu2.data 686821 # number of overall hits
system.l2c.overall_hits::total 2477576 # number of overall hits
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.ReadReq_misses::cpu2.dtb.walker 39 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.itb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::total 45 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 613 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 245 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 572 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 1430 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 65210 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 25360 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 40614 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 131184 # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst 6150 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst 2338 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu2.inst 6597 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total 15085 # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 15362 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 3902 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2.data 14056 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 33320 # number of ReadSharedReq misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.demand_misses::cpu0.inst 6150 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 80572 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 2338 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 29262 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker 39 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.itb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst 6597 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 54670 # number of demand (read+write) misses
system.l2c.demand_misses::total 179634 # number of demand (read+write) misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.overall_misses::cpu0.inst 6150 # number of overall misses
system.l2c.overall_misses::cpu0.data 80572 # number of overall misses
system.l2c.overall_misses::cpu1.inst 2338 # number of overall misses
system.l2c.overall_misses::cpu1.data 29262 # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker 39 # number of overall misses
system.l2c.overall_misses::cpu2.itb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu2.inst 6597 # number of overall misses
system.l2c.overall_misses::cpu2.data 54670 # number of overall misses
system.l2c.overall_misses::total 179634 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 3644000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.itb.walker 97000 # number of ReadReq miss cycles
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system.l2c.UpgradeReq_miss_latency::cpu1.data 5007000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data 7177500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 12184500 # number of UpgradeReq miss cycles
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system.l2c.ReadExReq_miss_latency::total 5122868500 # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 188281500 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu2.inst 560185000 # number of ReadCleanReq miss cycles
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system.l2c.demand_miss_latency::cpu2.inst 560185000 # number of demand (read+write) miss cycles
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system.l2c.overall_miss_latency::total 7415359000 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 18995 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 10338 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 12983 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 7660 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker 68752 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker 15995 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 134723 # number of ReadReq accesses(hits+misses)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.l2c.WriteReq_accesses::cpu0.itb.walker 2 # number of WriteReq accesses(hits+misses)
system.l2c.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
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system.l2c.Writeback_accesses::total 1548927 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 727 # number of UpgradeReq accesses(hits+misses)
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system.l2c.ReadCleanReq_accesses::cpu1.inst 163550 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu2.inst 424843 # number of ReadCleanReq accesses(hits+misses)
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system.l2c.UpgradeReq_miss_rate::cpu0.data 0.843191 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.816667 # miss rate for UpgradeReq accesses
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system.l2c.ReadExReq_miss_rate::cpu2.data 0.381987 # miss rate for ReadExReq accesses
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system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.014295 # miss rate for ReadCleanReq accesses
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system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.017501 # miss rate for ReadSharedReq accesses
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system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 97000 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 83133.333333 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 20436.734694 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 12548.076923 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 8520.629371 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75026.853312 # average ReadExReq miss latency
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system.l2c.ReadExReq_avg_miss_latency::total 39051.016130 # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80531.009410 # average ReadCleanReq miss latency
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system.l2c.ReadCleanReq_avg_miss_latency::total 49616.605900 # average ReadCleanReq miss latency
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system.l2c.demand_avg_miss_latency::cpu2.inst 84915.112930 # average overall miss latency
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system.l2c.overall_avg_miss_latency::cpu2.data 81098.216572 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 41280.375653 # average overall miss latency
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
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system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
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system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 39 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 1 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 40 # number of ReadReq MSHR misses
system.l2c.CleanEvict_mshr_misses::writebacks 51 # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total 51 # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 245 # number of UpgradeReq MSHR misses
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system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 2338 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 6597 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total 8935 # number of ReadCleanReq MSHR misses
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system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28761729000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31510213500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 60271942500 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000567 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000063 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.000297 # mshr miss rate for ReadReq accesses
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.816667 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.867982 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.484579 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.412177 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.381987 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.226656 # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.014295 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.015528 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010127 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.017501 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.022130 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.013311 # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014295 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.102858 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000567 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000063 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.015528 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.073730 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.034964 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014295 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.102858 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000567 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000063 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.015528 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.073730 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.034964 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 83435.897436 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 87000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 83525 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23181.632653 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20841.783217 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21543.451652 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65026.853312 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69287.622495 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 67649.809016 # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70531.009410 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 74915.112930 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73767.935087 # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 73759.866735 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 76338.574274 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 75778.260385 # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70531.009410 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66191.374479 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 83435.897436 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 87000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 74915.112930 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 71100.466435 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 69816.181773 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70531.009410 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66191.374479 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 83435.897436 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 87000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 74915.112930 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 71100.466435 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 69816.181773 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152014.550620 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 149536.426020 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 150714.174831 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167458.973521 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 186754.116851 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 178875.867592 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 152264.663063 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 150323.512995 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 151243.616832 # average overall mshr uncacheable latency
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::ReadReq 5067078 # Transaction distribution
system.membus.trans_dist::ReadResp 5116429 # Transaction distribution
system.membus.trans_dist::WriteReq 13886 # Transaction distribution
system.membus.trans_dist::WriteResp 13886 # Transaction distribution
system.membus.trans_dist::Writeback 144224 # Transaction distribution
system.membus.trans_dist::CleanEvict 8915 # Transaction distribution
system.membus.trans_dist::UpgradeReq 1691 # Transaction distribution
system.membus.trans_dist::UpgradeResp 1691 # Transaction distribution
system.membus.trans_dist::ReadExReq 130923 # Transaction distribution
system.membus.trans_dist::ReadExResp 130923 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 49352 # Transaction distribution
system.membus.trans_dist::MessageReq 1657 # Transaction distribution
system.membus.trans_dist::MessageResp 1657 # Transaction distribution
system.membus.trans_dist::BadAddressError 1 # Transaction distribution
system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution
system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3314 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total 3314 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7124404 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3037524 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 467564 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 2 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 10629494 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142133 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 142133 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 10774941 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6628 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total 6628 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3568437 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6075045 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17691840 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 27335322 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3025024 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 3025024 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 30366974 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 812 # Total snoops (count)
system.membus.snoop_fanout::samples 5464824 # Request fanout histogram
system.membus.snoop_fanout::mean 1.000303 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.017410 # Request fanout histogram
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.snoop_fanout::1 5463167 99.97% 99.97% # Request fanout histogram
system.membus.snoop_fanout::2 1657 0.03% 100.00% # Request fanout histogram
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.membus.snoop_fanout::max_value 2 # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.snoop_fanout::total 5464824 # Request fanout histogram
system.membus.reqLayer0.occupancy 233042000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.reqLayer1.occupancy 304115000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.reqLayer2.occupancy 2344000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.reqLayer3.occupancy 525464887 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.membus.respLayer0.occupancy 1172000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.respLayer2.occupancy 1340471277 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.respLayer4.occupancy 38659394 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.pc.south_bridge.ide.disks0.dma_read_txs 29 # Number of DMA read transactions (not PRD).
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.toL2Bus.trans_dist::ReadReq 5232649 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 7464311 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 13888 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 13888 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 1628034 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 977588 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 1686 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 1686 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 291075 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 291075 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 882303 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 1349887 # Transaction distribution
system.toL2Bus.trans_dist::MessageReq 1172 # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError 1 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 19960 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2645849 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15085510 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 77708 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 228805 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 18037872 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56466048 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213762586 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 290440 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 837080 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 271356154 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 159100 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 10426288 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 1.028740 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.167075 # Request fanout histogram
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.toL2Bus.snoop_fanout::1 10126637 97.13% 97.13% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 299651 2.87% 100.00% # Request fanout histogram
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.toL2Bus.snoop_fanout::total 10426288 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 2853173500 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.toL2Bus.respLayer0.occupancy 883247245 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.toL2Bus.respLayer1.occupancy 1934319786 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.toL2Bus.respLayer2.occupancy 28757491 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.toL2Bus.respLayer3.occupancy 101435667 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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