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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt

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ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
---------- Begin Simulation Statistics ----------
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
sim_seconds 2.607932 # Number of seconds simulated
sim_ticks 2607931908500 # Number of ticks simulated
final_tick 2607931908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
host_inst_rate 52184 # Simulator instruction rate (inst/s)
host_op_rate 62850 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2168410643 # Simulator tick rate (ticks/s)
host_mem_usage 492092 # Number of bytes of host memory used
host_seconds 1202.69 # Real time elapsed on the host
sim_insts 62761278 # Number of instructions simulated
sim_ops 75589768 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.realview.nvmem.bytes_read::cpu0.inst 48 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 128 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 176 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 48 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 128 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 176 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 3 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 8 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 18 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 49 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 67 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 18 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 49 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 67 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 18 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 49 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 67 # Total bandwidth to/from this memory (bytes/s)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 122112 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 457724 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher 4608960 # Number of bytes read from this memory
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.bytes_read::cpu1.dtb.walker 512 # Number of bytes read from this memory
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.physmem.bytes_read::cpu1.inst 71568 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 618744 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher 5382208 # Number of bytes read from this memory
system.physmem.bytes_read::total 132372740 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 122112 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 71568 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 193680 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4391552 # Number of bytes written to this memory
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.physmem.bytes_written::total 7420688 # Number of bytes written to this memory
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.num_reads::cpu0.dtb.walker 3 # Number of read requests responded to by this memory
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 4443 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 7211 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher 72015 # Number of read requests responded to by this memory
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.num_reads::cpu1.dtb.walker 8 # Number of read requests responded to by this memory
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.physmem.num_reads::cpu1.inst 1161 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 9686 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher 84097 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15317443 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 68618 # Number of write requests responded to by this memory
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.physmem.num_writes::total 825902 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 46439298 # Total read bandwidth from this memory (bytes/s)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.bw_read::cpu0.dtb.walker 74 # Total read bandwidth from this memory (bytes/s)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.physmem.bw_read::cpu0.itb.walker 74 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 46823 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 175512 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher 1767285 # Total read bandwidth from this memory (bytes/s)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.bw_read::cpu1.dtb.walker 196 # Total read bandwidth from this memory (bytes/s)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.physmem.bw_read::cpu1.inst 27442 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 237255 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher 2063784 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 50757744 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 46823 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 27442 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 74266 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1683921 # Write bandwidth from this memory (bytes/s)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.bw_write::cpu0.data 6519 # Write bandwidth from this memory (bytes/s)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.physmem.bw_write::cpu1.data 1154990 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2845430 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1683921 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 46439298 # Total bandwidth to/from this memory (bytes/s)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.bw_total::cpu0.dtb.walker 74 # Total bandwidth to/from this memory (bytes/s)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.physmem.bw_total::cpu0.itb.walker 74 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 46823 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 182031 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher 1767285 # Total bandwidth to/from this memory (bytes/s)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.bw_total::cpu1.dtb.walker 196 # Total bandwidth to/from this memory (bytes/s)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.physmem.bw_total::cpu1.inst 27442 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 1392245 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher 2063784 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 53603174 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15317443 # Number of read requests accepted
system.physmem.writeReqs 825902 # Number of write requests accepted
system.physmem.readBursts 15317443 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 825902 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 976329024 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 3987328 # Total number of bytes read from write queue
system.physmem.bytesWritten 7443968 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 132372740 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7420688 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 62302 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 709563 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 16003 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 957415 # Per bank write bursts
system.physmem.perBankRdBursts::1 954356 # Per bank write bursts
system.physmem.perBankRdBursts::2 951532 # Per bank write bursts
system.physmem.perBankRdBursts::3 951095 # Per bank write bursts
system.physmem.perBankRdBursts::4 960453 # Per bank write bursts
system.physmem.perBankRdBursts::5 954333 # Per bank write bursts
system.physmem.perBankRdBursts::6 950562 # Per bank write bursts
system.physmem.perBankRdBursts::7 950350 # Per bank write bursts
system.physmem.perBankRdBursts::8 957423 # Per bank write bursts
system.physmem.perBankRdBursts::9 955252 # Per bank write bursts
system.physmem.perBankRdBursts::10 950399 # Per bank write bursts
system.physmem.perBankRdBursts::11 949996 # Per bank write bursts
system.physmem.perBankRdBursts::12 957025 # Per bank write bursts
system.physmem.perBankRdBursts::13 954231 # Per bank write bursts
system.physmem.perBankRdBursts::14 950565 # Per bank write bursts
system.physmem.perBankRdBursts::15 950154 # Per bank write bursts
system.physmem.perBankWrBursts::0 7537 # Per bank write bursts
system.physmem.perBankWrBursts::1 7271 # Per bank write bursts
system.physmem.perBankWrBursts::2 7519 # Per bank write bursts
system.physmem.perBankWrBursts::3 7339 # Per bank write bursts
system.physmem.perBankWrBursts::4 7525 # Per bank write bursts
system.physmem.perBankWrBursts::5 7506 # Per bank write bursts
system.physmem.perBankWrBursts::6 7304 # Per bank write bursts
system.physmem.perBankWrBursts::7 7173 # Per bank write bursts
system.physmem.perBankWrBursts::8 7520 # Per bank write bursts
system.physmem.perBankWrBursts::9 7613 # Per bank write bursts
system.physmem.perBankWrBursts::10 6934 # Per bank write bursts
system.physmem.perBankWrBursts::11 6533 # Per bank write bursts
system.physmem.perBankWrBursts::12 7225 # Per bank write bursts
system.physmem.perBankWrBursts::13 7011 # Per bank write bursts
system.physmem.perBankWrBursts::14 7249 # Per bank write bursts
system.physmem.perBankWrBursts::15 7053 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.physmem.totGap 2607930021000 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.readPktSize::2 59 # Read request sizes (log2)
system.physmem.readPktSize::3 15138841 # Read request sizes (log2)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.physmem.readPktSize::4 3437 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.physmem.readPktSize::6 175106 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.writePktSize::2 757284 # Write request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.physmem.writePktSize::6 68618 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 1022635 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1020084 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 981701 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1092290 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 979402 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1043990 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2669652 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 2569034 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 3344990 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 138441 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 119851 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 110072 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 105368 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 19798 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 18864 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 18580 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 172 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 86 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 34 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 28 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 13 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 12 # What read queue length does an incoming req see
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.rdQLenPdf::23 12 # What read queue length does an incoming req see
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.physmem.rdQLenPdf::24 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 1 # What read queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.physmem.wrQLenPdf::15 3004 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 3292 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 3735 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4905 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5459 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5947 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6453 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 6852 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 7574 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 7122 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 7315 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 7509 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 7660 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 7978 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 7585 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 7635 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 7768 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 7486 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 568 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 271 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 105 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 43 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 18 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 17 # What write queue length does an incoming req see
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.physmem.wrQLenPdf::48 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 2 # What write queue length does an incoming req see
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 1 # What write queue length does an incoming req see
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.physmem.bytesPerActivate::samples 1020956 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 963.580205 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 884.289338 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 220.002398 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 33463 3.28% 3.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 19295 1.89% 5.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 8776 0.86% 6.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 2662 0.26% 6.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 3249 0.32% 6.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 2138 0.21% 6.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 8494 0.83% 7.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1074 0.11% 7.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 941805 92.25% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1020956 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6723 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 2269.096237 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 97829.440322 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-262143 6717 99.91% 99.91% # Reads before turning the bus around for writes
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.rdPerTurnAround::262144-524287 1 0.01% 99.93% # Reads before turning the bus around for writes
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.physmem.rdPerTurnAround::524288-786431 2 0.03% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.01% 99.97% # Reads before turning the bus around for writes
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.rdPerTurnAround::2.3593e+06-2.62144e+06 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::7.34003e+06-7.60218e+06 1 0.01% 100.00% # Reads before turning the bus around for writes
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.physmem.rdPerTurnAround::total 6723 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6723 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.300610 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.224413 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 1.695658 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 3618 53.82% 53.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 52 0.77% 54.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 1623 24.14% 78.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 981 14.59% 93.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 153 2.28% 95.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 115 1.71% 97.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 65 0.97% 98.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 63 0.94% 99.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24 23 0.34% 99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25 16 0.24% 99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26 7 0.10% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27 4 0.06% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28 1 0.01% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::31 1 0.01% 99.99% # Writes before turning the bus around for reads
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.wrPerTurnAround::32 1 0.01% 100.00% # Writes before turning the bus around for reads
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.physmem.wrPerTurnAround::total 6723 # Writes before turning the bus around for reads
system.physmem.totQLat 400005056750 # Total ticks spent queuing
system.physmem.totMemAccLat 686038950500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 76275705000 # Total ticks spent in databus transfers
system.physmem.avgQLat 26221.00 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.physmem.avgMemAccLat 44971.00 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 374.37 # Average DRAM read bandwidth in MiByte/s
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.avgWrBW 2.85 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 50.76 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.85 # Average system write bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.busUtil 2.95 # Data bus utilization in percentage
system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.physmem.avgRdQLen 6.13 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.82 # Average write queue length when enqueuing
system.physmem.readRowHits 14262971 # Number of row buffer hits during reads
system.physmem.writeRowHits 87526 # Number of row buffer hits during writes
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.readRowHitRate 93.50 # Row buffer hit rate for reads
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.physmem.writeRowHitRate 75.23 # Row buffer hit rate for writes
system.physmem.avgGap 161548.30 # Average gap between requests
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.pageHitRate 93.36 # Row buffer hit rate, read and write combined
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.physmem.memoryStateTime::IDLE 2277790546750 # Time in different power states
system.physmem.memoryStateTime::REF 87084400000 # Time in different power states
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.physmem.memoryStateTime::ACT 243051888250 # Time in different power states
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.physmem.actEnergy::0 3862736640 # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1 3855690720 # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0 2107644000 # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1 2103799500 # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0 59514748800 # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1 59475351000 # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0 383447520 # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1 370254240 # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0 170337086400 # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1 170337086400 # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0 141921165285 # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1 140687744850 # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0 1440263842500 # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1 1441345790250 # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0 1818390671145 # Total energy per rank (pJ)
system.physmem.totalEnergy::1 1818175716960 # Total energy per rank (pJ)
system.physmem.averagePower::0 697.255251 # Core power per rank (mW)
system.physmem.averagePower::1 697.172828 # Core power per rank (mW)
system.membus.trans_dist::ReadReq 16496763 # Transaction distribution
system.membus.trans_dist::ReadResp 16496763 # Transaction distribution
system.membus.trans_dist::WriteReq 769202 # Transaction distribution
system.membus.trans_dist::WriteResp 769202 # Transaction distribution
system.membus.trans_dist::Writeback 68618 # Transaction distribution
system.membus.trans_dist::UpgradeReq 58416 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 23667 # Transaction distribution
system.membus.trans_dist::UpgradeResp 16003 # Transaction distribution
system.membus.trans_dist::ReadExReq 15703 # Transaction distribution
system.membus.trans_dist::ReadExResp 8933 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384368 # Packet count per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13898 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2050 # Packet count per connected master and slave (bytes)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2045296 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 4445638 # Packet count per connected master and slave (bytes)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.membus.pkt_count::total 34723270 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2392677 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 176 # Cumulative packet size per connected master and slave (bytes)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27796 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4100 # Cumulative packet size per connected master and slave (bytes)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18682900 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 21107657 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.membus.pkt_size::total 142218185 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 72850 # Total snoops (count)
system.membus.snoop_fanout::samples 332577 # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.membus.snoop_fanout::1 332577 100.00% 100.00% # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.membus.snoop_fanout::total 332577 # Request fanout histogram
system.membus.reqLayer0.occupancy 1569259492 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.membus.reqLayer1.occupancy 13500 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.membus.reqLayer2.occupancy 11956494 # Layer occupancy (ticks)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.membus.reqLayer5.occupancy 1552000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.membus.reqLayer6.occupancy 17698783999 # Layer occupancy (ticks)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.membus.respLayer1.occupancy 5007965719 # Layer occupancy (ticks)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.membus.respLayer2.occupancy 37372928091 # Layer occupancy (ticks)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.membus.respLayer2.utilization 1.4 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.l2c.tags.replacements 91666 # number of replacements
system.l2c.tags.tagsinuse 54831.199714 # Cycle average of tags in use
system.l2c.tags.total_refs 387443 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 156491 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 2.475817 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.l2c.tags.occ_blocks::writebacks 7736.589041 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.331203 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 1.025467 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 672.803532 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 1677.780077 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 24285.244228 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.407687 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 678.722766 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 3493.963497 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 16278.332216 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.118051 # Average percentage of cache occupancy
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000020 # Average percentage of cache occupancy
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.010266 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.025601 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.370563 # Average percentage of cache occupancy
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000083 # Average percentage of cache occupancy
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.l2c.tags.occ_percent::cpu1.inst 0.010356 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.053314 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.248388 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.836658 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022 52524 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 12291 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2 158 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3 5897 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4 46469 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 327 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 2272 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 9679 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022 0.801453 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023 0.000153 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.187546 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 5049935 # Number of tag accesses
system.l2c.tags.data_accesses 5049935 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 116 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 44 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 4746 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 14884 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 72204 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 168 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 72 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 7407 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 16636 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 74707 # number of ReadReq hits
system.l2c.ReadReq_hits::total 190984 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 213987 # number of Writeback hits
system.l2c.Writeback_hits::total 213987 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 3107 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 2045 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 5152 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 90 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 245 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 335 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 1803 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 2746 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 4549 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 116 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 44 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 4746 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 16687 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher 72204 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 168 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 72 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 7407 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 19382 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher 74707 # number of demand (read+write) hits
system.l2c.demand_hits::total 195533 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 116 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 44 # number of overall hits
system.l2c.overall_hits::cpu0.inst 4746 # number of overall hits
system.l2c.overall_hits::cpu0.data 16687 # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher 72204 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 168 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 72 # number of overall hits
system.l2c.overall_hits::cpu1.inst 7407 # number of overall hits
system.l2c.overall_hits::cpu1.data 19382 # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher 74707 # number of overall hits
system.l2c.overall_hits::total 195533 # number of overall hits
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.ReadReq_misses::cpu0.dtb.walker 3 # number of ReadReq misses
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 1063 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 3259 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 72015 # number of ReadReq misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.ReadReq_misses::cpu1.dtb.walker 8 # number of ReadReq misses
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.l2c.ReadReq_misses::cpu1.inst 1104 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 4621 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 84097 # number of ReadReq misses
system.l2c.ReadReq_misses::total 166173 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 7830 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 5610 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 13440 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 1272 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 1187 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 2459 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 3945 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 5092 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 9037 # number of ReadExReq misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.demand_misses::cpu0.dtb.walker 3 # number of demand (read+write) misses
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 1063 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 7204 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher 72015 # number of demand (read+write) misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.demand_misses::cpu1.dtb.walker 8 # number of demand (read+write) misses
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.l2c.demand_misses::cpu1.inst 1104 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 9713 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher 84097 # number of demand (read+write) misses
system.l2c.demand_misses::total 175210 # number of demand (read+write) misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.overall_misses::cpu0.dtb.walker 3 # number of overall misses
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses
system.l2c.overall_misses::cpu0.inst 1063 # number of overall misses
system.l2c.overall_misses::cpu0.data 7204 # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher 72015 # number of overall misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.overall_misses::cpu1.dtb.walker 8 # number of overall misses
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.l2c.overall_misses::cpu1.inst 1104 # number of overall misses
system.l2c.overall_misses::cpu1.data 9713 # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher 84097 # number of overall misses
system.l2c.overall_misses::total 175210 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 195250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 182000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst 88517249 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 251848999 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 6854006378 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 744500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 96486500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 359268498 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 9492494272 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 17143743646 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 12214974 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 6369731 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 18584705 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 508980 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 4358314 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 4867294 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 294129193 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 380271953 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 674401146 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 195250 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 182000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 88517249 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 545978192 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 6854006378 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 744500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 96486500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 739540451 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 9492494272 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 17818144792 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 195250 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 182000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 88517249 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 545978192 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 6854006378 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 744500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 96486500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 739540451 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 9492494272 # number of overall miss cycles
system.l2c.overall_miss_latency::total 17818144792 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 119 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 47 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 5809 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 18143 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 144219 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 176 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 72 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 8511 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 21257 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 158804 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 357157 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 213987 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 213987 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 10937 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 7655 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 18592 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 1362 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 1432 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 2794 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 5748 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 7838 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 13586 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 119 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 47 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 5809 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 23891 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher 144219 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 176 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 72 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 8511 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 29095 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher 158804 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 370743 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 119 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 47 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 5809 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 23891 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher 144219 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 176 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 72 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 8511 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 29095 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher 158804 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 370743 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.025210 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.063830 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.182992 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.179629 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.499345 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.129714 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.217387 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.529565 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.465266 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.715918 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.732854 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.722892 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.933921 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.828911 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.880100 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.686326 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.649656 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.665170 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.025210 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.063830 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.182992 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.301536 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.499345 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.129714 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.333837 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.529565 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.472592 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.025210 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.063830 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.182992 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.301536 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.499345 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.129714 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.333837 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.529565 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.472592 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 65083.333333 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 60666.666667 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 83271.165569 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 77277.999079 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 95174.704964 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 93062.500000 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 87397.192029 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 77746.915819 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 112875.539817 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 103168.045627 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1560.022222 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1135.424421 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 1382.790551 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 400.141509 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 3671.705139 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 1979.379423 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 74557.463371 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 74680.273566 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 74626.662167 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 65083.333333 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 60666.666667 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 83271.165569 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 75788.199889 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 95174.704964 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 93062.500000 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 87397.192029 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 76139.241326 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 112875.539817 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 101695.935118 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 65083.333333 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 60666.666667 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 83271.165569 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 75788.199889 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 95174.704964 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 93062.500000 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 87397.192029 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 76139.241326 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 112875.539817 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 101695.935118 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 369 # number of cycles access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.l2c.blocked::no_mshrs 10 # number of cycles access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.l2c.avg_blocked_cycles::no_mshrs 36.900000 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.l2c.writebacks::writebacks 68618 # number of writebacks
system.l2c.writebacks::total 68618 # number of writebacks
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 3 # number of ReadReq MSHR misses
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst 1063 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 3259 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 72015 # number of ReadReq MSHR misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 8 # number of ReadReq MSHR misses
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.l2c.ReadReq_mshr_misses::cpu1.inst 1104 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 4621 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 84097 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 166173 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 7830 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 5610 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 13440 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1272 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1187 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 2459 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 3945 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 5092 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 9037 # number of ReadExReq MSHR misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.demand_mshr_misses::cpu0.dtb.walker 3 # number of demand (read+write) MSHR misses
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 1063 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 7204 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 72015 # number of demand (read+write) MSHR misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.demand_mshr_misses::cpu1.dtb.walker 8 # number of demand (read+write) MSHR misses
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.l2c.demand_mshr_misses::cpu1.inst 1104 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 9713 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 84097 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 175210 # number of demand (read+write) MSHR misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.overall_mshr_misses::cpu0.dtb.walker 3 # number of overall MSHR misses
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 1063 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 7204 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 72015 # number of overall MSHR misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.overall_mshr_misses::cpu1.dtb.walker 8 # number of overall MSHR misses
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.l2c.overall_mshr_misses::cpu1.inst 1104 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 9713 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 84097 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 175210 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 158750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 145000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 75361749 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 211101499 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 5961474378 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 645000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 82874000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 301675998 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 8458010282 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 15091446656 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 79003615 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 56662566 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 135666181 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 12832754 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 11966179 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 24798933 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 244772807 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 316260047 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 561032854 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 158750 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 145000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 75361749 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 455874306 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 5961474378 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 645000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 82874000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 617936045 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 8458010282 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 15652479510 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 158750 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 145000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 75361749 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 455874306 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 5961474378 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 645000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 82874000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 617936045 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 8458010282 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 15652479510 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 178129250 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12343853503 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3278250 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154953535743 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 167478796746 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1076363997 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16025248776 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 17101612773 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 178129250 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13420217500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3278250 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 170978784519 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 184580409519 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.025210 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.063830 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.182992 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.179629 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.499345 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.045455 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.129714 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.217387 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.529565 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.465266 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.715918 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.732854 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.722892 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.933921 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.828911 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.880100 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.686326 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.649656 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.665170 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.025210 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.063830 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.182992 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.301536 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.499345 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.045455 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.129714 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.333837 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.529565 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.472592 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.025210 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.063830 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.182992 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.301536 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.499345 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.045455 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.129714 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.333837 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.529565 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.472592 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 52916.666667 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48333.333333 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 70895.342427 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 64774.930654 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82781.009206 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 80625 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 75067.028986 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65283.704393 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100574.459041 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 90817.681910 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10089.861430 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10100.279144 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10094.209896 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10088.643082 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10081.026959 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10084.966653 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 62046.338910 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62109.200118 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 62081.758770 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 52916.666667 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48333.333333 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70895.342427 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 63280.719878 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82781.009206 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80625 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75067.028986 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63619.483682 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100574.459041 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 89335.537412 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 52916.666667 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48333.333333 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70895.342427 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 63280.719878 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82781.009206 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80625 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75067.028986 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63619.483682 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100574.459041 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 89335.537412 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.toL2Bus.trans_dist::ReadReq 1650974 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 1650974 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 769202 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 769202 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 213987 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 63464 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 24002 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 87466 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp 45 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 23286 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 23286 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 760669 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4337396 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 5098065 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 18146443 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 24785598 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 42932041 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 177868 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 783993 # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.toL2Bus.snoop_fanout::1 783993 100.00% 100.00% # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.toL2Bus.snoop_fanout::total 783993 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 2614417508 # Layer occupancy (ticks)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.toL2Bus.respLayer0.occupancy 1150691896 # Layer occupancy (ticks)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.toL2Bus.respLayer1.occupancy 2659939258 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.iobus.trans_dist::ReadReq 16322916 # Transaction distribution
system.iobus.trans_dist::ReadResp 16322916 # Transaction distribution
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iobus.trans_dist::WriteReq 8084 # Transaction distribution
system.iobus.trans_dist::WriteResp 8084 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30946 # Packet count per connected master and slave (bytes)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8832 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 740 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.iobus.pkt_count_system.bridge.master::total 2384368 # Packet count per connected master and slave (bytes)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.iobus.pkt_count::total 32662000 # Packet count per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40715 # Cumulative packet size per connected master and slave (bytes)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17664 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 394 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.iobus.pkt_size_system.bridge.master::total 2392677 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.iobus.pkt_size::total 123503205 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iobus.reqLayer0.occupancy 21715000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.iobus.reqLayer1.occupancy 4422000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iobus.reqLayer3.occupancy 522000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iobus.reqLayer6.occupancy 442000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.iobus.respLayer0.occupancy 2376284000 # Layer occupancy (ticks)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.iobus.respLayer1.occupancy 38188943909 # Layer occupancy (ticks)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.branchPred.lookups 6445077 # Number of BP lookups
system.cpu0.branchPred.condPredicted 4515785 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 302094 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 3732049 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 2838132 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.branchPred.BTBHitPct 76.047555 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 777958 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 15130 # Number of incorrect RAS predictions.
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.dtb.read_hits 6738270 # DTB read hits
system.cpu0.dtb.read_misses 20792 # DTB read misses
system.cpu0.dtb.write_hits 5108254 # DTB write hits
system.cpu0.dtb.write_misses 4938 # DTB write misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.dtb.flush_entries 1733 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 361 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.dtb.perms_faults 640 # Number of TLB faults due to permissions restrictions
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.dtb.read_accesses 6759062 # DTB read accesses
system.cpu0.dtb.write_accesses 5113192 # DTB write accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.dtb.hits 11846524 # DTB hits
system.cpu0.dtb.misses 25730 # DTB misses
system.cpu0.dtb.accesses 11872254 # DTB accesses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.itb.inst_hits 11251934 # ITB inst hits
system.cpu0.itb.inst_misses 5844 # ITB inst misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.itb.flush_entries 1215 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.itb.perms_faults 2392 # Number of TLB faults due to permissions restrictions
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.itb.inst_accesses 11257778 # ITB inst accesses
system.cpu0.itb.hits 11251934 # DTB hits
system.cpu0.itb.misses 5844 # DTB misses
system.cpu0.itb.accesses 11257778 # DTB accesses
system.cpu0.numCycles 70547986 # number of cpu cycles simulated
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.fetch.icacheStallCycles 4766943 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 34365037 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 6445077 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 3616090 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 61724532 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 827468 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 75473 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 31308 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 103372 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 2299403 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 9118 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 11252710 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 69213 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 1641 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 69423883 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 0.597378 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 1.081788 # Number of instructions fetched each cycle (Total)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.fetch.rateDist::0 50336190 72.51% 72.51% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 6591848 9.50% 82.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 2607109 3.76% 85.76% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 9888736 14.24% 100.00% # Number of instructions fetched each cycle (Total)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.fetch.rateDist::total 69423883 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.091357 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.487116 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 6423281 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 48508889 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 12244404 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 1928072 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 319237 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 872011 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 96101 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 34918059 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 1200237 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 319237 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 8391286 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 22294228 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 11033133 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 12128468 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 15257531 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 33562016 # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts 347139 # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents 4725852 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 2951017 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents 10590659 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 2752771 # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands 34856617 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 154488080 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 39935090 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 3818 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 30135138 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 4721470 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 454498 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 374192 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 4720858 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 6116778 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 5560819 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 585791 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 708239 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 32317524 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 796272 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 32794597 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 169276 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 3620256 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 7615411 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 145849 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 69423883 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.472382 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 0.871380 # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.iq.issued_per_cycle::0 50273243 72.41% 72.41% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 9200980 13.25% 85.67% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 6622047 9.54% 95.21% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 2961360 4.27% 99.47% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 365822 0.53% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 431 0.00% 100.00% # Number of insts issued each cycle
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.iq.issued_per_cycle::total 69423883 # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.iq.fu_full::IntAlu 2899348 33.55% 33.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 364 0.00% 33.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 33.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 33.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 33.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 33.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 33.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 33.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 33.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 33.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 33.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 33.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 33.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 33.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 33.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 33.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 33.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 33.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 33.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 33.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 33.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 33.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 33.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 33.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 33.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 33.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 33.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 33.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 2954493 34.19% 67.74% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 2788370 32.26% 100.00% # attempts to use FU when none available
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.iq.FU_type_0::No_OpClass 14544 0.04% 0.04% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 20241553 61.72% 61.77% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 42703 0.13% 61.90% # Type of FU issued
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 61.90% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 61.90% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 61.90% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 61.90% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 61.90% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 61.90% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 61.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 61.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 61.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 61.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 61.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 61.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 61.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 61.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 61.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 61.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 61.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.90% # Type of FU issued
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.iq.FU_type_0::SimdFloatMisc 684 0.00% 61.90% # Type of FU issued
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 61.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.90% # Type of FU issued
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.iq.FU_type_0::MemRead 7058068 21.52% 83.42% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 5437045 16.58% 100.00% # Type of FU issued
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.iq.FU_type_0::total 32794597 # Type of FU issued
system.cpu0.iq.rate 0.464855 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 8642575 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.263537 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 143812961 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 36735702 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 31078347 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 11966 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 4590 # Number of floating instruction queue writes
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu0.iq.fp_inst_queue_wakeup_accesses 3838 # Number of floating instruction queue wakeup accesses
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.iq.int_alu_accesses 41415013 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 7615 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 165813 # Number of loads that had data forwarded from stores
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.iew.lsq.thread0.squashedLoads 774144 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 762 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 6359 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 332945 # Number of stores squashed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.iew.lsq.thread0.rescheduledLoads 1087991 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 169554 # Number of times an access to memory failed due to the cache being blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.iew.iewSquashCycles 319237 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 7637691 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 6668537 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 33216242 # Number of instructions dispatched to IQ
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.iew.iewDispLoadInsts 6116778 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 5560819 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 485296 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 10796 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 6648479 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 6359 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 101328 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 128415 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 229743 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 32427250 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 6903411 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 342013 # Number of squashed instructions skipped in execute
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.exec_swp 0 # number of swp insts executed
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.iew.exec_nop 102446 # number of nop insts executed
system.cpu0.iew.exec_refs 12283212 # number of memory reference insts executed
system.cpu0.iew.exec_branches 4700114 # Number of branches executed
system.cpu0.iew.exec_stores 5379801 # Number of stores executed
system.cpu0.iew.exec_rate 0.459648 # Inst execution rate
system.cpu0.iew.wb_sent 32232102 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 31082185 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 15739944 # num instructions producing a value
system.cpu0.iew.wb_consumers 27168343 # num instructions consuming a value
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.iew.wb_rate 0.440582 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.579349 # average fanout of values written-back
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.commit.commitSquashedInsts 3250105 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 650423 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 207597 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 68788504 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.427377 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.179796 # Number of insts commited each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.commit.committed_per_cycle::0 54880088 79.78% 79.78% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 7965099 11.58% 91.36% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 2563469 3.73% 95.09% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 1116854 1.62% 96.71% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 779155 1.13% 97.84% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 426783 0.62% 98.46% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 259327 0.38% 98.84% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 232321 0.34% 99.18% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 565408 0.82% 100.00% # Number of insts commited each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.commit.committed_per_cycle::total 68788504 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 24068410 # Number of instructions committed
system.cpu0.commit.committedOps 29398607 # Number of ops (including micro ops) committed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.commit.refs 10570507 # Number of memory references committed
system.cpu0.commit.loads 5342633 # Number of loads committed
system.cpu0.commit.membars 231974 # Number of memory barriers committed
system.cpu0.commit.branches 4351471 # Number of branches committed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions.
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.commit.int_insts 25743783 # Number of committed integer instructions.
system.cpu0.commit.function_calls 499778 # Number of function calls committed.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.commit.op_class_0::IntAlu 18787662 63.91% 63.91% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 39754 0.14% 64.04% # Class of committed instruction
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 64.04% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 64.04% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 64.04% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 64.04% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 64.04% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 64.04% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 64.04% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 64.04% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 64.04% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 64.04% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 64.04% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 64.04% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 64.04% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 64.04% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 64.04% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 64.04% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 64.04% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 64.04% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 64.04% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 64.04% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 64.04% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 64.04% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 64.04% # Class of committed instruction
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.commit.op_class_0::SimdFloatMisc 684 0.00% 64.04% # Class of committed instruction
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 64.04% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.04% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.04% # Class of committed instruction
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.commit.op_class_0::MemRead 5342633 18.17% 82.22% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite 5227874 17.78% 100.00% # Class of committed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.commit.op_class_0::total 29398607 # Class of committed instruction
system.cpu0.commit.bw_lim_events 565408 # number cycles where commit BW limit reached
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.rob.rob_reads 99997744 # The number of ROB reads
system.cpu0.rob.rob_writes 65895627 # The number of ROB writes
system.cpu0.timesIdled 89184 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 1124103 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 5145325170 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 23987668 # Number of Instructions Simulated
system.cpu0.committedOps 29317865 # Number of Ops (including micro ops) Simulated
system.cpu0.cpi 2.941011 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 2.941011 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.340019 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.340019 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 37156240 # number of integer regfile reads
system.cpu0.int_regfile_writes 18851805 # number of integer regfile writes
system.cpu0.fp_regfile_reads 3262 # number of floating regfile reads
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu0.fp_regfile_writes 840 # number of floating regfile writes
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.cc_regfile_reads 113767432 # number of cc regfile reads
system.cpu0.cc_regfile_writes 12814569 # number of cc regfile writes
system.cpu0.misc_regfile_reads 112163009 # number of misc regfile reads
system.cpu0.misc_regfile_writes 502202 # number of misc regfile writes
system.cpu0.toL2Bus.trans_dist::ReadReq 900797 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 693938 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 10818 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 10818 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback 228050 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq 268938 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 56335 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 24640 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 62766 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 29 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 45 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 133470 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 124418 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 651974 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1223749 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 16358 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 46407 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 1938488 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20698608 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 38615195 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 26900 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 80012 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 59420715 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 640729 # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples 1524410 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 5.372076 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.483359 # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.toL2Bus.snoop_fanout::5 957213 62.79% 62.79% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::6 567197 37.21% 100.00% # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.toL2Bus.snoop_fanout::total 1524410 # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy 761732905 # Layer occupancy (ticks)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.toL2Bus.snoopLayer0.occupancy 71201999 # Layer occupancy (ticks)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.toL2Bus.respLayer0.occupancy 488672410 # Layer occupancy (ticks)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.toL2Bus.respLayer1.occupancy 613319434 # Layer occupancy (ticks)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.toL2Bus.respLayer2.occupancy 9639487 # Layer occupancy (ticks)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.toL2Bus.respLayer3.occupancy 26428702 # Layer occupancy (ticks)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.icache.tags.replacements 322116 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.545879 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 10915164 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 322628 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 33.832042 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 6524367000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.545879 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999113 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999113 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.icache.tags.tag_accesses 22821148 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 22821148 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 10915164 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 10915164 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 10915164 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 10915164 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 10915164 # number of overall hits
system.cpu0.icache.overall_hits::total 10915164 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 334091 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 334091 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 334091 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 334091 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 334091 # number of overall misses
system.cpu0.icache.overall_misses::total 334091 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 2863305358 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 2863305358 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 2863305358 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 2863305358 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 2863305358 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 2863305358 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 11249255 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 11249255 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 11249255 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 11249255 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 11249255 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 11249255 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029699 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.029699 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029699 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.029699 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029699 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.029699 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8570.435474 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 8570.435474 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8570.435474 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 8570.435474 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8570.435474 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 8570.435474 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 177531 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 307 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 22346 # number of cycles access was blocked
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.icache.blocked::no_targets 5 # number of cycles access was blocked
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.944643 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets 61.400000 # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 11453 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 11453 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 11453 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 11453 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 11453 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 11453 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 322638 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 322638 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 322638 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 322638 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 322638 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 322638 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 2310628588 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 2310628588 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 2310628588 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 2310628588 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 2310628588 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 2310628588 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 272886999 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 272886999 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 272886999 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 272886999 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028681 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028681 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028681 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.028681 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028681 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.028681 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7161.675277 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7161.675277 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7161.675277 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 7161.675277 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7161.675277 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 7161.675277 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 3529222 # number of hwpf identified
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 247992 # number of hwpf that were already in mshr
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 2979692 # number of hwpf that were already in the cache
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 86609 # number of hwpf that were already in the prefetch queue
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 16144 # number of hwpf removed because MSHR allocated
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 198785 # number of hwpf issued
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 261906 # number of hwpf spanning a virtual page
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.l2cache.tags.replacements 165160 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 15951.411231 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 747099 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 181321 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 4.120311 # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle 4999805500 # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 4772.372752 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 11.637155 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.084033 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 735.053900 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1518.442449 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8912.820942 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.291283 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000710 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000066 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.044864 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.092678 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.543995 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.973597 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 7338 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 12 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8811 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 34 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 105 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1027 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5229 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 943 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 485 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1656 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6017 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 598 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.447876 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000732 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.537781 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 15517001 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 15517001 # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 19658 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 6554 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.inst 314769 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.data 162769 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 503750 # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks 228045 # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total 228045 # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 6593 # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total 6593 # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 622 # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total 622 # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 95529 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 95529 # number of ReadExReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 19658 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 6554 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 314769 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 258298 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 599279 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 19658 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 6554 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 314769 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data 258298 # number of overall hits
system.cpu0.l2cache.overall_hits::total 599279 # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 345 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 171 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.inst 7801 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.data 50805 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total 59122 # number of ReadReq misses
system.cpu0.l2cache.Writeback_misses::writebacks 5 # number of Writeback misses
system.cpu0.l2cache.Writeback_misses::total 5 # number of Writeback misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 19680 # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total 19680 # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 10856 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total 10856 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 23597 # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total 23597 # number of ReadExReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 345 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 171 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst 7801 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data 74402 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total 82719 # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 345 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 171 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst 7801 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data 74402 # number of overall misses
system.cpu0.l2cache.overall_misses::total 82719 # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 7498249 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3753000 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 255179729 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 1303745054 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total 1570176032 # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 310997961 # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total 310997961 # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 212766148 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 212766148 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 609000 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 609000 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 893661798 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total 893661798 # number of ReadExReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 7498249 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3753000 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst 255179729 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data 2197406852 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total 2463837830 # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 7498249 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3753000 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst 255179729 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data 2197406852 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total 2463837830 # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 20003 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 6725 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 322570 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.data 213574 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total 562872 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks 228050 # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total 228050 # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26273 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total 26273 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 11478 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total 11478 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 119126 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total 119126 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 20003 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 6725 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst 322570 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data 332700 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total 681998 # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 20003 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 6725 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst 322570 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data 332700 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total 681998 # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.017247 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.025428 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.024184 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.237880 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total 0.105036 # miss rate for ReadReq accesses
system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000022 # miss rate for Writeback accesses
system.cpu0.l2cache.Writeback_miss_rate::total 0.000022 # miss rate for Writeback accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.749058 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.749058 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.945809 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.945809 # miss rate for SCUpgradeReq accesses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.198084 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.198084 # miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.017247 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.025428 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.024184 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.223631 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total 0.121289 # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.017247 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.025428 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.024184 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.223631 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total 0.121289 # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 21734.055072 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 21947.368421 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 32711.156134 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 25661.746954 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26558.236054 # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 15802.741921 # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 15802.741921 # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19598.945099 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19598.945099 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 609000 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 609000 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 37871.839556 # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 37871.839556 # average ReadExReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 21734.055072 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 21947.368421 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 32711.156134 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29534.244402 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 29785.633651 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 21734.055072 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 21947.368421 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 32711.156134 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29534.244402 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 29785.633651 # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs 4781 # number of cycles access was blocked
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.l2cache.blocked::no_mshrs 266 # number of cycles access was blocked
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 17.973684 # average number of cycles each access was blocked
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.l2cache.writebacks::writebacks 105131 # number of writebacks
system.cpu0.l2cache.writebacks::total 105131 # number of writebacks
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 1845 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 997 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total 2844 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 936 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total 936 # number of ReadExReq MSHR hits
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 1845 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1933 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total 3780 # number of demand (read+write) MSHR hits
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 1845 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1933 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total 3780 # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 344 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 170 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 5956 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 49808 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total 56278 # number of ReadReq MSHR misses
system.cpu0.l2cache.Writeback_mshr_misses::writebacks 5 # number of Writeback MSHR misses
system.cpu0.l2cache.Writeback_mshr_misses::total 5 # number of Writeback MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 198779 # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total 198779 # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 19680 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total 19680 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 10856 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 10856 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 22661 # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total 22661 # number of ReadExReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 344 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 170 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 5956 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data 72469 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total 78939 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 344 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 170 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 5956 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data 72469 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 198779 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total 277718 # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 5004751 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2550500 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 181100759 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 940424592 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1129080602 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 8151036272 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 8151036272 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 354005766 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 354005766 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 158485722 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 158485722 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 490000 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 490000 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 601346170 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 601346170 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 5004751 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2550500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 181100759 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 1541770762 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total 1730426772 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 5004751 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2550500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 181100759 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 1541770762 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 8151036272 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 9881463044 # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 244240750 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 13865359008 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 14109599758 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 1262027985 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 1262027985 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 244240750 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 15127386993 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15371627743 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.017197 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.025279 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.018464 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.233212 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.099984 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000022 # mshr miss rate for Writeback accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000022 # mshr miss rate for Writeback accesses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.749058 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.749058 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.945809 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.945809 # mshr miss rate for SCUpgradeReq accesses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.190227 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.190227 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.017197 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.025279 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.018464 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.217821 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.115747 # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.017197 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.025279 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.018464 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.217821 # mshr miss rate for overall accesses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.407212 # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14548.694767 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15002.941176 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 30406.440396 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 18880.994860 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20062.557340 # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41005.520060 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41005.520060 # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17988.097866 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17988.097866 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14598.905859 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14598.905859 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 490000 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 490000 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 26536.612241 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 26536.612241 # average ReadExReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14548.694767 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15002.941176 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 30406.440396 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 21274.900468 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 21921.062745 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14548.694767 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15002.941176 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 30406.440396 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 21274.900468 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41005.520060 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35580.923973 # average overall mshr miss latency
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.dcache.tags.replacements 297335 # number of replacements
system.cpu0.dcache.tags.tagsinuse 469.059398 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 9029469 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 297847 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 30.315796 # Average number of references to valid blocks.
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.dcache.tags.warmup_cycle 284699500 # Cycle when the warmup percentage was hit.
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 469.059398 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.916132 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.916132 # Average percentage of cache occupancy
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.dcache.tags.tag_accesses 20887113 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 20887113 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 4736171 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 4736171 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3900194 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 3900194 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 45240 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 45240 # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 135351 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 135351 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 133505 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 133505 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 8636365 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 8636365 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 8681605 # number of overall hits
system.cpu0.dcache.overall_hits::total 8681605 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 322447 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 322447 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 906986 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 906986 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 75027 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 75027 # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10798 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 10798 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 11479 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 11479 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 1229433 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 1229433 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 1304460 # number of overall misses
system.cpu0.dcache.overall_misses::total 1304460 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3662752641 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 3662752641 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 13080008270 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 13080008270 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 182730500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 182730500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 273467244 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 273467244 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 660000 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 660000 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 16742760911 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 16742760911 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 16742760911 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 16742760911 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 5058618 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 5058618 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4807180 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 4807180 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 120267 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 120267 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 146149 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 146149 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144984 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 144984 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 9865798 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 9865798 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 9986065 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 9986065 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063742 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.063742 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.188673 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.188673 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.623837 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.623837 # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.073884 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.073884 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.079174 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.079174 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.124616 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.124616 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.130628 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.130628 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 11359.239320 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 11359.239320 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14421.400408 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 14421.400408 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16922.624560 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16922.624560 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23823.263699 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23823.263699 # average StoreCondReq miss latency
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13618.278435 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 13618.278435 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12835.012887 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 12835.012887 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 1895359 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 9 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 100025 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 18.948853 # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.dcache.writebacks::writebacks 228050 # number of writebacks
system.cpu0.dcache.writebacks::total 228050 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 162419 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 162419 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 762846 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 762846 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 1187 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1187 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 925265 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 925265 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 925265 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 925265 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 160028 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 160028 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 144140 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 144140 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 44124 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 44124 # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9611 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9611 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 11479 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 11479 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 304168 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 304168 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 348292 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 348292 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1657269084 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1657269084 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 2153079279 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2153079279 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 708295495 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 708295495 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 147083500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 147083500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 249287756 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 249287756 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 626000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 626000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 3810348363 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 3810348363 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 4518643858 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 4518643858 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 14541407491 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 14541407491 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1345528496 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1345528496 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 15886935987 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 15886935987 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031635 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031635 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029984 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029984 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.366884 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.366884 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.065762 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.065762 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.079174 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.079174 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030831 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.030831 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.034878 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.034878 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10356.119454 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10356.119454 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14937.416949 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14937.416949 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16052.386343 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16052.386343 # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15303.662470 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15303.662470 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21716.853036 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21716.853036 # average StoreCondReq mshr miss latency
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12527.117787 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12527.117787 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12973.722790 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12973.722790 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.branchPred.lookups 9149866 # Number of BP lookups
system.cpu1.branchPred.condPredicted 6786400 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 422129 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 5825788 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 4286605 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.branchPred.BTBHitPct 73.579832 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 927303 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 19424 # Number of incorrect RAS predictions.
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.dtb.read_hits 25102636 # DTB read hits
system.cpu1.dtb.read_misses 30137 # DTB read misses
system.cpu1.dtb.write_hits 6841685 # DTB write hits
system.cpu1.dtb.write_misses 6769 # DTB write misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.dtb.flush_entries 1912 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 1186 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 224 # Number of TLB faults due to prefetch
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.dtb.perms_faults 731 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 25132773 # DTB read accesses
system.cpu1.dtb.write_accesses 6848454 # DTB write accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.dtb.hits 31944321 # DTB hits
system.cpu1.dtb.misses 36906 # DTB misses
system.cpu1.dtb.accesses 31981227 # DTB accesses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.itb.inst_hits 16803682 # ITB inst hits
system.cpu1.itb.inst_misses 6173 # ITB inst misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.itb.flush_entries 1327 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.itb.perms_faults 2309 # Number of TLB faults due to permissions restrictions
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.itb.inst_accesses 16809855 # ITB inst accesses
system.cpu1.itb.hits 16803682 # DTB hits
system.cpu1.itb.misses 6173 # DTB misses
system.cpu1.itb.accesses 16809855 # DTB accesses
system.cpu1.numCycles 436917069 # number of cpu cycles simulated
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.fetch.icacheStallCycles 7779761 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 51586006 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 9149866 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 5213908 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 424935366 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 1119898 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 77514 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles 41827 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles 113975 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 2395843 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 15405 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 16801187 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 110293 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 1839 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 435919640 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 0.141195 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 0.582401 # Number of instructions fetched each cycle (Total)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.fetch.rateDist::0 407581344 93.50% 93.50% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 9416514 2.16% 95.66% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 4632400 1.06% 96.72% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 14289382 3.28% 100.00% # Number of instructions fetched each cycle (Total)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.fetch.rateDist::total 435919640 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.020942 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.118068 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 9900868 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 404219752 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 17609153 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 3776585 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 413282 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 1053225 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 148821 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 53082842 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 1693858 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 413282 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 13042184 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 210392870 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 23473030 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 17900158 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 170698116 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 51361658 # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts 445811 # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents 60462789 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 44486963 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents 161544271 # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents 5689953 # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands 54453588 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 239756743 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 64654520 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 6270 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 48767925 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 5685663 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 754764 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 650155 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 9515727 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 9671211 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 7398216 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 539915 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 877439 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 49754499 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 1063600 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 65146152 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 226823 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 4308815 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 9268536 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 164257 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 435919640 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.149445 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 0.502702 # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.iq.issued_per_cycle::0 391740283 89.87% 89.87% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 28930464 6.64% 96.50% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 10221316 2.34% 98.85% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 4337467 1.00% 99.84% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 689895 0.16% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 215 0.00% 100.00% # Number of insts issued each cycle
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.iq.issued_per_cycle::total 435919640 # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.iq.fu_full::IntAlu 4426779 17.51% 17.51% # attempts to use FU when none available
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.iq.fu_full::IntMult 691 0.00% 17.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 17.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 17.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 17.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 17.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 17.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 17.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 17.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 17.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 17.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 17.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 17.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 17.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 17.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 17.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 17.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 17.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 17.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 17.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 17.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 17.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 17.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 17.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 17.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 17.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 17.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 17.51% # attempts to use FU when none available
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.iq.fu_full::MemRead 17782110 70.33% 87.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 3074512 12.16% 100.00% # attempts to use FU when none available
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.iq.FU_type_0::No_OpClass 14260 0.02% 0.02% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 32351105 49.66% 49.68% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 60186 0.09% 49.77% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.77% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.77% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.77% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.77% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.77% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.77% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.77% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.77% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.77% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.77% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.77% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.77% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.77% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.77% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.77% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.77% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.77% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.77% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.77% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.77% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.77% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.77% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.77% # Type of FU issued
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.iq.FU_type_0::SimdFloatMisc 1702 0.00% 49.78% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.78% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.78% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.78% # Type of FU issued
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.iq.FU_type_0::MemRead 25491005 39.13% 88.91% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 7227894 11.09% 100.00% # Type of FU issued
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.iq.FU_type_0::total 65146152 # Type of FU issued
system.cpu1.iq.rate 0.149104 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 25284092 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.388113 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 591701467 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 55128847 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 48339304 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 21392 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 7974 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 6777 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 90402329 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 13655 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 164874 # Number of loads that had data forwarded from stores
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.iew.lsq.thread0.squashedLoads 922858 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 700 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 9957 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 405915 # Number of stores squashed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.iew.lsq.thread0.rescheduledLoads 16016509 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 155340 # Number of times an access to memory failed due to the cache being blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.iew.iewSquashCycles 413282 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 90103879 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 101302025 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 50907640 # Number of instructions dispatched to IQ
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.iew.iewDispLoadInsts 9671211 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 7398216 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 775761 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 15322 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 101224655 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 9957 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 133208 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 167801 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 301009 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 64655254 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 25297716 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 454169 # Number of squashed instructions skipped in execute
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.exec_swp 0 # number of swp insts executed
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.iew.exec_nop 89541 # number of nop insts executed
system.cpu1.iew.exec_refs 32443779 # number of memory reference insts executed
system.cpu1.iew.exec_branches 6846575 # Number of branches executed
system.cpu1.iew.exec_stores 7146063 # Number of stores executed
system.cpu1.iew.exec_rate 0.147981 # Inst execution rate
system.cpu1.iew.wb_sent 64439493 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 48346081 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 25811466 # num instructions producing a value
system.cpu1.iew.wb_consumers 39458467 # num instructions consuming a value
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.iew.wb_rate 0.110653 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.654143 # average fanout of values written-back
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.commit.commitSquashedInsts 3859068 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 899343 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 275462 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 435139005 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.106498 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 0.626723 # Number of insts commited each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.commit.committed_per_cycle::0 413392451 95.00% 95.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 12955608 2.98% 97.98% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 3521257 0.81% 98.79% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 1360882 0.31% 99.10% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 1313314 0.30% 99.40% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 777449 0.18% 99.58% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 559175 0.13% 99.71% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 305729 0.07% 99.78% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 953140 0.22% 100.00% # Number of insts commited each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.commit.committed_per_cycle::total 435139005 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 38843249 # Number of instructions committed
system.cpu1.commit.committedOps 46341542 # Number of ops (including micro ops) committed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.commit.refs 15740654 # Number of memory references committed
system.cpu1.commit.loads 8748353 # Number of loads committed
system.cpu1.commit.membars 195273 # Number of memory barriers committed
system.cpu1.commit.branches 6419002 # Number of branches committed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions.
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.commit.int_insts 41058956 # Number of committed integer instructions.
system.cpu1.commit.function_calls 553431 # Number of function calls committed.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.commit.op_class_0::IntAlu 30541068 65.90% 65.90% # Class of committed instruction
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.commit.op_class_0::IntMult 58118 0.13% 66.03% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 0 0.00% 66.03% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 66.03% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 66.03% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 66.03% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 66.03% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 66.03% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 66.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 66.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 66.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 66.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 66.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 66.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 66.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 66.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 66.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 66.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 66.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 66.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 66.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 66.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 66.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 66.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 66.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc 1702 0.00% 66.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 66.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.03% # Class of committed instruction
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.commit.op_class_0::MemRead 8748353 18.88% 84.91% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite 6992301 15.09% 100.00% # Class of committed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.commit.op_class_0::total 46341542 # Class of committed instruction
system.cpu1.commit.bw_lim_events 953140 # number cycles where commit BW limit reached
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.rob.rob_reads 483317632 # The number of ROB reads
system.cpu1.rob.rob_writes 101136219 # The number of ROB writes
system.cpu1.timesIdled 117466 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 997429 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 4778390126 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 38773610 # Number of Instructions Simulated
system.cpu1.committedOps 46271903 # Number of Ops (including micro ops) Simulated
system.cpu1.cpi 11.268413 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 11.268413 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.088744 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.088744 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 76047297 # number of integer regfile reads
system.cpu1.int_regfile_writes 30995697 # number of integer regfile writes
system.cpu1.fp_regfile_reads 4960 # number of floating regfile reads
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu1.fp_regfile_writes 2260 # number of floating regfile writes
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.cc_regfile_reads 220730482 # number of cc regfile reads
system.cpu1.cc_regfile_writes 19377985 # number of cc regfile writes
system.cpu1.misc_regfile_reads 520419201 # number of misc regfile reads
system.cpu1.misc_regfile_writes 723683 # number of misc regfile writes
system.cpu1.toL2Bus.trans_dist::ReadReq 2172606 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 1978157 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 758384 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 758384 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback 291033 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq 272197 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 56199 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 25233 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 54439 # Transaction distribution
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 45 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 157045 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 149477 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1093505 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 4944143 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17380 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 65233 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 6120261 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 34983760 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 51460526 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 28972 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 118552 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 86591810 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 595717 # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples 1871452 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 5.290652 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.454063 # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.toL2Bus.snoop_fanout::5 1327511 70.93% 70.93% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::6 543941 29.07% 100.00% # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.toL2Bus.snoop_fanout::total 1871452 # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy 2995139487 # Layer occupancy (ticks)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.toL2Bus.snoopLayer0.occupancy 46865000 # Layer occupancy (ticks)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.toL2Bus.respLayer0.occupancy 820984463 # Layer occupancy (ticks)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.toL2Bus.respLayer1.occupancy 2122961296 # Layer occupancy (ticks)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.toL2Bus.respLayer2.occupancy 10148477 # Layer occupancy (ticks)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.toL2Bus.respLayer3.occupancy 36069550 # Layer occupancy (ticks)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.icache.tags.replacements 546235 # number of replacements
system.cpu1.icache.tags.tagsinuse 498.934216 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 16238797 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 546747 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 29.700752 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 73709463000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.934216 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974481 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.974481 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.icache.tags.tag_accesses 34148852 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 34148852 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 16238797 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 16238797 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 16238797 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 16238797 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 16238797 # number of overall hits
system.cpu1.icache.overall_hits::total 16238797 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 562244 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 562244 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 562244 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 562244 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 562244 # number of overall misses
system.cpu1.icache.overall_misses::total 562244 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4743193454 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 4743193454 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 4743193454 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 4743193454 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 4743193454 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 4743193454 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 16801041 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 16801041 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 16801041 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 16801041 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 16801041 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 16801041 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033465 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.033465 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033465 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.033465 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033465 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.033465 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8436.183319 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 8436.183319 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8436.183319 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 8436.183319 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8436.183319 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 8436.183319 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 307905 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 7 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 40708 # number of cycles access was blocked
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.563747 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 15474 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 15474 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 15474 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 15474 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 15474 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 15474 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 546770 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 546770 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 546770 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 546770 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 546770 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 546770 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3839673113 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 3839673113 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3839673113 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 3839673113 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3839673113 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 3839673113 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5117249 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5117249 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5117249 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 5117249 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.032544 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.032544 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.032544 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.032544 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.032544 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.032544 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7022.464863 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7022.464863 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7022.464863 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 7022.464863 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7022.464863 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 7022.464863 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 5063185 # number of hwpf identified
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 195793 # number of hwpf that were already in mshr
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4609637 # number of hwpf that were already in the cache
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 49643 # number of hwpf that were already in the prefetch queue
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 8256 # number of hwpf removed because MSHR allocated
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 199856 # number of hwpf issued
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 430863 # number of hwpf spanning a virtual page
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.l2cache.tags.replacements 189917 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 15760.362755 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 1051721 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 205349 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 5.121627 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 2533057390500 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 4796.141133 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 17.055492 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.249384 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 825.564654 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2172.411955 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 7947.940138 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.292733 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001041 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000076 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.050388 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.132594 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.485104 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.961936 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 8428 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 6994 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2154 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 2511 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 3763 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2597 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1568 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2829 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.514404 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.426880 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 21502320 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 21502320 # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 29274 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7085 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.inst 535244 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.data 196892 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 768495 # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks 291031 # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total 291031 # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2209 # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total 2209 # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1205 # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total 1205 # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 122716 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 122716 # number of ReadExReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 29274 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7085 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 535244 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 319608 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 891211 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 29274 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7085 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 535244 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 319608 # number of overall hits
system.cpu1.l2cache.overall_hits::total 891211 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 364 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 158 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.inst 11361 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.data 60780 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 72663 # number of ReadReq misses
system.cpu1.l2cache.Writeback_misses::writebacks 2 # number of Writeback misses
system.cpu1.l2cache.Writeback_misses::total 2 # number of Writeback misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 20588 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 20588 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 13188 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 13188 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 25387 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 25387 # number of ReadExReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 364 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 158 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 11361 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 86167 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 98050 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 364 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 158 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 11361 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 86167 # number of overall misses
system.cpu1.l2cache.overall_misses::total 98050 # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 8462000 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 3365000 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 344449975 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1612650155 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total 1968927130 # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 357562229 # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total 357562229 # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 267838079 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 267838079 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1192000 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1192000 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1149303620 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total 1149303620 # number of ReadExReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 8462000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 3365000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst 344449975 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data 2761953775 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total 3118230750 # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 8462000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 3365000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst 344449975 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data 2761953775 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total 3118230750 # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 29638 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7243 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 546605 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.data 257672 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 841158 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks 291033 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total 291033 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 22797 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 22797 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 14393 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 14393 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 148103 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 148103 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 29638 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7243 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst 546605 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data 405775 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total 989261 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 29638 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7243 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst 546605 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 405775 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total 989261 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.012282 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.021814 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.020785 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.235881 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.086384 # miss rate for ReadReq accesses
system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000007 # miss rate for Writeback accesses
system.cpu1.l2cache.Writeback_miss_rate::total 0.000007 # miss rate for Writeback accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.903101 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.903101 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.916279 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.916279 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.171414 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.171414 # miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.012282 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.021814 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.020785 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.212352 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.099114 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.012282 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.021814 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.020785 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.212352 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.099114 # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23247.252747 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 21297.468354 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30318.631723 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 26532.579056 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 27096.694741 # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 17367.506752 # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 17367.506752 # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20309.226494 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20309.226494 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 596000 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 596000 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 45271.344389 # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 45271.344389 # average ReadExReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23247.252747 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 21297.468354 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30318.631723 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32053.498149 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 31802.455380 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23247.252747 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 21297.468354 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30318.631723 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32053.498149 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 31802.455380 # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs 8115 # number of cycles access was blocked
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.l2cache.blocked::no_mshrs 442 # number of cycles access was blocked
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 18.359729 # average number of cycles each access was blocked
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.l2cache.writebacks::writebacks 108849 # number of writebacks
system.cpu1.l2cache.writebacks::total 108849 # number of writebacks
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 2808 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 143 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total 2953 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1573 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total 1573 # number of ReadExReq MSHR hits
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 2808 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1716 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total 4526 # number of demand (read+write) MSHR hits
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 2808 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1716 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total 4526 # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 363 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 157 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 8553 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 60637 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total 69710 # number of ReadReq MSHR misses
system.cpu1.l2cache.Writeback_mshr_misses::writebacks 2 # number of Writeback MSHR misses
system.cpu1.l2cache.Writeback_mshr_misses::total 2 # number of Writeback MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 199848 # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total 199848 # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 20588 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total 20588 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 13188 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 13188 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 23814 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total 23814 # number of ReadExReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 363 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 157 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 8553 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data 84451 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total 93524 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 363 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 157 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 8553 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data 84451 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 199848 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total 293372 # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 5904000 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 2254500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 234181256 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1184058953 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1426398709 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 10843374528 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 10843374528 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 344645957 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 344645957 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 188520557 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 188520557 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 996000 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 996000 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 690789082 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 690789082 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 5904000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 2254500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 234181256 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 1874848035 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total 2117187791 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 5904000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 2254500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 234181256 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1874848035 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 10843374528 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 12960562319 # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4572000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 174823243259 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 174827815259 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 29484635658 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 29484635658 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 4572000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 204307878917 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 204312450917 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.012248 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.021676 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.015647 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.235326 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.082874 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000007 # mshr miss rate for Writeback accesses
system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000007 # mshr miss rate for Writeback accesses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.903101 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.903101 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.916279 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.916279 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.160794 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.160794 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.012248 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.021676 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.015647 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.208123 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.094539 # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.012248 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.021676 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.015647 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.208123 # mshr miss rate for overall accesses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.296557 # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16264.462810 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14359.872611 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27380.013562 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 19527.004189 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 20461.895123 # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 54258.108803 # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 54258.108803 # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16740.137799 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16740.137799 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14294.855702 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14294.855702 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 498000 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 498000 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29007.687999 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29007.687999 # average ReadExReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16264.462810 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14359.872611 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27380.013562 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22200.424329 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22637.908890 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16264.462810 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14359.872611 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27380.013562 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22200.424329 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 54258.108803 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 44177.911726 # average overall mshr miss latency
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.dcache.tags.replacements 381661 # number of replacements
system.cpu1.dcache.tags.tagsinuse 481.780956 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 12332117 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 381992 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 32.283705 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 70951149500 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.780956 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.940978 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.940978 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 331 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 331 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.646484 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 27770563 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 27770563 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 7205629 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 7205629 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 4858222 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 4858222 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 24502 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 24502 # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 94117 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 94117 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 93451 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 93451 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 12063851 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 12063851 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 12088353 # number of overall hits
system.cpu1.dcache.overall_hits::total 12088353 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 362275 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 362275 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 967298 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 967298 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 47536 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 47536 # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14955 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 14955 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 14395 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 14395 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 1329573 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 1329573 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 1377109 # number of overall misses
system.cpu1.dcache.overall_misses::total 1377109 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4296873688 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 4296873688 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 15627489636 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 15627489636 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 254785499 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 254785499 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 332075324 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 332075324 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1276000 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1276000 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 19924363324 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 19924363324 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 19924363324 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 19924363324 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 7567904 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 7567904 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 5825520 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 5825520 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 72038 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 72038 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 109072 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 109072 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 107846 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 107846 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 13393424 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 13393424 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 13465462 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 13465462 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.047870 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.047870 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.166045 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.166045 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.659874 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.659874 # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.137111 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.137111 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.133477 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.133477 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.099271 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.099271 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.102270 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.102270 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11860.806536 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 11860.806536 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16155.817169 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 16155.817169 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17036.810364 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17036.810364 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23068.796388 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23068.796388 # average StoreCondReq miss latency
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14985.535449 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 14985.535449 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14468.254382 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 14468.254382 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 4991 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 2160220 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 228 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 94010 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 21.890351 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets 22.978619 # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.dcache.writebacks::writebacks 291033 # number of writebacks
system.cpu1.dcache.writebacks::total 291033 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 148293 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 148293 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 797245 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 797245 # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1426 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1426 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 945538 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 945538 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 945538 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 945538 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 213982 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 213982 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 170053 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 170053 # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 30328 # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total 30328 # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13529 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13529 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 14395 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 14395 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 384035 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 384035 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 414363 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 414363 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2231950081 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2231950081 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2569103752 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2569103752 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 638180745 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 638180745 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 208910751 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 208910751 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 302166676 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 302166676 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1220000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1220000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4801053833 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 4801053833 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5439234578 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 5439234578 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 183653885735 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 183653885735 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 50893842775 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 50893842775 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 234547728510 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 234547728510 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028275 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.028275 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029191 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029191 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.421000 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.421000 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.124037 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.124037 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.133477 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.133477 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028673 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.028673 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030772 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.030772 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10430.550612 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10430.550612 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15107.664975 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15107.664975 # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21042.625462 # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21042.625462 # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15441.699387 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15441.699387 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20991.085516 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20991.085516 # average StoreCondReq mshr miss latency
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12501.604888 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12501.604888 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13126.738097 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13126.738097 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iocache.tags.replacements 0 # number of replacements
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.iocache.tags.tag_accesses 0 # Number of tag accesses
system.iocache.tags.data_accesses 0 # Number of data accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736182068909 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1736182068909 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736182068909 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1736182068909 # number of overall MSHR uncacheable cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu0.kern.inst.quiesce 42962 # number of quiesce instructions executed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.cpu1.kern.inst.quiesce 50554 # number of quiesce instructions executed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink