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gem5/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini

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ARM: Add regression tests
2010-07-27 07:03:44 +02:00
[root]
type=Root
children=system
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
full_system=false
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sim_quantum=0
Stats: Re update stats.
2011-02-08 04:23:13 +01:00
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
[system]
type=System
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
boot_osflags=a
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
cache_line_size=64
clk_domain=system.clk_domain
stats: update references
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
exit_on_work_items=false
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
init_param=0
kernel=
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
kernel_addr_check=true
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
load_addr_mask=1099511627775
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
load_offset=0
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
mem_mode=timing
mem_ranges=
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
memories=system.physmem
stats: update stale config.ini files, eio and few other stats.
2015-07-04 17:43:47 +02:00
mmap_using_noreserve=false
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
multi_thread=false
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
num_work_ids=16
stats: update references
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
readfile=
symbolfile=
stats: Update to match ARM ISA changes
2016-06-02 15:14:36 +02:00
thermal_components=
thermal_model=Null
Stats: Re update stats.
2011-02-08 04:23:13 +01:00
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
ARM: Update stats for CBNZ fix.
2012-03-09 21:33:07 +01:00
system_port=system.membus.slave[0]
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.clk_domain]
type=SrcClockDomain
clock=1000
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
domain_id=-1
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
init_perf_level=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
voltage_domain=system.voltage_domain
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
[system.cpu]
type=TimingSimpleCPU
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
branchPred=Null
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
checker=Null
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
cpu_id=0
stats: update references
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
do_checkpoint_insts=true
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
do_quiesce=true
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
do_statistics_insts=true
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
dstage2_mmu=system.cpu.dstage2_mmu
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
dtb=system.cpu.dtb
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
function_trace=false
function_trace_start=0
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
interrupts=system.cpu.interrupts
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
isa=system.cpu.isa
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
istage2_mmu=system.cpu.istage2_mmu
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
stats: update references
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
profile=0
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
progress_interval=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
simpoint_start_insts=
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
socket_id=0
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
switched_out=false
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
type=Cache
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=tags
ARM: Update stats for CBNZ fix.
2012-03-09 21:33:07 +01:00
addr_ranges=0:18446744073709551615
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
assoc=2
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
clusivity=mostly_incl
stats: update references
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
stats: update stale config.ini files, eio and few other stats.
2015-07-04 17:43:47 +02:00
demand_mshr_reserve=1
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
hit_latency=2
stats: update stale config.ini files, eio and few other stats.
2015-07-04 17:43:47 +02:00
is_read_only=false
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
max_miss_count=0
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
mshrs=4
stats: update references
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
prefetch_on_access=false
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
prefetcher=Null
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
response_latency=2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
size=262144
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
tags=system.cpu.dcache.tags
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
tgts_per_mshr=20
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
write_buffers=8
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
writeback_clean=false
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
cpu_side=system.cpu.dcache_port
ARM: Update stats for CBNZ fix.
2012-03-09 21:33:07 +01:00
mem_side=system.cpu.toL2Bus.slave[1]
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
stats: update references
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
hit_latency=2
stats: update references
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
size=262144
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
stats: update stale config.ini files, eio and few other stats.
2015-07-04 17:43:47 +02:00
sys=system
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
stats: update references
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
stats: update references
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
sys=system
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
[system.cpu.dtb]
type=ArmTLB
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
children=walker
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
is_stage2=false
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
size=64
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: update references
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
is_stage2=false
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
num_squash_per_cycle=2
stats: update references
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
sys=system
ARM: Update stats for CBNZ fix.
2012-03-09 21:33:07 +01:00
port=system.cpu.toL2Bus.slave[3]
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
[system.cpu.icache]
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
type=Cache
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=tags
ARM: Update stats for CBNZ fix.
2012-03-09 21:33:07 +01:00
addr_ranges=0:18446744073709551615
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
assoc=2
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
clusivity=mostly_incl
stats: update references
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
stats: update stale config.ini files, eio and few other stats.
2015-07-04 17:43:47 +02:00
demand_mshr_reserve=1
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
hit_latency=2
stats: update stale config.ini files, eio and few other stats.
2015-07-04 17:43:47 +02:00
is_read_only=true
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
max_miss_count=0
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
mshrs=4
stats: update references
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
prefetch_on_access=false
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
prefetcher=Null
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
response_latency=2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
size=131072
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
tags=system.cpu.icache.tags
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
tgts_per_mshr=20
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
write_buffers=8
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
writeback_clean=true
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
cpu_side=system.cpu.icache_port
ARM: Update stats for CBNZ fix.
2012-03-09 21:33:07 +01:00
mem_side=system.cpu.toL2Bus.slave[0]
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
stats: update references
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
hit_latency=2
stats: update references
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
size=131072
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
[system.cpu.interrupts]
type=ArmInterrupts
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
[system.cpu.isa]
type=ArmISA
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
decoderFlavour=Generic
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
fpsid=1090793632
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
id_mmfr0=270536963
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
id_mmfr1=0
id_mmfr2=19070976
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
id_mmfr3=34611729
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
id_pfr0=49
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
id_pfr1=4113
midr=1091551472
stats: update stale config.ini files, eio and few other stats.
2015-07-04 17:43:47 +02:00
pmu=Null
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system=system
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
stats: update stale config.ini files, eio and few other stats.
2015-07-04 17:43:47 +02:00
sys=system
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
stats: update references
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
stats: update references
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
sys=system
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
[system.cpu.itb]
type=ArmTLB
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
children=walker
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
is_stage2=false
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
size=64
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: update references
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
is_stage2=false
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
num_squash_per_cycle=2
stats: update references
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
sys=system
ARM: Update stats for CBNZ fix.
2012-03-09 21:33:07 +01:00
port=system.cpu.toL2Bus.slave[2]
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
[system.cpu.l2cache]
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
type=Cache
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=tags
ARM: Update stats for CBNZ fix.
2012-03-09 21:33:07 +01:00
addr_ranges=0:18446744073709551615
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
assoc=8
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
clusivity=mostly_incl
stats: update references
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
stats: update stale config.ini files, eio and few other stats.
2015-07-04 17:43:47 +02:00
demand_mshr_reserve=1
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
hit_latency=20
stats: update stale config.ini files, eio and few other stats.
2015-07-04 17:43:47 +02:00
is_read_only=false
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
max_miss_count=0
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
mshrs=20
stats: update references
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
prefetch_on_access=false
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
prefetcher=Null
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
response_latency=20
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
size=2097152
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
tags=system.cpu.l2cache.tags
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
tgts_per_mshr=12
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
write_buffers=8
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
writeback_clean=false
ARM: Update stats for CBNZ fix.
2012-03-09 21:33:07 +01:00
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
stats: update references
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
hit_latency=20
stats: update references
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
size=2097152
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
[system.cpu.toL2Bus]
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
type=CoherentXBar
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
children=snoop_filter
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: update references
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: update stale config.ini files, eio and few other stats.
2015-07-04 17:43:47 +02:00
forward_latency=0
frontend_latency=1
stats: update references
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
point_of_coherency=false
stats: update references
2016-07-21 18:19:18 +02:00
power_model=Null
stats: update stale config.ini files, eio and few other stats.
2015-07-04 17:43:47 +02:00
response_latency=1
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
snoop_filter=system.cpu.toL2Bus.snoop_filter
stats: update stale config.ini files, eio and few other stats.
2015-07-04 17:43:47 +02:00
snoop_response_latency=1
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
system=system
tests: update reference config.ini files for previous cset Rename 'responder_set' to 'use_default_range'.
2010-08-17 14:06:22 +02:00
use_default_range=false
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
width=32
ARM: Update stats for CBNZ fix.
2012-03-09 21:33:07 +01:00
master=system.cpu.l2cache.cpu_side
stats: update stale config.ini files, eio and few other stats.
2015-07-04 17:43:47 +02:00
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
[system.cpu.tracer]
type=ExeTracer
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing
stats: update stale config.ini files, eio and few other stats.
2015-07-04 17:43:47 +02:00
drivers=
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
egid=100
env=
errout=cerr
euid=100
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: update references
2016-07-21 18:19:18 +02:00
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/eon
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
gid=100
input=cin
stats: update stale config.ini files, eio and few other stats.
2015-07-04 17:43:47 +02:00
kvmInSE=false
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
useArchPT=false
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
domain_id=-1
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
init_perf_level=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
voltage_domain=system.voltage_domain
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
[system.membus]
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
type=CoherentXBar
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: update references
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: update stale config.ini files, eio and few other stats.
2015-07-04 17:43:47 +02:00
forward_latency=4
frontend_latency=3
stats: update references
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
point_of_coherency=true
stats: update references
2016-07-21 18:19:18 +02:00
power_model=Null
stats: update stale config.ini files, eio and few other stats.
2015-07-04 17:43:47 +02:00
response_latency=2
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
snoop_filter=Null
stats: update stale config.ini files, eio and few other stats.
2015-07-04 17:43:47 +02:00
snoop_response_latency=4
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
system=system
tests: update reference config.ini files for previous cset Rename 'responder_set' to 'use_default_range'.
2010-08-17 14:06:22 +02:00
use_default_range=false
stats: update stale config.ini files, eio and few other stats.
2015-07-04 17:43:47 +02:00
width=16
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
master=system.physmem.port
ARM: Update stats for CBNZ fix.
2012-03-09 21:33:07 +01:00
slave=system.system_port system.cpu.l2cache.mem_side
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
[system.physmem]
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
type=SimpleMemory
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
bandwidth=73.000000
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
conf_table_reported=true
stats: update references
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
in_addr_map=true
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
latency=30000
latency_var=0
null=false
stats: update references
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
range=0:134217727
ARM: Update stats for CBNZ fix.
2012-03-09 21:33:07 +01:00
port=system.membus.master[0]
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.voltage_domain]
type=VoltageDomain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
voltage=1.000000
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