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gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt

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Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
---------- Begin Simulation Statistics ----------
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
sim_seconds 1.903338 # Number of seconds simulated
sim_ticks 1903338216000 # Number of ticks simulated
final_tick 1903338216000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
host_inst_rate 150214 # Simulator instruction rate (inst/s)
host_op_rate 150214 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5096064990 # Simulator tick rate (ticks/s)
host_mem_usage 314972 # Number of bytes of host memory used
host_seconds 373.49 # Real time elapsed on the host
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
sim_insts 56103611 # Number of instructions simulated
sim_ops 56103611 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.bytes_read::cpu0.inst 740992 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 24346432 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2650176 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 236544 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 996032 # Number of bytes read from this memory
system.physmem.bytes_read::total 28970176 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 740992 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 236544 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 977536 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7923904 # Number of bytes written to this memory
system.physmem.bytes_written::total 7923904 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst 11578 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 380413 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41409 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 3696 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 15563 # Number of read requests responded to by this memory
system.physmem.num_reads::total 452659 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 123811 # Number of write requests responded to by this memory
system.physmem.num_writes::total 123811 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst 389312 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 12791438 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 1392383 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 124278 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 523308 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 15220719 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 389312 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 124278 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 513590 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4163161 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4163161 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4163161 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 389312 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 12791438 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1392383 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 124278 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 523308 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 19383880 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 452659 # Number of read requests accepted
system.physmem.writeReqs 123811 # Number of write requests accepted
system.physmem.readBursts 452659 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 123811 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 28966400 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 3776 # Total number of bytes read from write queue
system.physmem.bytesWritten 7923264 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 28970176 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7923904 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 59 # Number of DRAM read bursts serviced by the write queue
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.neitherReadNorWriteReqs 3474 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 28542 # Per bank write bursts
system.physmem.perBankRdBursts::1 28115 # Per bank write bursts
system.physmem.perBankRdBursts::2 28449 # Per bank write bursts
system.physmem.perBankRdBursts::3 28319 # Per bank write bursts
system.physmem.perBankRdBursts::4 28001 # Per bank write bursts
system.physmem.perBankRdBursts::5 28388 # Per bank write bursts
system.physmem.perBankRdBursts::6 28437 # Per bank write bursts
system.physmem.perBankRdBursts::7 28681 # Per bank write bursts
system.physmem.perBankRdBursts::8 28670 # Per bank write bursts
system.physmem.perBankRdBursts::9 28576 # Per bank write bursts
system.physmem.perBankRdBursts::10 28034 # Per bank write bursts
system.physmem.perBankRdBursts::11 27899 # Per bank write bursts
system.physmem.perBankRdBursts::12 27884 # Per bank write bursts
system.physmem.perBankRdBursts::13 28245 # Per bank write bursts
system.physmem.perBankRdBursts::14 28268 # Per bank write bursts
system.physmem.perBankRdBursts::15 28092 # Per bank write bursts
system.physmem.perBankWrBursts::0 8222 # Per bank write bursts
system.physmem.perBankWrBursts::1 7571 # Per bank write bursts
system.physmem.perBankWrBursts::2 7821 # Per bank write bursts
system.physmem.perBankWrBursts::3 7782 # Per bank write bursts
system.physmem.perBankWrBursts::4 7428 # Per bank write bursts
system.physmem.perBankWrBursts::5 7859 # Per bank write bursts
system.physmem.perBankWrBursts::6 7924 # Per bank write bursts
system.physmem.perBankWrBursts::7 7992 # Per bank write bursts
system.physmem.perBankWrBursts::8 7912 # Per bank write bursts
system.physmem.perBankWrBursts::9 7920 # Per bank write bursts
system.physmem.perBankWrBursts::10 7418 # Per bank write bursts
system.physmem.perBankWrBursts::11 7297 # Per bank write bursts
system.physmem.perBankWrBursts::12 7319 # Per bank write bursts
system.physmem.perBankWrBursts::13 7829 # Per bank write bursts
system.physmem.perBankWrBursts::14 7922 # Per bank write bursts
system.physmem.perBankWrBursts::15 7585 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.numWrRetry 11 # Number of times write queue was full causing retry
system.physmem.totGap 1903333578000 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.readPktSize::6 452659 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.writePktSize::6 123811 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 323009 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 67548 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 34699 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 6478 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2371 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2334 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1401 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1384 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1370 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1491 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1342 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1292 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1112 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 975 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 964 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 959 # What read queue length does an incoming req see
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.rdQLenPdf::16 957 # What read queue length does an incoming req see
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.rdQLenPdf::17 955 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 964 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 962 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 15 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 9 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 4 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.wrQLenPdf::0 4849 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 4883 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 4897 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 5584 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 6333 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 5671 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 5669 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 5751 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 5810 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 5108 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 5105 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 5103 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 5948 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 6051 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 6046 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 6136 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 6172 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5299 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5396 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5248 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5812 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6208 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 343 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 192 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 30 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 22 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 18 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.wrQLenPdf::31 24 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 47120 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 782.856367 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 226.112166 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 1866.075506 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-67 16751 35.55% 35.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-131 6847 14.53% 50.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-195 4876 10.35% 60.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-259 2833 6.01% 66.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-323 1808 3.84% 70.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-387 1449 3.08% 73.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-451 1103 2.34% 75.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-515 806 1.71% 77.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-579 633 1.34% 78.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-643 628 1.33% 80.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-707 650 1.38% 81.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-771 508 1.08% 82.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-835 311 0.66% 83.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-899 305 0.65% 83.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-963 262 0.56% 84.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1027 366 0.78% 85.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1091 155 0.33% 85.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1155 210 0.45% 85.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1219 130 0.28% 86.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1283 135 0.29% 86.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1347 148 0.31% 86.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1411 388 0.82% 87.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1475 228 0.48% 88.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1539 713 1.51% 89.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1603 124 0.26% 89.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1667 79 0.17% 90.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1731 68 0.14% 90.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1795 140 0.30% 90.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1859 59 0.13% 90.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1923 90 0.19% 90.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1987 49 0.10% 90.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2051 89 0.19% 91.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2115 69 0.15% 91.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2179 88 0.19% 91.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2243 28 0.06% 91.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2307 26 0.06% 91.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2371 54 0.11% 91.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2435 52 0.11% 91.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2499 27 0.06% 91.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2563 28 0.06% 91.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2627 27 0.06% 91.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2691 54 0.11% 92.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2755 53 0.11% 92.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2819 17 0.04% 92.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2883 31 0.07% 92.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2947 83 0.18% 92.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3011 40 0.08% 92.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3075 35 0.07% 92.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3139 42 0.09% 92.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3203 86 0.18% 92.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3267 24 0.05% 92.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3331 15 0.03% 93.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3395 51 0.11% 93.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3459 50 0.11% 93.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3523 24 0.05% 93.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3587 22 0.05% 93.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3651 24 0.05% 93.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3715 52 0.11% 93.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3779 51 0.11% 93.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3843 12 0.03% 93.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3907 29 0.06% 93.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3971 84 0.18% 93.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4035 41 0.09% 93.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4099 31 0.07% 94.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4163 38 0.08% 94.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4227 87 0.18% 94.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4291 24 0.05% 94.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4355 17 0.04% 94.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4419 52 0.11% 94.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4483 51 0.11% 94.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4547 24 0.05% 94.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4611 22 0.05% 94.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4675 23 0.05% 94.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4739 50 0.11% 94.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4803 51 0.11% 94.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4867 12 0.03% 94.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4931 27 0.06% 95.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4995 86 0.18% 95.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5059 41 0.09% 95.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5123 30 0.06% 95.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5187 39 0.08% 95.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5251 84 0.18% 95.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5315 24 0.05% 95.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5379 9 0.02% 95.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5443 53 0.11% 95.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5507 50 0.11% 95.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5571 23 0.05% 95.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5635 22 0.05% 95.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5699 22 0.05% 96.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5763 49 0.10% 96.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5827 50 0.11% 96.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5891 9 0.02% 96.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5955 25 0.05% 96.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6019 85 0.18% 96.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6083 41 0.09% 96.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6147 30 0.06% 96.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6211 42 0.09% 96.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6275 84 0.18% 96.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6339 24 0.05% 96.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6403 10 0.02% 96.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6467 52 0.11% 97.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6531 52 0.11% 97.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6595 24 0.05% 97.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6659 22 0.05% 97.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6723 25 0.05% 97.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6787 49 0.10% 97.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6851 49 0.10% 97.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6915 8 0.02% 97.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6979 27 0.06% 97.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7043 87 0.18% 97.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7107 41 0.09% 97.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7171 317 0.67% 98.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7235 1 0.00% 98.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7299 2 0.00% 98.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7363 1 0.00% 98.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7427 6 0.01% 98.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7491 1 0.00% 98.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7683 14 0.03% 98.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7747 2 0.00% 98.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7939 8 0.02% 98.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8003 1 0.00% 98.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8131 3 0.01% 98.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8195 322 0.68% 99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8640-8643 1 0.00% 99.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8704-8707 2 0.00% 99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9088-9091 2 0.00% 99.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9219 2 0.00% 99.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9344-9347 3 0.01% 99.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9728-9731 2 0.00% 99.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9856-9859 3 0.01% 99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10176-10179 1 0.00% 99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10304-10307 2 0.00% 99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11328-11331 2 0.00% 99.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11392-11395 2 0.00% 99.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11456-11459 2 0.00% 99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11584-11587 2 0.00% 99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11648-11651 1 0.00% 99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11840-11843 1 0.00% 99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11904-11907 2 0.00% 99.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11968-11971 1 0.00% 99.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12032-12035 4 0.01% 99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12480-12483 1 0.00% 99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12544-12547 2 0.00% 99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.47% # Bytes accessed per row activation
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.47% # Bytes accessed per row activation
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.bytesPerActivate::13248-13251 2 0.00% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13312-13315 3 0.01% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13568-13571 2 0.00% 99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13696-13699 3 0.01% 99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14144-14147 2 0.00% 99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14208-14211 2 0.00% 99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14272-14275 2 0.00% 99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14336-14339 3 0.01% 99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.52% # Bytes accessed per row activation
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.52% # Bytes accessed per row activation
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15232-15235 2 0.00% 99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15363 39 0.08% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15552-15555 2 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16000-16003 2 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16387 175 0.37% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 47120 # Bytes accessed per row activation
system.physmem.totQLat 8783315250 # Total ticks spent queuing
system.physmem.totMemAccLat 16310447750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2263000000 # Total ticks spent in databus transfers
system.physmem.totBankLat 5264132500 # Total ticks spent accessing banks
system.physmem.avgQLat 19406.35 # Average queueing delay per DRAM burst
system.physmem.avgBankLat 11630.87 # Average bank access latency per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.avgMemAccLat 36037.22 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 15.22 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 4.16 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 15.22 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 4.16 # Average system write bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.busUtil 0.15 # Data bus utilization in percentage
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.avgWrQLen 9.32 # Average write queue length when enqueuing
system.physmem.readRowHits 430734 # Number of row buffer hits during reads
system.physmem.writeRowHits 98547 # Number of row buffer hits during writes
system.physmem.readRowHitRate 95.17 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 79.59 # Row buffer hit rate for writes
system.physmem.avgGap 3301704.47 # Average gap between requests
system.physmem.pageHitRate 91.82 # Row buffer hit rate, read and write combined
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.prechargeAllPercent 0.41 # Percentage of time for which DRAM has all the banks in precharge state
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.membus.throughput 19439855 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 296479 # Transaction distribution
system.membus.trans_dist::ReadResp 296230 # Transaction distribution
system.membus.trans_dist::WriteReq 12351 # Transaction distribution
system.membus.trans_dist::WriteResp 12351 # Transaction distribution
system.membus.trans_dist::Writeback 123811 # Transaction distribution
system.membus.trans_dist::UpgradeReq 5304 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 1475 # Transaction distribution
system.membus.trans_dist::UpgradeResp 3474 # Transaction distribution
system.membus.trans_dist::ReadExReq 164353 # Transaction distribution
system.membus.trans_dist::ReadExResp 164224 # Transaction distribution
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.membus.trans_dist::BadAddressError 249 # Transaction distribution
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39094 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 915454 # Packet count per connected master and slave (bytes)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 498 # Packet count per connected master and slave (bytes)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.membus.pkt_count_system.l2c.mem_side::total 955046 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124656 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 124656 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1079702 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68202 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31586624 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total 31654826 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5307456 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 5307456 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 36962282 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 36962282 # Total data (bytes)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.membus.snoop_data_through_bus 38336 # Total snoop data (bytes)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.membus.reqLayer0.occupancy 36252500 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.membus.reqLayer1.occupancy 1624596499 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.membus.reqLayer2.occupancy 317500 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.membus.respLayer1.occupancy 3836772510 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.membus.respLayer2.occupancy 376321991 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.l2c.tags.replacements 345713 # number of replacements
system.l2c.tags.tagsinuse 65292.619294 # Cycle average of tags in use
system.l2c.tags.total_refs 2607692 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 410924 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 6.345923 # Average number of references to valid blocks.
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.l2c.tags.warmup_cycle 7069563750 # Cycle when the warmup percentage was hit.
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.l2c.tags.occ_blocks::writebacks 53648.503329 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 4120.078366 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 5598.798644 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 1365.340117 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 559.898838 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.818611 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.062867 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.085431 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.020833 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.008543 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.996286 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.tags.occ_task_id_blocks::1024 65211 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 2154 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 5524 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 6881 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 50473 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.995041 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 27399611 # Number of tag accesses
system.l2c.tags.data_accesses 27399611 # Number of data accesses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.l2c.ReadReq_hits::cpu0.inst 754547 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 572386 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 313557 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 249669 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1890159 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 840492 # number of Writeback hits
system.l2c.Writeback_hits::total 840492 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 130 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 74 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 204 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 37 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 33 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 70 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 144073 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 44330 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 188403 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst 754547 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 716459 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 313557 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 293999 # number of demand (read+write) hits
system.l2c.demand_hits::total 2078562 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 754547 # number of overall hits
system.l2c.overall_hits::cpu0.data 716459 # number of overall hits
system.l2c.overall_hits::cpu1.inst 313557 # number of overall hits
system.l2c.overall_hits::cpu1.data 293999 # number of overall hits
system.l2c.overall_hits::total 2078562 # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst 11586 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 272059 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 3706 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 1775 # number of ReadReq misses
system.l2c.ReadReq_misses::total 289126 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 2565 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 587 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 3152 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 58 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 107 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 165 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 108741 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 14088 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 122829 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst 11586 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 380800 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 3706 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 15863 # number of demand (read+write) misses
system.l2c.demand_misses::total 411955 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst 11586 # number of overall misses
system.l2c.overall_misses::cpu0.data 380800 # number of overall misses
system.l2c.overall_misses::cpu1.inst 3706 # number of overall misses
system.l2c.overall_misses::cpu1.data 15863 # number of overall misses
system.l2c.overall_misses::total 411955 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst 929054999 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 17693461250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 314236981 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 144928247 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 19081681477 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 842965 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 1256946 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 2099911 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 221993 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 116495 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 338488 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 8947158383 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 1452475204 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 10399633587 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst 929054999 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 26640619633 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 314236981 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 1597403451 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 29481315064 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst 929054999 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 26640619633 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 314236981 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 1597403451 # number of overall miss cycles
system.l2c.overall_miss_latency::total 29481315064 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst 766133 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 844445 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 317263 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 251444 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2179285 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 840492 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 840492 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 2695 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 661 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 3356 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 95 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 140 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 235 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 252814 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 58418 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 311232 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst 766133 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 1097259 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 317263 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 309862 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2490517 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 766133 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 1097259 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 317263 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 309862 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2490517 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.015123 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.322175 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.011681 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.007059 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.132670 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.951763 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.888048 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.939213 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.610526 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.764286 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.702128 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.430123 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.241159 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.394654 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.015123 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.347047 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.011681 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.051194 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.165409 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.015123 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.347047 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.011681 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.051194 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.165409 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80187.726480 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 65035.382950 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 84791.414193 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 81649.716620 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 65997.805376 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 328.641326 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2141.304940 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 666.215419 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3827.465517 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1088.738318 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 2051.442424 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 82279.530104 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 103100.170642 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 84667.575141 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 80187.726480 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 69959.610381 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 84791.414193 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 100699.959087 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 71564.406462 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 80187.726480 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 69959.610381 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 84791.414193 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 100699.959087 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 71564.406462 # average overall miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.l2c.writebacks::writebacks 82291 # number of writebacks
system.l2c.writebacks::total 82291 # number of writebacks
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.l2c.ReadReq_mshr_hits::cpu0.inst 7 # number of ReadReq MSHR hits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_mshr_hits::cpu0.data 1 # number of ReadReq MSHR hits
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.l2c.ReadReq_mshr_hits::cpu1.inst 10 # number of ReadReq MSHR hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.l2c.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.demand_mshr_hits::cpu0.data 1 # number of demand (read+write) MSHR hits
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.l2c.demand_mshr_hits::cpu1.inst 10 # number of demand (read+write) MSHR hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.l2c.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.overall_mshr_hits::cpu0.data 1 # number of overall MSHR hits
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.l2c.overall_mshr_hits::cpu1.inst 10 # number of overall MSHR hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.l2c.ReadReq_mshr_misses::cpu0.inst 11579 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 272058 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 3696 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 1775 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 289108 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 2565 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 587 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 3152 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 58 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 107 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 165 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 108741 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 14088 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 122829 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 11579 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 380799 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 3696 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 15863 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 411937 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 11579 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 380799 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 3696 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 15863 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 411937 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 782519751 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14298950750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 266998019 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 147305751 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 15495774271 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 25723531 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5884082 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 31607613 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 641556 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1072106 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 1713662 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7614105115 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1279019296 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 8893124411 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 782519751 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 21913055865 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 266998019 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 1426325047 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 24388898682 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 782519751 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 21913055865 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 266998019 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 1426325047 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 24388898682 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 931434500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 458421000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 1389855500 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1577498000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 884169000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 2461667000 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2508932500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1342590000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 3851522500 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015114 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.322174 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011650 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.007059 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.132662 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.951763 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.888048 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.939213 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.610526 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.764286 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.702128 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.430123 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.241159 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.394654 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015114 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.347046 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011650 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.051194 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.165402 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015114 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.347046 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011650 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.051194 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.165402 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67580.944037 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52558.464555 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72239.723755 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 82989.155493 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 53598.566179 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10028.667057 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10023.989779 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10027.796003 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 11061.310345 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10019.682243 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10385.830303 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70020.554483 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 90787.854628 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 72402.481588 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67580.944037 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57544.940677 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72239.723755 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 89915.214461 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 59205.409279 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67580.944037 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57544.940677 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72239.723755 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 89915.214461 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 59205.409279 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iocache.tags.replacements 41695 # number of replacements
system.iocache.tags.tagsinuse 0.213166 # Cycle average of tags in use
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iocache.tags.warmup_cycle 1712301131000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide 0.213166 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide 0.013323 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.013323 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 375543 # Number of tag accesses
system.iocache.tags.data_accesses 375543 # Number of data accesses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses
system.iocache.ReadReq_misses::total 175 # number of ReadReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses
system.iocache.demand_misses::total 41727 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses
system.iocache.overall_misses::total 41727 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 21368383 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 21368383 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide 13021515788 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 13021515788 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 13042884171 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 13042884171 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 13042884171 # number of overall miss cycles
system.iocache.overall_miss_latency::total 13042884171 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122105.045714 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 122105.045714 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 313378.797362 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 313378.797362 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 312576.609174 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 312576.609174 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 312576.609174 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 312576.609174 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 407057 # number of cycles access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iocache.blocked::no_mshrs 29358 # number of cycles access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 13.865284 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.writebacks::writebacks 41520 # number of writebacks
system.iocache.writebacks::total 41520 # number of writebacks
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12267383 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 12267383 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10859254806 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 10859254806 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 10871522189 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 10871522189 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 10871522189 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 10871522189 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70099.331429 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 70099.331429 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 261341.326675 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 261341.326675 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 260539.271671 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 260539.271671 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 260539.271671 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 260539.271671 # average overall mshr miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.branchPred.lookups 11006012 # Number of BP lookups
system.cpu0.branchPred.condPredicted 9319545 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 291548 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 7161716 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 4729334 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.branchPred.BTBHitPct 66.036324 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 682987 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 26515 # Number of incorrect RAS predictions.
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.dtb.read_hits 7888949 # DTB read hits
system.cpu0.dtb.read_misses 30101 # DTB read misses
system.cpu0.dtb.read_acv 574 # DTB read access violations
system.cpu0.dtb.read_accesses 665608 # DTB read accesses
system.cpu0.dtb.write_hits 5247941 # DTB write hits
system.cpu0.dtb.write_misses 8093 # DTB write misses
system.cpu0.dtb.write_acv 365 # DTB write access violations
system.cpu0.dtb.write_accesses 232480 # DTB write accesses
system.cpu0.dtb.data_hits 13136890 # DTB hits
system.cpu0.dtb.data_misses 38194 # DTB misses
system.cpu0.dtb.data_acv 939 # DTB access violations
system.cpu0.dtb.data_accesses 898088 # DTB accesses
system.cpu0.itb.fetch_hits 973403 # ITB hits
system.cpu0.itb.fetch_misses 31216 # ITB misses
system.cpu0.itb.fetch_acv 1004 # ITB acv
system.cpu0.itb.fetch_accesses 1004619 # ITB accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.write_acv 0 # DTB write access violations
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.data_hits 0 # DTB hits
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.numCycles 104578589 # number of cpu cycles simulated
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.fetch.icacheStallCycles 21960114 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 56555379 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 11006012 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 5412321 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 10656012 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 1518801 # Number of cycles fetch has spent squashing
system.cpu0.fetch.BlockedCycles 32354382 # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles 30030 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 204805 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 243991 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 103 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 6896028 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 198863 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples 66418859 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 0.851496 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.187669 # Number of instructions fetched each cycle (Total)
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.fetch.rateDist::0 55762847 83.96% 83.96% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 696881 1.05% 85.01% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 1363707 2.05% 87.06% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 607827 0.92% 87.97% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 2362378 3.56% 91.53% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 460793 0.69% 92.22% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 493104 0.74% 92.97% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 775074 1.17% 94.13% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 3896248 5.87% 100.00% # Number of instructions fetched each cycle (Total)
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.fetch.rateDist::total 66418859 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.105242 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.540793 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 23145338 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 31820288 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 9657130 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 858074 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 938028 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 439220 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 31710 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 55497748 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 98418 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 938028 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 24047696 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 12280609 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 16434779 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 9089203 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 3628542 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 52477613 # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents 6876 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 427894 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents 1374075 # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RenamedOperands 35152162 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 63950241 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 63830636 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 110747 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 30925813 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 4226341 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 1321793 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 195129 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 9844333 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 8256385 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 5476723 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 1002198 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 667476 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 46574896 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 1622063 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 45553168 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 69417 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 5159281 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 2712846 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 1098313 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 66418859 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.685847 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.329893 # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.iq.issued_per_cycle::0 46042875 69.32% 69.32% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 9328009 14.04% 83.37% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 4252197 6.40% 89.77% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 2720710 4.10% 93.86% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 2085310 3.14% 97.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 1089347 1.64% 98.64% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 576580 0.87% 99.51% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 279468 0.42% 99.93% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 44363 0.07% 100.00% # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.iq.issued_per_cycle::total 66418859 # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.iq.fu_full::IntAlu 65077 10.66% 10.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 0 0.00% 10.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 284948 46.66% 57.32% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 260601 42.68% 100.00% # attempts to use FU when none available
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 31229788 68.56% 68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 47289 0.10% 68.67% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.67% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 14649 0.03% 68.70% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.70% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.70% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.70% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.71% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.71% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.71% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.71% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.71% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.71% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.71% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.71% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.71% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.71% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.71% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.71% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.71% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.71% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.71% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.71% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.71% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.71% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.71% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.71% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.71% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.71% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 8205422 18.01% 86.72% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 5307142 11.65% 98.37% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 743210 1.63% 100.00% # Type of FU issued
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.iq.FU_type_0::total 45553168 # Type of FU issued
system.cpu0.iq.rate 0.435588 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 610626 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.013405 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 157729759 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 53136035 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 44625486 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 475478 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 231159 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 224228 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 45911492 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 248517 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 497947 # Number of loads that had data forwarded from stores
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.iew.lsq.thread0.squashedLoads 1006840 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 3517 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 11189 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 378910 # Number of stores squashed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.iew.lsq.thread0.rescheduledLoads 13584 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 146356 # Number of times an access to memory failed due to the cache being blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.iew.iewSquashCycles 938028 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 8572601 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 702117 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 50999649 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 565079 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 8256385 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 5476723 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 1432117 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 572819 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 5269 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 11189 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 141170 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 315582 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 456752 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 45215846 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 7939970 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 337321 # Number of squashed instructions skipped in execute
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.iew.exec_swp 0 # number of swp insts executed
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.iew.exec_nop 2802690 # number of nop insts executed
system.cpu0.iew.exec_refs 13207799 # number of memory reference insts executed
system.cpu0.iew.exec_branches 7146234 # Number of branches executed
system.cpu0.iew.exec_stores 5267829 # Number of stores executed
system.cpu0.iew.exec_rate 0.432362 # Inst execution rate
system.cpu0.iew.wb_sent 44934571 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 44849714 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 22315831 # num instructions producing a value
system.cpu0.iew.wb_consumers 29845824 # num instructions consuming a value
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.iew.wb_rate 0.428861 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.747704 # average fanout of values written-back
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.commit.commitSquashedInsts 5562563 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 523750 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 426483 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 65480831 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.692465 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.608721 # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.commit.committed_per_cycle::0 48404249 73.92% 73.92% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 7174588 10.96% 84.88% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 3839849 5.86% 90.74% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 2141053 3.27% 94.01% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 1161993 1.77% 95.79% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 481151 0.73% 96.52% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 411214 0.63% 97.15% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 389126 0.59% 97.74% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 1477608 2.26% 100.00% # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.commit.committed_per_cycle::total 65480831 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 45343202 # Number of instructions committed
system.cpu0.commit.committedOps 45343202 # Number of ops (including micro ops) committed
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.commit.refs 12347358 # Number of memory references committed
system.cpu0.commit.loads 7249545 # Number of loads committed
system.cpu0.commit.membars 175312 # Number of memory barriers committed
system.cpu0.commit.branches 6808554 # Number of branches committed
system.cpu0.commit.fp_insts 222342 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 42040123 # Number of committed integer instructions.
system.cpu0.commit.function_calls 564734 # Number of function calls committed.
system.cpu0.commit.bw_lim_events 1477608 # number cycles where commit BW limit reached
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.rob.rob_reads 114710793 # The number of ROB reads
system.cpu0.rob.rob_writes 102749676 # The number of ROB writes
system.cpu0.timesIdled 949561 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 38159730 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 3702093008 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 42781436 # Number of Instructions Simulated
system.cpu0.committedOps 42781436 # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total 42781436 # Number of Instructions Simulated
system.cpu0.cpi 2.444485 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 2.444485 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.409084 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.409084 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 59516377 # number of integer regfile reads
system.cpu0.int_regfile_writes 32453910 # number of integer regfile writes
system.cpu0.fp_regfile_reads 110308 # number of floating regfile reads
system.cpu0.fp_regfile_writes 111090 # number of floating regfile writes
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.misc_regfile_reads 1625466 # number of misc regfile reads
system.cpu0.misc_regfile_writes 747841 # number of misc regfile writes
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.toL2Bus.throughput 112873708 # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq 2210500 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2210236 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 12351 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 12351 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 840492 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 5351 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 1545 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 6896 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 353777 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 312228 # Transaction distribution
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.toL2Bus.trans_dist::BadAddressError 249 # Transaction distribution
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1532372 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2827999 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 634560 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 901176 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 5896107 # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 49032512 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 108336621 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20304832 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 35573309 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total 213247274 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 213236842 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 1600000 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 5059383343 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.toL2Bus.snoopLayer0.occupancy 733500 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.toL2Bus.respLayer0.occupancy 3452114362 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.toL2Bus.respLayer1.occupancy 5048329138 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.toL2Bus.respLayer2.occupancy 1429282335 # Layer occupancy (ticks)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.toL2Bus.respLayer3.occupancy 1486623569 # Layer occupancy (ticks)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iobus.throughput 1434231 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 7371 # Transaction distribution
system.iobus.trans_dist::ReadResp 7371 # Transaction distribution
system.iobus.trans_dist::WriteReq 53903 # Transaction distribution
system.iobus.trans_dist::WriteResp 53903 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10490 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::total 39094 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 122548 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 41960 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iobus.tot_pkt_size_system.bridge.master::total 68202 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 2729826 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 2729826 # Total data (bytes)
system.iobus.reqLayer0.occupancy 9845000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iobus.reqLayer29.occupancy 377802180 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iobus.respLayer0.occupancy 26743000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iobus.respLayer1.occupancy 42660009 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.icache.tags.replacements 765570 # number of replacements
system.cpu0.icache.tags.tagsinuse 509.693534 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 6090993 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 766079 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 7.950868 # Average number of references to valid blocks.
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu0.icache.tags.warmup_cycle 26716185250 # Cycle when the warmup percentage was hit.
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.693534 # Average occupied blocks per requestor
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995495 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.995495 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 314 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 7662265 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 7662265 # Number of data accesses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.icache.ReadReq_hits::cpu0.inst 6090993 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 6090993 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 6090993 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 6090993 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 6090993 # number of overall hits
system.cpu0.icache.overall_hits::total 6090993 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 805033 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 805033 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 805033 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 805033 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 805033 # number of overall misses
system.cpu0.icache.overall_misses::total 805033 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11432598915 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 11432598915 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 11432598915 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 11432598915 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 11432598915 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 11432598915 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 6896026 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 6896026 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 6896026 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 6896026 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 6896026 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 6896026 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116739 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.116739 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116739 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.116739 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116739 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.116739 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14201.404060 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14201.404060 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14201.404060 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14201.404060 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14201.404060 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14201.404060 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 4227 # number of cycles access was blocked
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.icache.blocked::no_mshrs 138 # number of cycles access was blocked
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs 30.630435 # average number of cycles each access was blocked
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 38794 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 38794 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 38794 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 38794 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 38794 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 38794 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 766239 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 766239 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 766239 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 766239 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 766239 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 766239 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9400829636 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 9400829636 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9400829636 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 9400829636 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9400829636 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 9400829636 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.111113 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.111113 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.111113 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.111113 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.111113 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.111113 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12268.795553 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12268.795553 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12268.795553 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12268.795553 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12268.795553 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12268.795553 # average overall mshr miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.dcache.tags.replacements 1099493 # number of replacements
system.cpu0.dcache.tags.tagsinuse 471.490981 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 9327298 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 1100005 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 8.479323 # Average number of references to valid blocks.
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu0.dcache.tags.warmup_cycle 25754000 # Cycle when the warmup percentage was hit.
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 471.490981 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.920881 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.920881 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 220 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 50559091 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 50559091 # Number of data accesses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.dcache.ReadReq_hits::cpu0.data 5751167 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 5751167 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3244504 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 3244504 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151160 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 151160 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 174499 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 174499 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 8995671 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 8995671 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 8995671 # number of overall hits
system.cpu0.dcache.overall_hits::total 8995671 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 1359261 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 1359261 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1665675 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1665675 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 17016 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 17016 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 764 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 764 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 3024936 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 3024936 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 3024936 # number of overall misses
system.cpu0.dcache.overall_misses::total 3024936 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 36687958870 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 36687958870 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 74828467074 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 74828467074 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 254575245 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 254575245 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4747557 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 4747557 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 111516425944 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 111516425944 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 111516425944 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 111516425944 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7110428 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 7110428 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4910179 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 4910179 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 168176 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 168176 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 175263 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 175263 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 12020607 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 12020607 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 12020607 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 12020607 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.191164 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.191164 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.339229 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.339229 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.101180 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.101180 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004359 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004359 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.251646 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.251646 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.251646 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.251646 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26991.106837 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 26991.106837 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44923.809911 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 44923.809911 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14960.933533 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14960.933533 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6214.079843 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6214.079843 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36865.714165 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 36865.714165 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36865.714165 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 36865.714165 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 2890749 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 819 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 46898 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 61.639068 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 117 # average number of cycles each access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.dcache.writebacks::writebacks 594718 # number of writebacks
system.cpu0.dcache.writebacks::total 594718 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 521771 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 521771 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1409219 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 1409219 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4206 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4206 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1930990 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 1930990 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1930990 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 1930990 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 837490 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 837490 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 256456 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 256456 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 12810 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12810 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 764 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 764 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 1093946 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 1093946 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 1093946 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 1093946 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 24898598196 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 24898598196 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10973118276 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10973118276 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 152117754 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 152117754 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3219443 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3219443 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35871716472 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 35871716472 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35871716472 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 35871716472 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 993486001 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 993486001 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1673832998 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1673832998 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2667318999 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2667318999 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.117783 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.117783 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.052229 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.052229 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.076170 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.076170 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004359 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004359 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091006 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.091006 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091006 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.091006 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29730.024473 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29730.024473 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42787.527981 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42787.527981 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11874.922248 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11874.922248 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4213.930628 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4213.930628 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32791.121748 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32791.121748 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32791.121748 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32791.121748 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.branchPred.lookups 3875512 # Number of BP lookups
system.cpu1.branchPred.condPredicted 3181518 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 119538 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 2413999 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 1363069 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.branchPred.BTBHitPct 56.465185 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 281270 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 11131 # Number of incorrect RAS predictions.
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.dtb.read_hits 2756439 # DTB read hits
system.cpu1.dtb.read_misses 11971 # DTB read misses
system.cpu1.dtb.read_acv 6 # DTB read access violations
system.cpu1.dtb.read_accesses 281635 # DTB read accesses
system.cpu1.dtb.write_hits 1697476 # DTB write hits
system.cpu1.dtb.write_misses 2261 # DTB write misses
system.cpu1.dtb.write_acv 35 # DTB write access violations
system.cpu1.dtb.write_accesses 106637 # DTB write accesses
system.cpu1.dtb.data_hits 4453915 # DTB hits
system.cpu1.dtb.data_misses 14232 # DTB misses
system.cpu1.dtb.data_acv 41 # DTB access violations
system.cpu1.dtb.data_accesses 388272 # DTB accesses
system.cpu1.itb.fetch_hits 435796 # ITB hits
system.cpu1.itb.fetch_misses 5916 # ITB misses
system.cpu1.itb.fetch_acv 132 # ITB acv
system.cpu1.itb.fetch_accesses 441712 # ITB accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.write_acv 0 # DTB write access violations
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.data_hits 0 # DTB hits
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.numCycles 25703316 # number of cpu cycles simulated
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.fetch.icacheStallCycles 8513027 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 18550498 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 3875512 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 1644339 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 3370867 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 594419 # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles 10509044 # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles 24053 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles 56236 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 158916 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 118 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 2181303 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 77306 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples 23021613 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 0.805786 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.167146 # Number of instructions fetched each cycle (Total)
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.fetch.rateDist::0 19650746 85.36% 85.36% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 192109 0.83% 86.19% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 424155 1.84% 88.03% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 258878 1.12% 89.16% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 512227 2.22% 91.38% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 176251 0.77% 92.15% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 202668 0.88% 93.03% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 249358 1.08% 94.11% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 1355221 5.89% 100.00% # Number of instructions fetched each cycle (Total)
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.fetch.rateDist::total 23021613 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.150779 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.721716 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 8599650 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 10723354 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 3129491 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 191921 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 377196 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 176309 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 12258 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 18185515 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 36387 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 377196 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 8917984 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 3106321 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 6595327 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 2921217 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 1103566 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 17011608 # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents 230 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 267059 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents 236234 # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands 11254383 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 20310939 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 20246817 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 58360 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 9542826 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 1711557 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 544600 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 54677 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 3272980 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 2918733 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 1792509 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 312208 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 170960 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 14943030 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 650638 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 14484391 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 37394 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 2166782 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 1088105 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 467114 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 23021613 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.629165 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.310842 # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.iq.issued_per_cycle::0 16750827 72.76% 72.76% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 2784830 12.10% 84.86% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 1224236 5.32% 90.18% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 874900 3.80% 93.98% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 759442 3.30% 97.27% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 313710 1.36% 98.64% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 192948 0.84% 99.48% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 103377 0.45% 99.92% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 17343 0.08% 100.00% # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.iq.issued_per_cycle::total 23021613 # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.iq.fu_full::IntAlu 19111 7.55% 7.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 0 0.00% 7.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 130840 51.68% 59.23% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 103199 40.77% 100.00% # attempts to use FU when none available
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.iq.FU_type_0::No_OpClass 3518 0.02% 0.02% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 9521262 65.73% 65.76% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 23052 0.16% 65.92% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.92% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 11116 0.08% 65.99% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.99% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.99% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.99% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 1759 0.01% 66.01% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.01% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.01% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.01% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.01% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.01% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.01% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.01% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.01% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.01% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.01% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.01% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.01% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.01% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.01% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.01% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.01% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.01% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.01% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 2876494 19.86% 85.87% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 1724250 11.90% 97.77% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 322940 2.23% 100.00% # Type of FU issued
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.iq.FU_type_0::total 14484391 # Type of FU issued
system.cpu1.iq.rate 0.563522 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 253150 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.017477 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 52052620 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 17652734 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 14115090 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 228319 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 110924 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 107745 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 14614655 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 119368 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 134347 # Number of loads that had data forwarded from stores
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.iew.lsq.thread0.squashedLoads 418294 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 981 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 3304 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 169372 # Number of stores squashed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.iew.lsq.thread0.rescheduledLoads 5236 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 20861 # Number of times an access to memory failed due to the cache being blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.iew.iewSquashCycles 377196 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 2407064 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 140680 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 16469424 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 189598 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 2918733 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 1792509 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 583051 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 52184 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 2431 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 3304 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 57543 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 133828 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 191371 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 14348807 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 2776029 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 135584 # Number of squashed instructions skipped in execute
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.iew.exec_swp 0 # number of swp insts executed
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.iew.exec_nop 875756 # number of nop insts executed
system.cpu1.iew.exec_refs 4481633 # number of memory reference insts executed
system.cpu1.iew.exec_branches 2254475 # Number of branches executed
system.cpu1.iew.exec_stores 1705604 # Number of stores executed
system.cpu1.iew.exec_rate 0.558247 # Inst execution rate
system.cpu1.iew.wb_sent 14259530 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 14222835 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 6903248 # num instructions producing a value
system.cpu1.iew.wb_consumers 9726426 # num instructions consuming a value
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.iew.wb_rate 0.553346 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.709741 # average fanout of values written-back
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.commit.commitSquashedInsts 2312839 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 183524 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 178531 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 22644417 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.622505 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.551942 # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.commit.committed_per_cycle::0 17386197 76.78% 76.78% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 2263939 10.00% 86.78% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 1130304 4.99% 91.77% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 578693 2.56% 94.32% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 365284 1.61% 95.94% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 174241 0.77% 96.71% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 166825 0.74% 97.44% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 129123 0.57% 98.01% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 449811 1.99% 100.00% # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.commit.committed_per_cycle::total 22644417 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 14096266 # Number of instructions committed
system.cpu1.commit.committedOps 14096266 # Number of ops (including micro ops) committed
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.commit.refs 4123576 # Number of memory references committed
system.cpu1.commit.loads 2500439 # Number of loads committed
system.cpu1.commit.membars 61456 # Number of memory barriers committed
system.cpu1.commit.branches 2105755 # Number of branches committed
system.cpu1.commit.fp_insts 106451 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 13014804 # Number of committed integer instructions.
system.cpu1.commit.function_calls 225813 # Number of function calls committed.
system.cpu1.commit.bw_lim_events 449811 # number cycles where commit BW limit reached
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.rob.rob_reads 38521772 # The number of ROB reads
system.cpu1.rob.rob_writes 33194220 # The number of ROB writes
system.cpu1.timesIdled 266846 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 2681703 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 3780938744 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 13322175 # Number of Instructions Simulated
system.cpu1.committedOps 13322175 # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total 13322175 # Number of Instructions Simulated
system.cpu1.cpi 1.929363 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 1.929363 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.518306 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.518306 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 18552962 # number of integer regfile reads
system.cpu1.int_regfile_writes 10191479 # number of integer regfile writes
system.cpu1.fp_regfile_reads 58039 # number of floating regfile reads
system.cpu1.fp_regfile_writes 58174 # number of floating regfile writes
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu1.misc_regfile_reads 1024653 # number of misc regfile reads
system.cpu1.misc_regfile_writes 265032 # number of misc regfile writes
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.icache.tags.replacements 316719 # number of replacements
system.cpu1.icache.tags.tagsinuse 504.225697 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 1849767 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 317231 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 5.830978 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 49140510500 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 504.225697 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.984816 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.984816 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 420 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 2498600 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 2498600 # Number of data accesses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.icache.ReadReq_hits::cpu1.inst 1849767 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 1849767 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 1849767 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 1849767 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 1849767 # number of overall hits
system.cpu1.icache.overall_hits::total 1849767 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 331536 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 331536 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 331536 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 331536 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 331536 # number of overall misses
system.cpu1.icache.overall_misses::total 331536 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4647513106 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 4647513106 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 4647513106 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 4647513106 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 4647513106 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 4647513106 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 2181303 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 2181303 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 2181303 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 2181303 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 2181303 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 2181303 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.151990 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.151990 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.151990 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.151990 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.151990 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.151990 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14018.125048 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 14018.125048 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14018.125048 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 14018.125048 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14018.125048 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 14018.125048 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 1365 # number of cycles access was blocked
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.icache.blocked::no_mshrs 71 # number of cycles access was blocked
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.icache.avg_blocked_cycles::no_mshrs 19.225352 # average number of cycles each access was blocked
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 14239 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 14239 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 14239 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 14239 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 14239 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 14239 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 317297 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 317297 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 317297 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 317297 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 317297 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 317297 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3842042413 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 3842042413 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3842042413 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 3842042413 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3842042413 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 3842042413 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.145462 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.145462 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.145462 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.145462 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.145462 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.145462 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12108.662903 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12108.662903 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12108.662903 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 12108.662903 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12108.662903 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 12108.662903 # average overall mshr miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.dcache.tags.replacements 323504 # number of replacements
system.cpu1.dcache.tags.tagsinuse 495.920224 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 3389718 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 323845 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 10.467100 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 42037852500 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 495.920224 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.968594 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.968594 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu1.dcache.tags.occ_task_id_blocks::1024 341 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.666016 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 17217310 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 17217310 # Number of data accesses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.dcache.ReadReq_hits::cpu1.data 2089496 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 2089496 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 1222054 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 1222054 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 41428 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 41428 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 44398 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 44398 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 3311550 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 3311550 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 3311550 # number of overall hits
system.cpu1.dcache.overall_hits::total 3311550 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 467553 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 467553 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 348721 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 348721 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 7730 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 7730 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 782 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 782 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 816274 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 816274 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 816274 # number of overall misses
system.cpu1.dcache.overall_misses::total 816274 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 7286969700 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 7286969700 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13547153677 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 13547153677 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 112298247 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 112298247 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5736606 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 5736606 # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 20834123377 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 20834123377 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 20834123377 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 20834123377 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 2557049 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 2557049 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 1570775 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 1570775 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 49158 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 49158 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 45180 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 45180 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 4127824 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 4127824 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 4127824 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 4127824 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.182849 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.182849 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.222006 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.222006 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.157248 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.157248 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.017309 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.017309 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.197749 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.197749 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.197749 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.197749 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15585.334069 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15585.334069 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 38848.115476 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 38848.115476 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14527.586934 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14527.586934 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7335.813299 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7335.813299 # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25523.443570 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 25523.443570 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 25523.443570 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 25523.443570 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 423453 # number of cycles access was blocked
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.dcache.blocked::no_mshrs 7447 # number of cycles access was blocked
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 56.862226 # average number of cycles each access was blocked
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.dcache.writebacks::writebacks 245774 # number of writebacks
system.cpu1.dcache.writebacks::total 245774 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 203756 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 203756 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 288423 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 288423 # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1420 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1420 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 492179 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 492179 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 492179 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 492179 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 263797 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 263797 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 60298 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 60298 # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 6310 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 6310 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 781 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 781 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 324095 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 324095 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 324095 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 324095 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3377520942 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3377520942 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2032860866 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2032860866 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70443003 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70443003 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4174394 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4174394 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5410381808 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 5410381808 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5410381808 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 5410381808 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 489946000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 489946000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 936242002 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 936242002 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1426188002 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1426188002 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.103165 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.103165 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038387 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038387 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.128362 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.128362 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.017286 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.017286 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.078515 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.078515 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.078515 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.078515 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12803.485036 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12803.485036 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33713.570367 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33713.570367 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11163.708875 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11163.708875 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5344.934699 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5344.934699 # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16693.814493 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16693.814493 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16693.814493 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16693.814493 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.kern.inst.quiesce 4836 # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei 166329 # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0 57049 39.81% 39.81% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21 131 0.09% 39.90% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22 1924 1.34% 41.24% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30 16 0.01% 41.25% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31 84196 58.75% 100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total 143316 # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0 56102 49.10% 49.10% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21 131 0.11% 49.22% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22 1924 1.68% 50.90% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30 16 0.01% 50.91% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 56086 49.09% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 114259 # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0 1865433154000 98.01% 98.01% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21 62620000 0.00% 98.01% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22 558222500 0.03% 98.04% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30 8649500 0.00% 98.04% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31 37274722500 1.96% 100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total 1903337368500 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0 0.983400 # fraction of swpipl calls that actually changed the ipl
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.kern.ipl_used::31 0.666136 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total 0.797252 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2 8 3.56% 3.56% # number of syscalls executed
system.cpu0.kern.syscall::3 19 8.44% 12.00% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.78% 13.78% # number of syscalls executed
system.cpu0.kern.syscall::6 33 14.67% 28.44% # number of syscalls executed
system.cpu0.kern.syscall::12 1 0.44% 28.89% # number of syscalls executed
system.cpu0.kern.syscall::17 9 4.00% 32.89% # number of syscalls executed
system.cpu0.kern.syscall::19 10 4.44% 37.33% # number of syscalls executed
system.cpu0.kern.syscall::20 6 2.67% 40.00% # number of syscalls executed
system.cpu0.kern.syscall::23 1 0.44% 40.44% # number of syscalls executed
system.cpu0.kern.syscall::24 3 1.33% 41.78% # number of syscalls executed
system.cpu0.kern.syscall::33 7 3.11% 44.89% # number of syscalls executed
system.cpu0.kern.syscall::41 2 0.89% 45.78% # number of syscalls executed
system.cpu0.kern.syscall::45 36 16.00% 61.78% # number of syscalls executed
system.cpu0.kern.syscall::47 3 1.33% 63.11% # number of syscalls executed
system.cpu0.kern.syscall::48 10 4.44% 67.56% # number of syscalls executed
system.cpu0.kern.syscall::54 10 4.44% 72.00% # number of syscalls executed
system.cpu0.kern.syscall::58 1 0.44% 72.44% # number of syscalls executed
system.cpu0.kern.syscall::59 6 2.67% 75.11% # number of syscalls executed
system.cpu0.kern.syscall::71 25 11.11% 86.22% # number of syscalls executed
system.cpu0.kern.syscall::73 3 1.33% 87.56% # number of syscalls executed
system.cpu0.kern.syscall::74 6 2.67% 90.22% # number of syscalls executed
system.cpu0.kern.syscall::87 1 0.44% 90.67% # number of syscalls executed
system.cpu0.kern.syscall::90 3 1.33% 92.00% # number of syscalls executed
system.cpu0.kern.syscall::92 9 4.00% 96.00% # number of syscalls executed
system.cpu0.kern.syscall::97 2 0.89% 96.89% # number of syscalls executed
system.cpu0.kern.syscall::98 2 0.89% 97.78% # number of syscalls executed
system.cpu0.kern.syscall::132 1 0.44% 98.22% # number of syscalls executed
system.cpu0.kern.syscall::144 2 0.89% 99.11% # number of syscalls executed
system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 225 # number of syscalls executed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.kern.callpal::wripir 104 0.07% 0.07% # number of callpals executed
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed
system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.kern.callpal::swpctx 3010 1.99% 2.06% # number of callpals executed
system.cpu0.kern.callpal::tbi 50 0.03% 2.09% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.00% 2.10% # number of callpals executed
system.cpu0.kern.callpal::swpipl 136886 90.50% 92.60% # number of callpals executed
system.cpu0.kern.callpal::rdps 6293 4.16% 96.76% # number of callpals executed
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.77% # number of callpals executed
system.cpu0.kern.callpal::wrusp 3 0.00% 96.77% # number of callpals executed
system.cpu0.kern.callpal::rdusp 9 0.01% 96.77% # number of callpals executed
system.cpu0.kern.callpal::whami 2 0.00% 96.77% # number of callpals executed
system.cpu0.kern.callpal::rti 4358 2.88% 99.66% # number of callpals executed
system.cpu0.kern.callpal::callsys 382 0.25% 99.91% # number of callpals executed
system.cpu0.kern.callpal::imb 138 0.09% 100.00% # number of callpals executed
system.cpu0.kern.callpal::total 151247 # number of callpals executed
system.cpu0.kern.mode_switch::kernel 6436 # number of protection mode switches
system.cpu0.kern.mode_switch::user 1343 # number of protection mode switches
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.kern.mode_good::kernel 1342
system.cpu0.kern.mode_good::user 1343
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.kern.mode_good::idle 0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.kern.mode_switch_good::kernel 0.208515 # fraction of useful protection mode switches
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.kern.mode_switch_good::total 0.345160 # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel 1901289587500 99.89% 99.89% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user 2047773000 0.11% 100.00% # number of ticks spent at the given mode
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.kern.swap_context 3011 # number of times the context was actually changed
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.kern.inst.quiesce 3850 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 71149 # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0 24567 38.92% 38.92% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22 1923 3.05% 41.97% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30 104 0.16% 42.13% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31 36529 57.87% 100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total 63123 # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0 24137 48.08% 48.08% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22 1923 3.83% 51.92% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30 104 0.21% 52.12% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31 24033 47.88% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total 50197 # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0 1869107624500 98.20% 98.20% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22 533184500 0.03% 98.23% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30 48972500 0.00% 98.23% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31 33633158500 1.77% 100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total 1903322940000 # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0 0.982497 # fraction of swpipl calls that actually changed the ipl
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.kern.ipl_used::31 0.657916 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total 0.795225 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::3 11 10.89% 10.89% # number of syscalls executed
system.cpu1.kern.syscall::6 9 8.91% 19.80% # number of syscalls executed
system.cpu1.kern.syscall::15 1 0.99% 20.79% # number of syscalls executed
system.cpu1.kern.syscall::17 6 5.94% 26.73% # number of syscalls executed
system.cpu1.kern.syscall::23 3 2.97% 29.70% # number of syscalls executed
system.cpu1.kern.syscall::24 3 2.97% 32.67% # number of syscalls executed
system.cpu1.kern.syscall::33 4 3.96% 36.63% # number of syscalls executed
system.cpu1.kern.syscall::45 18 17.82% 54.46% # number of syscalls executed
system.cpu1.kern.syscall::47 3 2.97% 57.43% # number of syscalls executed
system.cpu1.kern.syscall::59 1 0.99% 58.42% # number of syscalls executed
system.cpu1.kern.syscall::71 29 28.71% 87.13% # number of syscalls executed
system.cpu1.kern.syscall::74 10 9.90% 97.03% # number of syscalls executed
system.cpu1.kern.syscall::132 3 2.97% 100.00% # number of syscalls executed
system.cpu1.kern.syscall::total 101 # number of syscalls executed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu1.kern.callpal::wripir 16 0.02% 0.03% # number of callpals executed
system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed
system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.kern.callpal::swpctx 1228 1.89% 1.92% # number of callpals executed
system.cpu1.kern.callpal::tbi 3 0.00% 1.92% # number of callpals executed
system.cpu1.kern.callpal::wrent 7 0.01% 1.93% # number of callpals executed
system.cpu1.kern.callpal::swpipl 58251 89.62% 91.55% # number of callpals executed
system.cpu1.kern.callpal::rdps 2464 3.79% 95.34% # number of callpals executed
system.cpu1.kern.callpal::wrkgp 1 0.00% 95.34% # number of callpals executed
system.cpu1.kern.callpal::wrusp 4 0.01% 95.35% # number of callpals executed
system.cpu1.kern.callpal::whami 3 0.00% 95.35% # number of callpals executed
system.cpu1.kern.callpal::rti 2844 4.38% 99.73% # number of callpals executed
system.cpu1.kern.callpal::callsys 133 0.20% 99.93% # number of callpals executed
system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.kern.callpal::total 65000 # number of callpals executed
system.cpu1.kern.mode_switch::kernel 1608 # number of protection mode switches
system.cpu1.kern.mode_switch::user 397 # number of protection mode switches
system.cpu1.kern.mode_switch::idle 2054 # number of protection mode switches
system.cpu1.kern.mode_good::kernel 463
system.cpu1.kern.mode_good::user 397
system.cpu1.kern.mode_good::idle 66
system.cpu1.kern.mode_switch_good::kernel 0.287935 # fraction of useful protection mode switches
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.kern.mode_switch_good::idle 0.032132 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total 0.228135 # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel 38501499500 2.02% 2.02% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user 724848000 0.04% 2.06% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 1863406690000 97.94% 100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context 1229 # number of times the context was actually changed
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink