2012-08-28 20:30:25 +02:00
---------- Begin Simulation Statistics ----------
2015-12-05 01:11:25 +01:00
sim_seconds 2.832913 # Number of seconds simulated
sim_ticks 2832912592000 # Number of ticks simulated
final_tick 2832912592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2012-08-28 20:30:25 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
2015-12-05 01:11:25 +01:00
host_inst_rate 73621 # Simulator instruction rate (inst/s)
host_op_rate 89295 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1844379035 # Simulator tick rate (ticks/s)
host_mem_usage 584220 # Number of bytes of host memory used
host_seconds 1535.97 # Real time elapsed on the host
sim_insts 113079343 # Number of instructions simulated
sim_ops 137154534 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2015-11-06 09:26:50 +01:00
system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 512 # Number of bytes read from this memory
2015-12-05 01:11:25 +01:00
system.physmem.bytes_read::cpu.inst 1316096 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9383208 # Number of bytes read from this memory
2014-11-12 15:05:25 +01:00
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
2015-12-05 01:11:25 +01:00
system.physmem.bytes_read::total 10702120 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1316096 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1316096 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7997312 # Number of bytes written to this memory
2014-10-30 05:18:29 +01:00
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
2015-12-05 01:11:25 +01:00
system.physmem.bytes_written::total 8014836 # Number of bytes written to this memory
2015-11-06 09:26:50 +01:00
system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 8 # Number of read requests responded to by this memory
2015-12-05 01:11:25 +01:00
system.physmem.num_reads::cpu.inst 22811 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 147133 # Number of read requests responded to by this memory
2014-11-12 15:05:25 +01:00
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
2015-12-05 01:11:25 +01:00
system.physmem.num_reads::total 169988 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 124958 # Number of write requests responded to by this memory
2014-10-30 05:18:29 +01:00
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
2015-12-05 01:11:25 +01:00
system.physmem.num_writes::total 129339 # Number of write requests responded to by this memory
2015-11-06 09:26:50 +01:00
system.physmem.bw_read::cpu.dtb.walker 474 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 181 # Total read bandwidth from this memory (bytes/s)
2015-12-05 01:11:25 +01:00
system.physmem.bw_read::cpu.inst 464573 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3312212 # Total read bandwidth from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s)
2015-12-05 01:11:25 +01:00
system.physmem.bw_read::total 3777780 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 464573 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 464573 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2823000 # Write bandwidth from this memory (bytes/s)
2015-11-06 09:26:50 +01:00
system.physmem.bw_write::cpu.data 6186 # Write bandwidth from this memory (bytes/s)
2015-12-05 01:11:25 +01:00
system.physmem.bw_write::total 2829186 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2823000 # Total bandwidth to/from this memory (bytes/s)
2015-11-06 09:26:50 +01:00
system.physmem.bw_total::cpu.dtb.walker 474 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 181 # Total bandwidth to/from this memory (bytes/s)
2015-12-05 01:11:25 +01:00
system.physmem.bw_total::cpu.inst 464573 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3318398 # Total bandwidth to/from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s)
2015-12-05 01:11:25 +01:00
system.physmem.bw_total::total 6606966 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 169989 # Number of read requests accepted
system.physmem.writeReqs 129339 # Number of write requests accepted
system.physmem.readBursts 169989 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 129339 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 10867584 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 11712 # Total number of bytes read from write queue
system.physmem.bytesWritten 8027584 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 10702184 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 8014836 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 183 # Number of DRAM read bursts serviced by the write queue
2015-09-25 13:27:03 +02:00
system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one
2015-12-05 01:11:25 +01:00
system.physmem.neitherReadNorWriteReqs 48490 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 11395 # Per bank write bursts
system.physmem.perBankRdBursts::1 10615 # Per bank write bursts
system.physmem.perBankRdBursts::2 11052 # Per bank write bursts
system.physmem.perBankRdBursts::3 11362 # Per bank write bursts
system.physmem.perBankRdBursts::4 12761 # Per bank write bursts
system.physmem.perBankRdBursts::5 10093 # Per bank write bursts
system.physmem.perBankRdBursts::6 10904 # Per bank write bursts
system.physmem.perBankRdBursts::7 11084 # Per bank write bursts
system.physmem.perBankRdBursts::8 10554 # Per bank write bursts
system.physmem.perBankRdBursts::9 10523 # Per bank write bursts
system.physmem.perBankRdBursts::10 10030 # Per bank write bursts
system.physmem.perBankRdBursts::11 8841 # Per bank write bursts
system.physmem.perBankRdBursts::12 9967 # Per bank write bursts
system.physmem.perBankRdBursts::13 10661 # Per bank write bursts
system.physmem.perBankRdBursts::14 9878 # Per bank write bursts
system.physmem.perBankRdBursts::15 10086 # Per bank write bursts
system.physmem.perBankWrBursts::0 8599 # Per bank write bursts
system.physmem.perBankWrBursts::1 7964 # Per bank write bursts
system.physmem.perBankWrBursts::2 8486 # Per bank write bursts
system.physmem.perBankWrBursts::3 8679 # Per bank write bursts
system.physmem.perBankWrBursts::4 7544 # Per bank write bursts
system.physmem.perBankWrBursts::5 7468 # Per bank write bursts
system.physmem.perBankWrBursts::6 8077 # Per bank write bursts
system.physmem.perBankWrBursts::7 8182 # Per bank write bursts
system.physmem.perBankWrBursts::8 8055 # Per bank write bursts
system.physmem.perBankWrBursts::9 7911 # Per bank write bursts
system.physmem.perBankWrBursts::10 7496 # Per bank write bursts
system.physmem.perBankWrBursts::11 6568 # Per bank write bursts
system.physmem.perBankWrBursts::12 7556 # Per bank write bursts
system.physmem.perBankWrBursts::13 8042 # Per bank write bursts
system.physmem.perBankWrBursts::14 7357 # Per bank write bursts
system.physmem.perBankWrBursts::15 7447 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2015-12-05 01:11:25 +01:00
system.physmem.numWrRetry 10 # Number of times write queue was full causing retry
system.physmem.totGap 2832912360000 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
2015-05-05 09:22:39 +02:00
system.physmem.readPktSize::2 542 # Read request sizes (log2)
2014-10-30 05:18:29 +01:00
system.physmem.readPktSize::3 14 # Read request sizes (log2)
2015-09-25 13:27:03 +02:00
system.physmem.readPktSize::4 2996 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2015-12-05 01:11:25 +01:00
system.physmem.readPktSize::6 166437 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
2014-10-30 05:18:29 +01:00
system.physmem.writePktSize::2 4381 # Write request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2015-12-05 01:11:25 +01:00
system.physmem.writePktSize::6 124958 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 150468 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 16446 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 2150 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 725 # What read queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
2014-10-30 05:18:29 +01:00
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
2013-05-30 18:54:18 +02:00
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
2015-12-05 01:11:25 +01:00
system.physmem.wrQLenPdf::15 2028 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2391 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5730 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 6051 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 6673 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6911 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 7819 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 7306 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 8204 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 8270 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 8353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 9948 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 7795 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 7406 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 7428 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 6937 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 6695 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 6529 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 304 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 260 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 184 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 181 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 129 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 148 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 104 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 103 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 125 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 96 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 130 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 99 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 72 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 97 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 84 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 85 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 61 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 102 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 84 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 51 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 76 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 64 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 30 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 20 # What write queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.wrQLenPdf::59 33 # What write queue length does an incoming req see
2015-12-05 01:11:25 +01:00
system.physmem.wrQLenPdf::60 18 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 24 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 30 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 62097 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 304.283685 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 179.850271 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 324.574400 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 23280 37.49% 37.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 14997 24.15% 61.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 6479 10.43% 72.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3584 5.77% 77.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2530 4.07% 81.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1603 2.58% 84.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1574 2.53% 87.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1048 1.69% 88.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 7002 11.28% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 62097 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6262 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 27.116097 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 564.155612 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 6261 99.98% 99.98% # Reads before turning the bus around for writes
2015-09-25 13:27:03 +02:00
system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
2015-12-05 01:11:25 +01:00
system.physmem.rdPerTurnAround::total 6262 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6262 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 20.030501 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.464444 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 12.039261 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 5446 86.97% 86.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 116 1.85% 88.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 36 0.57% 89.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 167 2.67% 92.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 22 0.35% 92.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 138 2.20% 94.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 54 0.86% 95.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 12 0.19% 95.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 19 0.30% 95.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 16 0.26% 96.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 6 0.10% 96.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 3 0.05% 96.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 160 2.56% 98.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 6 0.10% 99.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 9 0.14% 99.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 25 0.40% 99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 2 0.03% 99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 1 0.02% 99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 2 0.03% 99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 1 0.02% 99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 3 0.05% 99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 1 0.02% 99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119 1 0.02% 99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.02% 99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 13 0.21% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6262 # Writes before turning the bus around for reads
system.physmem.totQLat 2134847750 # Total ticks spent queuing
system.physmem.totMemAccLat 5318710250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 849030000 # Total ticks spent in databus transfers
system.physmem.avgQLat 12572.28 # Average queueing delay per DRAM burst
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2015-12-05 01:11:25 +01:00
system.physmem.avgMemAccLat 31322.28 # Average memory access latency per DRAM burst
2015-09-25 13:27:03 +02:00
system.physmem.avgRdBW 3.84 # Average DRAM read bandwidth in MiByte/s
2015-12-05 01:11:25 +01:00
system.physmem.avgWrBW 2.83 # Average achieved write bandwidth in MiByte/s
2015-09-25 13:27:03 +02:00
system.physmem.avgRdBWSys 3.78 # Average system read bandwidth in MiByte/s
2015-11-06 09:26:50 +01:00
system.physmem.avgWrBWSys 2.83 # Average system write bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-07-03 16:15:03 +02:00
system.physmem.busUtil 0.05 # Data bus utilization in percentage
2014-10-30 05:18:29 +01:00
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
2015-07-03 16:15:03 +02:00
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
2015-12-05 01:11:25 +01:00
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
system.physmem.avgWrQLen 26.05 # Average write queue length when enqueuing
system.physmem.readRowHits 139313 # Number of row buffer hits during reads
system.physmem.writeRowHits 93826 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.04 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 74.79 # Row buffer hit rate for writes
system.physmem.avgGap 9464241.10 # Average gap between requests
2015-11-06 09:26:50 +01:00
system.physmem.pageHitRate 78.96 # Row buffer hit rate, read and write combined
2015-12-05 01:11:25 +01:00
system.physmem_0.actEnergy 247680720 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 135143250 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 696267000 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 421193520 # Energy for write commands per rank (pJ)
2015-11-06 09:26:50 +01:00
system.physmem_0.refreshEnergy 185031927600 # Energy for refresh commands per rank (pJ)
2015-12-05 01:11:25 +01:00
system.physmem_0.actBackEnergy 83693103705 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1626331305750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1896556621545 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.472831 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 2705407276500 # Time in different power states
2015-11-06 09:26:50 +01:00
system.physmem_0.memoryStateTime::REF 94597100000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-12-05 01:11:25 +01:00
system.physmem_0.memoryStateTime::ACT 32908202000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-12-05 01:11:25 +01:00
system.physmem_1.actEnergy 221772600 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 121006875 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 628212000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 391599360 # Energy for write commands per rank (pJ)
2015-11-06 09:26:50 +01:00
system.physmem_1.refreshEnergy 185031927600 # Energy for refresh commands per rank (pJ)
2015-12-05 01:11:25 +01:00
system.physmem_1.actBackEnergy 81799663455 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1627992218250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1896186400140 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.342145 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 2708183660500 # Time in different power states
2015-11-06 09:26:50 +01:00
system.physmem_1.memoryStateTime::REF 94597100000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-12-05 01:11:25 +01:00
system.physmem_1.memoryStateTime::ACT 30129768250 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2014-10-30 05:18:29 +01:00
system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 128 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 45 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 45 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 45 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 45 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 45 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 45 # Total bandwidth to/from this memory (bytes/s)
2012-08-28 20:30:25 +02:00
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
2014-10-30 05:18:29 +01:00
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
2015-12-05 01:11:25 +01:00
system.cpu.branchPred.lookups 46857763 # Number of BP lookups
system.cpu.branchPred.condPredicted 24018162 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1233841 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 29502900 # Number of BTB lookups
system.cpu.branchPred.BTBHits 21322687 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2015-12-05 01:11:25 +01:00
system.cpu.branchPred.BTBHitPct 72.273190 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 11723693 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 33902 # Number of incorrect RAS predictions.
2014-11-12 15:05:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2014-12-23 15:31:20 +01:00
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-12-05 01:11:25 +01:00
system.cpu.checker.dtb.walker.walks 9704 # Table walker walks requested
system.cpu.checker.dtb.walker.walksShort 9704 # Table walker walks initiated with short descriptors
system.cpu.checker.dtb.walker.walkWaitTime::samples 9704 # Table walker wait (enqueue to first request) latency
system.cpu.checker.dtb.walker.walkWaitTime::0 9704 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.checker.dtb.walker.walkWaitTime::total 9704 # Table walker wait (enqueue to first request) latency
2015-09-25 13:27:03 +02:00
system.cpu.checker.dtb.walker.walksPending::samples 375751000 # Table walker pending requests distribution
system.cpu.checker.dtb.walker.walksPending::0 375751000 100.00% 100.00% # Table walker pending requests distribution
system.cpu.checker.dtb.walker.walksPending::total 375751000 # Table walker pending requests distribution
2015-12-05 01:11:25 +01:00
system.cpu.checker.dtb.walker.walkPageSizes::4K 6218 82.47% 82.47% # Table walker page sizes translated
system.cpu.checker.dtb.walker.walkPageSizes::1M 1322 17.53% 100.00% # Table walker page sizes translated
system.cpu.checker.dtb.walker.walkPageSizes::total 7540 # Table walker page sizes translated
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 9704 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 9704 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 7540 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7540 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin::total 17244 # Table walker requests started/completed, data/inst
2012-08-28 20:30:25 +02:00
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
2015-12-05 01:11:25 +01:00
system.cpu.checker.dtb.read_hits 24571778 # DTB read hits
system.cpu.checker.dtb.read_misses 8287 # DTB read misses
system.cpu.checker.dtb.write_hits 19630535 # DTB write hits
system.cpu.checker.dtb.write_misses 1417 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu.checker.dtb.flush_tlb 128 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2015-09-25 13:27:03 +02:00
system.cpu.checker.dtb.flush_entries 4283 # Number of entries that have been flushed from TLB
2012-08-28 20:30:25 +02:00
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
2015-11-06 09:26:50 +01:00
system.cpu.checker.dtb.prefetch_faults 1642 # Number of TLB faults due to prefetch
2012-08-28 20:30:25 +02:00
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2014-10-30 05:18:29 +01:00
system.cpu.checker.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
2015-12-05 01:11:25 +01:00
system.cpu.checker.dtb.read_accesses 24580065 # DTB read accesses
system.cpu.checker.dtb.write_accesses 19631952 # DTB write accesses
2012-08-28 20:30:25 +02:00
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
2015-12-05 01:11:25 +01:00
system.cpu.checker.dtb.hits 44202313 # DTB hits
system.cpu.checker.dtb.misses 9704 # DTB misses
system.cpu.checker.dtb.accesses 44212017 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-09-25 13:27:03 +02:00
system.cpu.checker.itb.walker.walks 4825 # Table walker walks requested
system.cpu.checker.itb.walker.walksShort 4825 # Table walker walks initiated with short descriptors
system.cpu.checker.itb.walker.walkWaitTime::samples 4825 # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.walker.walkWaitTime::0 4825 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.walker.walkWaitTime::total 4825 # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.walker.walksPending::samples 375090000 # Table walker pending requests distribution
system.cpu.checker.itb.walker.walksPending::0 375090000 100.00% 100.00% # Table walker pending requests distribution
system.cpu.checker.itb.walker.walksPending::total 375090000 # Table walker pending requests distribution
system.cpu.checker.itb.walker.walkPageSizes::4K 2798 88.26% 88.26% # Table walker page sizes translated
system.cpu.checker.itb.walker.walkPageSizes::1M 372 11.74% 100.00% # Table walker page sizes translated
system.cpu.checker.itb.walker.walkPageSizes::total 3170 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2015-09-25 13:27:03 +02:00
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 4825 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 4825 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2015-09-25 13:27:03 +02:00
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 3170 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 3170 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin::total 7995 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu.checker.itb.inst_hits 115776285 # ITB inst hits
2015-09-25 13:27:03 +02:00
system.cpu.checker.itb.inst_misses 4825 # ITB inst misses
2012-08-28 20:30:25 +02:00
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.write_hits 0 # DTB write hits
system.cpu.checker.itb.write_misses 0 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu.checker.itb.flush_tlb 128 # Number of times complete TLB was flushed
system.cpu.checker.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2015-09-25 13:27:03 +02:00
system.cpu.checker.itb.flush_entries 2976 # Number of entries that have been flushed from TLB
2012-08-28 20:30:25 +02:00
system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
2015-12-05 01:11:25 +01:00
system.cpu.checker.itb.inst_accesses 115781110 # ITB inst accesses
system.cpu.checker.itb.hits 115776285 # DTB hits
2015-09-25 13:27:03 +02:00
system.cpu.checker.itb.misses 4825 # DTB misses
2015-12-05 01:11:25 +01:00
system.cpu.checker.itb.accesses 115781110 # DTB accesses
system.cpu.checker.numCycles 139003519 # number of cpu cycles simulated
2012-08-28 20:30:25 +02:00
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
2014-12-23 15:31:20 +01:00
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-12-05 01:11:25 +01:00
system.cpu.dtb.walker.walks 71876 # Table walker walks requested
system.cpu.dtb.walker.walksShort 71876 # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29748 # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22357 # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksSquashedBefore 19771 # Table walks squashed before starting
system.cpu.dtb.walker.walkWaitTime::samples 52105 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::mean 423.395068 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::stdev 2574.283993 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0-4095 50327 96.59% 96.59% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::4096-8191 585 1.12% 97.71% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::8192-12287 525 1.01% 98.72% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::12288-16383 339 0.65% 99.37% # Table walker wait (enqueue to first request) latency
2015-11-06 09:26:50 +01:00
system.cpu.dtb.walker.walkWaitTime::16384-20479 52 0.10% 99.47% # Table walker wait (enqueue to first request) latency
2015-12-05 01:11:25 +01:00
system.cpu.dtb.walker.walkWaitTime::20480-24575 221 0.42% 99.89% # Table walker wait (enqueue to first request) latency
2015-11-06 09:26:50 +01:00
system.cpu.dtb.walker.walkWaitTime::24576-28671 14 0.03% 99.92% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::28672-32767 10 0.02% 99.94% # Table walker wait (enqueue to first request) latency
2015-12-05 01:11:25 +01:00
system.cpu.dtb.walker.walkWaitTime::32768-36863 8 0.02% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::36864-40959 5 0.01% 99.96% # Table walker wait (enqueue to first request) latency
2015-11-06 09:26:50 +01:00
system.cpu.dtb.walker.walkWaitTime::40960-45055 3 0.01% 99.97% # Table walker wait (enqueue to first request) latency
2015-12-05 01:11:25 +01:00
system.cpu.dtb.walker.walkWaitTime::45056-49151 12 0.02% 99.99% # Table walker wait (enqueue to first request) latency
2015-11-06 09:26:50 +01:00
system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::53248-57343 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::57344-61439 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::61440-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
2015-12-05 01:11:25 +01:00
system.cpu.dtb.walker.walkWaitTime::total 52105 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples 17499 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 11526.115778 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 9158.153521 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 8139.378931 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-32767 17316 98.95% 98.95% # Table walker service (enqueue to completion) latency
2015-11-06 09:26:50 +01:00
system.cpu.dtb.walker.walkCompletionTime::32768-65535 177 1.01% 99.97% # Table walker service (enqueue to completion) latency
2015-09-25 13:27:03 +02:00
system.cpu.dtb.walker.walkCompletionTime::131072-163839 5 0.03% 99.99% # Table walker service (enqueue to completion) latency
2015-12-05 01:11:25 +01:00
system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total 17499 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples 131377054816 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::mean 0.616890 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::stdev 0.493493 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0-1 131322424316 99.96% 99.96% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::2-3 37436500 0.03% 99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::4-5 7011000 0.01% 99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::6-7 6169000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::8-9 1200000 0.00% 100.00% # Table walker pending requests distribution
2015-11-06 09:26:50 +01:00
system.cpu.dtb.walker.walksPending::10-11 643000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::12-13 1366500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::14-15 794500 0.00% 100.00% # Table walker pending requests distribution
2015-07-03 16:15:03 +02:00
system.cpu.dtb.walker.walksPending::16-17 10000 0.00% 100.00% # Table walker pending requests distribution
2015-12-05 01:11:25 +01:00
system.cpu.dtb.walker.walksPending::total 131377054816 # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K 6345 82.32% 82.32% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::1M 1363 17.68% 100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total 7708 # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71876 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71876 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7708 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7708 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 79584 # Table walker requests started/completed, data/inst
2012-08-28 20:30:25 +02:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
2015-12-05 01:11:25 +01:00
system.cpu.dtb.read_hits 25445789 # DTB read hits
system.cpu.dtb.read_misses 61974 # DTB read misses
system.cpu.dtb.write_hits 19906281 # DTB write hits
system.cpu.dtb.write_misses 9902 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu.dtb.flush_tlb 128 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2015-11-06 09:26:50 +01:00
system.cpu.dtb.flush_entries 4317 # Number of entries that have been flushed from TLB
2015-12-05 01:11:25 +01:00
system.cpu.dtb.align_faults 357 # Number of TLB faults due to alignment restrictions
2015-11-06 09:26:50 +01:00
system.cpu.dtb.prefetch_faults 2185 # Number of TLB faults due to prefetch
2012-08-28 20:30:25 +02:00
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2015-11-06 09:26:50 +01:00
system.cpu.dtb.perms_faults 1330 # Number of TLB faults due to permissions restrictions
2015-12-05 01:11:25 +01:00
system.cpu.dtb.read_accesses 25507763 # DTB read accesses
system.cpu.dtb.write_accesses 19916183 # DTB write accesses
2012-08-28 20:30:25 +02:00
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
2015-12-05 01:11:25 +01:00
system.cpu.dtb.hits 45352070 # DTB hits
system.cpu.dtb.misses 71876 # DTB misses
system.cpu.dtb.accesses 45423946 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-12-05 01:11:25 +01:00
system.cpu.itb.walker.walks 11893 # Table walker walks requested
system.cpu.itb.walker.walksShort 11893 # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walksShortTerminationLevel::Level1 3935 # Level at which table walker walks with short descriptors terminate
2015-11-06 09:26:50 +01:00
system.cpu.itb.walker.walksShortTerminationLevel::Level2 7737 # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walksSquashedBefore 221 # Table walks squashed before starting
2015-12-05 01:11:25 +01:00
system.cpu.itb.walker.walkWaitTime::samples 11672 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::mean 618.017478 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::stdev 2885.502200 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0-4095 11116 95.24% 95.24% # Table walker wait (enqueue to first request) latency
2015-11-06 09:26:50 +01:00
system.cpu.itb.walker.walkWaitTime::4096-8191 159 1.36% 96.60% # Table walker wait (enqueue to first request) latency
2015-12-05 01:11:25 +01:00
system.cpu.itb.walker.walkWaitTime::8192-12287 192 1.64% 98.24% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::12288-16383 62 0.53% 98.77% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::16384-20479 98 0.84% 99.61% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::20480-24575 33 0.28% 99.90% # Table walker wait (enqueue to first request) latency
2015-11-06 09:26:50 +01:00
system.cpu.itb.walker.walkWaitTime::24576-28671 2 0.02% 99.91% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::28672-32767 7 0.06% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::45056-49151 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::49152-53247 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::57344-61439 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
2015-12-05 01:11:25 +01:00
system.cpu.itb.walker.walkWaitTime::total 11672 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples 3547 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 12874.259938 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 10191.545390 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 8701.526273 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-16383 2599 73.27% 73.27% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::16384-32767 890 25.09% 98.36% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::32768-49151 56 1.58% 99.94% # Table walker service (enqueue to completion) latency
2015-11-06 09:26:50 +01:00
system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.06% 100.00% # Table walker service (enqueue to completion) latency
2015-12-05 01:11:25 +01:00
system.cpu.itb.walker.walkCompletionTime::total 3547 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples 24002810416 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::mean 0.962951 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::stdev 0.189029 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 889895500 3.71% 3.71% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::1 23112364416 96.29% 100.00% # Table walker pending requests distribution
2015-11-06 09:26:50 +01:00
system.cpu.itb.walker.walksPending::2 493000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::3 57500 0.00% 100.00% # Table walker pending requests distribution
2015-12-05 01:11:25 +01:00
system.cpu.itb.walker.walksPending::total 24002810416 # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K 3008 90.44% 90.44% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::1M 318 9.56% 100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total 3326 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11893 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 11893 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3326 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 3326 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 15219 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 66221269 # ITB inst hits
system.cpu.itb.inst_misses 11893 # ITB inst misses
2012-08-28 20:30:25 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu.itb.flush_tlb 128 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2015-12-05 01:11:25 +01:00
system.cpu.itb.flush_entries 3094 # Number of entries that have been flushed from TLB
2012-08-28 20:30:25 +02:00
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
2015-12-05 01:11:25 +01:00
system.cpu.itb.perms_faults 2209 # Number of TLB faults due to permissions restrictions
2012-08-28 20:30:25 +02:00
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
2015-12-05 01:11:25 +01:00
system.cpu.itb.inst_accesses 66233162 # ITB inst accesses
system.cpu.itb.hits 66221269 # DTB hits
system.cpu.itb.misses 11893 # DTB misses
system.cpu.itb.accesses 66233162 # DTB accesses
system.cpu.numCycles 278796094 # number of cpu cycles simulated
2012-08-28 20:30:25 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-12-05 01:11:25 +01:00
system.cpu.fetch.icacheStallCycles 104750737 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 184597310 # Number of instructions fetch has processed
system.cpu.fetch.Branches 46857763 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 33046380 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 161828011 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 6150220 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 189816 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 10180 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 357136 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 560173 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 186 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 66221459 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 1133676 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 5180 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 270771349 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.831471 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.217911 # Number of instructions fetched each cycle (Total)
2012-08-28 20:30:25 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2015-12-05 01:11:25 +01:00
system.cpu.fetch.rateDist::0 171553381 63.36% 63.36% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 29224188 10.79% 74.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 14067085 5.20% 79.35% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 55926695 20.65% 100.00% # Number of instructions fetched each cycle (Total)
2012-08-28 20:30:25 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
2014-09-03 13:42:59 +02:00
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
2015-12-05 01:11:25 +01:00
system.cpu.fetch.rateDist::total 270771349 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.168072 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.662123 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 77850364 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 121893157 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 64586539 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 3844068 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 2597221 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 3423151 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 486287 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 157328219 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 3698916 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 2597221 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 83695488 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 11783440 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 76673328 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 62587040 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 33434832 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 146701505 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 957116 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 452960 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 63776 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 16375 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 30685156 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 150380164 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 678249075 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 164321181 # Number of integer rename lookups
2015-11-06 09:26:50 +01:00
system.cpu.rename.fp_rename_lookups 10889 # Number of floating rename lookups
2015-12-05 01:11:25 +01:00
system.cpu.rename.CommittedMaps 141709271 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 8670890 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 2840534 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 2644382 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 13862021 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 26394587 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 21292605 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1688978 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 2214312 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 143440731 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2121629 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 143228275 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 270765 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 8407822 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 14697300 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 125774 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 270771349 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.528964 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 0.865543 # Number of insts issued each cycle
2012-08-28 20:30:25 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2015-12-05 01:11:25 +01:00
system.cpu.iq.issued_per_cycle::0 182535287 67.41% 67.41% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 45134238 16.67% 84.08% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 32022031 11.83% 95.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 10269230 3.79% 99.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 810530 0.30% 100.00% # Number of insts issued each cycle
2015-11-06 09:26:50 +01:00
system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle
2014-09-03 13:42:59 +02:00
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
2012-08-28 20:30:25 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
2014-09-03 13:42:59 +02:00
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
2015-12-05 01:11:25 +01:00
system.cpu.iq.issued_per_cycle::total 270771349 # Number of insts issued each cycle
2012-08-28 20:30:25 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2015-12-05 01:11:25 +01:00
system.cpu.iq.fu_full::IntAlu 7336420 32.74% 32.74% # attempts to use FU when none available
2015-11-06 09:26:50 +01:00
system.cpu.iq.fu_full::IntMult 32 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.74% # attempts to use FU when none available
2015-12-05 01:11:25 +01:00
system.cpu.iq.fu_full::MemRead 5631672 25.13% 57.86% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 9443165 42.14% 100.00% # attempts to use FU when none available
2012-08-28 20:30:25 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2014-10-30 05:18:29 +01:00
system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued
2015-12-05 01:11:25 +01:00
system.cpu.iq.FU_type_0::IntAlu 95929589 66.98% 66.98% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 113798 0.08% 67.06% # Type of FU issued
2014-10-30 05:18:29 +01:00
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued
2015-11-06 09:26:50 +01:00
system.cpu.iq.FU_type_0::SimdFloatMisc 8576 0.01% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.06% # Type of FU issued
2015-12-05 01:11:25 +01:00
system.cpu.iq.FU_type_0::MemRead 26176168 18.28% 85.34% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 20997807 14.66% 100.00% # Type of FU issued
2012-08-28 20:30:25 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2015-12-05 01:11:25 +01:00
system.cpu.iq.FU_type_0::total 143228275 # Type of FU issued
system.cpu.iq.rate 0.513738 # Inst issue rate
system.cpu.iq.fu_busy_cnt 22411289 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.156473 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 579874368 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 153975557 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 140119306 # Number of integer instruction queue wakeup accesses
2015-11-06 09:26:50 +01:00
system.cpu.iq.fp_inst_queue_reads 35585 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 13122 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 11367 # Number of floating instruction queue wakeup accesses
2015-12-05 01:11:25 +01:00
system.cpu.iq.int_alu_accesses 165613882 # Number of integer alu accesses
2015-11-06 09:26:50 +01:00
system.cpu.iq.fp_alu_accesses 23345 # Number of floating point alu accesses
2015-12-05 01:11:25 +01:00
system.cpu.iew.lsq.thread0.forwLoads 322775 # Number of loads that had data forwarded from stores
2012-08-28 20:30:25 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2015-12-05 01:11:25 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 1495918 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 503 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 18543 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 704297 # Number of stores squashed
2012-08-28 20:30:25 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2015-12-05 01:11:25 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 87804 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 6457 # Number of times an access to memory failed due to the cache being blocked
2012-08-28 20:30:25 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2015-12-05 01:11:25 +01:00
system.cpu.iew.iewSquashCycles 2597221 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1240950 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 535645 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 145763292 # Number of instructions dispatched to IQ
2014-09-03 13:42:59 +02:00
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2015-12-05 01:11:25 +01:00
system.cpu.iew.iewDispLoadInsts 26394587 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 21292605 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1096200 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 17982 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 501480 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 18543 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 317940 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 471176 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 789116 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 142285522 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 25773547 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 870984 # Number of squashed instructions skipped in execute
2012-08-28 20:30:25 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
2015-12-05 01:11:25 +01:00
system.cpu.iew.exec_nop 200932 # number of nop insts executed
system.cpu.iew.exec_refs 46642466 # number of memory reference insts executed
system.cpu.iew.exec_branches 26501161 # Number of branches executed
system.cpu.iew.exec_stores 20868919 # Number of stores executed
system.cpu.iew.exec_rate 0.510357 # Inst execution rate
system.cpu.iew.wb_sent 141899022 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 140130673 # cumulative count of insts written-back
system.cpu.iew.wb_producers 63222272 # num instructions producing a value
system.cpu.iew.wb_consumers 95712658 # num instructions consuming a value
system.cpu.iew.wb_rate 0.502628 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.660542 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 7606616 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1995855 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 755952 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 267837215 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.512660 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.117818 # Number of insts commited each cycle
2012-08-28 20:30:25 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2015-12-05 01:11:25 +01:00
system.cpu.commit.committed_per_cycle::0 194442706 72.60% 72.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 43232016 16.14% 88.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 15468771 5.78% 94.51% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 4394333 1.64% 96.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 6341721 2.37% 98.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1685699 0.63% 99.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 801066 0.30% 99.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 412117 0.15% 99.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 1058786 0.40% 100.00% # Number of insts commited each cycle
2012-08-28 20:30:25 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2015-12-05 01:11:25 +01:00
system.cpu.commit.committed_per_cycle::total 267837215 # Number of insts commited each cycle
system.cpu.commit.committedInsts 113234248 # Number of instructions committed
system.cpu.commit.committedOps 137309439 # Number of ops (including micro ops) committed
2012-08-28 20:30:25 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
2015-12-05 01:11:25 +01:00
system.cpu.commit.refs 45486977 # Number of memory references committed
system.cpu.commit.loads 24898669 # Number of loads committed
system.cpu.commit.membars 814916 # Number of memory barriers committed
system.cpu.commit.branches 26015904 # Number of branches committed
2015-09-25 13:27:03 +02:00
system.cpu.commit.fp_insts 11364 # Number of committed floating point instructions.
2015-12-05 01:11:25 +01:00
system.cpu.commit.int_insts 120139692 # Number of committed integer instructions.
system.cpu.commit.function_calls 4881505 # Number of function calls committed.
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2015-12-05 01:11:25 +01:00
system.cpu.commit.op_class_0::IntAlu 91701155 66.78% 66.78% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 112732 0.08% 66.87% # Class of committed instruction
2014-10-30 05:18:29 +01:00
system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction
2015-11-06 09:26:50 +01:00
system.cpu.commit.op_class_0::SimdFloatMisc 8575 0.01% 66.87% # Class of committed instruction
2015-09-25 13:27:03 +02:00
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction
2015-12-05 01:11:25 +01:00
system.cpu.commit.op_class_0::MemRead 24898669 18.13% 85.01% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 20588308 14.99% 100.00% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2015-12-05 01:11:25 +01:00
system.cpu.commit.op_class_0::total 137309439 # Class of committed instruction
system.cpu.commit.bw_lim_events 1058786 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 389537878 # The number of ROB reads
system.cpu.rob.rob_writes 292763814 # The number of ROB writes
system.cpu.timesIdled 892824 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 8024745 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 5387029091 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 113079343 # Number of Instructions Simulated
system.cpu.committedOps 137154534 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 2.465491 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.465491 # CPI: Total CPI of All Threads
system.cpu.ipc 0.405599 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.405599 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 155725297 # number of integer regfile reads
system.cpu.int_regfile_writes 88564294 # number of integer regfile writes
2015-11-06 09:26:50 +01:00
system.cpu.fp_regfile_reads 9527 # number of floating regfile reads
2014-10-30 05:18:29 +01:00
system.cpu.fp_regfile_writes 2716 # number of floating regfile writes
2015-12-05 01:11:25 +01:00
system.cpu.cc_regfile_reads 502644824 # number of cc regfile reads
system.cpu.cc_regfile_writes 53156150 # number of cc regfile writes
system.cpu.misc_regfile_reads 348441241 # number of misc regfile reads
system.cpu.misc_regfile_writes 1521640 # number of misc regfile writes
system.cpu.dcache.tags.replacements 837355 # number of replacements
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.tagsinuse 511.925653 # Cycle average of tags in use
2015-12-05 01:11:25 +01:00
system.cpu.dcache.tags.total_refs 40093226 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 837867 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 47.851540 # Average number of references to valid blocks.
2015-09-25 13:27:03 +02:00
system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.occ_blocks::cpu.data 511.925653 # Average occupied blocks per requestor
2015-09-25 13:27:03 +02:00
system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999855 # Average percentage of cache occupancy
2014-11-12 15:05:25 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id
2014-11-12 15:05:25 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2015-12-05 01:11:25 +01:00
system.cpu.dcache.tags.tag_accesses 179262562 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 179262562 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 23296906 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 23296906 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 15545467 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 15545467 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 345973 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 345973 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 441682 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 441682 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 460325 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 460325 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 38842373 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 38842373 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 39188346 # number of overall hits
system.cpu.dcache.overall_hits::total 39188346 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 708692 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 708692 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 3602140 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 3602140 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 177879 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 177879 # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 27097 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 27097 # number of LoadLockedReq misses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.StoreCondReq_misses::cpu.data 7 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses
2015-12-05 01:11:25 +01:00
system.cpu.dcache.demand_misses::cpu.data 4310832 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 4310832 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 4488711 # number of overall misses
system.cpu.dcache.overall_misses::total 4488711 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11726844500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11726844500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 232349107178 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 232349107178 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 373049000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 373049000 # number of LoadLockedReq miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 305000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 305000 # number of StoreCondReq miss cycles
2015-12-05 01:11:25 +01:00
system.cpu.dcache.demand_miss_latency::cpu.data 244075951678 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 244075951678 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 244075951678 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 244075951678 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 24005598 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 24005598 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19147607 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19147607 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 523852 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 523852 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468779 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 468779 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460332 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 460332 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 43153205 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 43153205 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 43677057 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 43677057 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029522 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.029522 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188125 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.188125 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339560 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.339560 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057803 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057803 # miss rate for LoadLockedReq accesses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000015 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000015 # miss rate for StoreCondReq accesses
2015-12-05 01:11:25 +01:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.099896 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.099896 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.102770 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.102770 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16547.166470 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16547.166470 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64503.075166 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 64503.075166 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13767.169797 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13767.169797 # average LoadLockedReq miss latency
2015-11-06 09:26:50 +01:00
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 43571.428571 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 43571.428571 # average StoreCondReq miss latency
2015-12-05 01:11:25 +01:00
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56619.221458 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 56619.221458 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54375.510403 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 54375.510403 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 870696 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-12-05 01:11:25 +01:00
system.cpu.dcache.blocked::no_mshrs 6851 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
2015-12-05 01:11:25 +01:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 127.090352 # average number of cycles each access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
2015-12-05 01:11:25 +01:00
system.cpu.dcache.writebacks::writebacks 695416 # number of writebacks
system.cpu.dcache.writebacks::total 695416 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 295634 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 295634 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3302552 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 3302552 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18703 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 18703 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 3598186 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 3598186 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 3598186 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 3598186 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 413058 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 413058 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299588 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 299588 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119604 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 119604 # number of SoftPFReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8394 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 8394 # number of LoadLockedReq MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 7 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses
2015-12-05 01:11:25 +01:00
system.cpu.dcache.demand_mshr_misses::cpu.data 712646 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 712646 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 832250 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 832250 # number of overall MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31129 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total 31129 # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27585 # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total 27585 # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses
2015-12-05 01:11:25 +01:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6391901000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6391901000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19972155480 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 19972155480 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1700460500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1700460500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 126799500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 126799500 # number of LoadLockedReq MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 298000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 298000 # number of StoreCondReq MSHR miss cycles
2015-12-05 01:11:25 +01:00
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26364056480 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 26364056480 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28064516980 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 28064516980 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6276327500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6276327500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5075770951 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5075770951 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11352098451 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 11352098451 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017207 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017207 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015646 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015646 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228316 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228316 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017906 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017906 # mshr miss rate for LoadLockedReq accesses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000015 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000015 # mshr miss rate for StoreCondReq accesses
2015-12-05 01:11:25 +01:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016514 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.016514 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019055 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.019055 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15474.584683 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15474.584683 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66665.405423 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66665.405423 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14217.421658 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14217.421658 # average SoftPFReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15105.968549 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15105.968549 # average LoadLockedReq mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 42571.428571 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 42571.428571 # average StoreCondReq mshr miss latency
2015-12-05 01:11:25 +01:00
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36994.603885 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 36994.603885 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33721.258011 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 33721.258011 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201623.164894 # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201623.164894 # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184004.747181 # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184004.747181 # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193345.683329 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193345.683329 # average overall mshr uncacheable latency
2014-11-12 15:05:25 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-12-05 01:11:25 +01:00
system.cpu.icache.tags.replacements 1886675 # number of replacements
system.cpu.icache.tags.tagsinuse 511.154168 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 64239376 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 1887187 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 34.039751 # Average number of references to valid blocks.
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.warmup_cycle 16318088500 # Cycle when the warmup percentage was hit.
2015-12-05 01:11:25 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 511.154168 # Average occupied blocks per requestor
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.occ_percent::cpu.inst 0.998348 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.998348 # Average percentage of cache occupancy
2014-11-12 15:05:25 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id
2015-09-25 13:27:03 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
2014-11-12 15:05:25 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2015-12-05 01:11:25 +01:00
system.cpu.icache.tags.tag_accesses 68105664 # Number of tag accesses
system.cpu.icache.tags.data_accesses 68105664 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 64239376 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 64239376 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 64239376 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 64239376 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 64239376 # number of overall hits
system.cpu.icache.overall_hits::total 64239376 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1979079 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1979079 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1979079 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1979079 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1979079 # number of overall misses
system.cpu.icache.overall_misses::total 1979079 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 28144068491 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 28144068491 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 28144068491 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 28144068491 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 28144068491 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 28144068491 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 66218455 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 66218455 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 66218455 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 66218455 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 66218455 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 66218455 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029887 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.029887 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.029887 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.029887 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.029887 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.029887 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14220.790828 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14220.790828 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14220.790828 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14220.790828 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14220.790828 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14220.790828 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 5080 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-12-05 01:11:25 +01:00
system.cpu.icache.blocked::no_mshrs 162 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
2015-12-05 01:11:25 +01:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 31.358025 # average number of cycles each access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
2012-08-28 20:30:25 +02:00
system.cpu.icache.cache_copies 0 # number of cache copies performed
2015-12-05 01:11:25 +01:00
system.cpu.icache.writebacks::writebacks 1886675 # number of writebacks
system.cpu.icache.writebacks::total 1886675 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91868 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 91868 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 91868 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 91868 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 91868 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 91868 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1887211 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1887211 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1887211 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1887211 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1887211 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1887211 # number of overall MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3004 # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total 3004 # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3004 # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total 3004 # number of overall MSHR uncacheable misses
2015-12-05 01:11:25 +01:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25180995493 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 25180995493 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25180995493 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 25180995493 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25180995493 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 25180995493 # number of overall MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 377667500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 377667500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 377667500 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 377667500 # number of overall MSHR uncacheable cycles
2015-12-05 01:11:25 +01:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028500 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028500 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028500 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.028500 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028500 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.028500 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13342.967741 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13342.967741 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13342.967741 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13342.967741 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13342.967741 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13342.967741 # average overall mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 125721.537949 # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125721.537949 # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125721.537949 # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125721.537949 # average overall mshr uncacheable latency
2012-08-28 20:30:25 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.tags.replacements 96487 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65023.312748 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 4997676 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 161725 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 30.902309 # Average number of references to valid blocks.
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.tags.occ_blocks::writebacks 49475.678025 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.897856 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 1.835471 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 10343.602046 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 5191.299351 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.754939 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000166 # Average percentage of cache occupancy
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000028 # Average percentage of cache occupancy
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.157831 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.079213 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.992177 # Average percentage of cache occupancy
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_task_id_blocks::1023 12 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65226 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2890 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6640 # Occupied blocks per task id
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55530 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000183 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995270 # Percentage of cache occupancy per task id
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.tags.tag_accesses 44233161 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 44233161 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 54581 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11841 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 66422 # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks 695416 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 695416 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 1846676 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 1846676 # number of WritebackClean hits
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.UpgradeReq_hits::cpu.data 33 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 33 # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 4 # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 161568 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 161568 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1867325 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1867325 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 527485 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 527485 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 54581 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 11841 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 1867325 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 689053 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2622800 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 54581 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 11841 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 1867325 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 689053 # number of overall hits
system.cpu.l2cache.overall_hits::total 2622800 # number of overall hits
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 21 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 8 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 29 # number of ReadReq misses
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2721 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 2721 # number of UpgradeReq misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 135393 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 135393 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 19844 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 19844 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 13444 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 13444 # number of ReadSharedReq misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_misses::cpu.dtb.walker 21 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 8 # number of demand (read+write) misses
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.demand_misses::cpu.inst 19844 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 148837 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 168710 # number of demand (read+write) misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_misses::cpu.dtb.walker 21 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 8 # number of overall misses
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.overall_misses::cpu.inst 19844 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 148837 # number of overall misses
system.cpu.l2cache.overall_misses::total 168710 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3081000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 1062000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 4143000 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 2179500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 2179500 # number of UpgradeReq miss cycles
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162000 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162000 # number of SCUpgradeReq miss cycles
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 17603720000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 17603720000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2626422000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 2626422000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1819515000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 1819515000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3081000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 1062000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 2626422000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 19423235000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 22053800000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3081000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 1062000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 2626422000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 19423235000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 22053800000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 54602 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11849 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 66451 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks 695416 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 695416 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 1846676 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 1846676 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2754 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2754 # number of UpgradeReq accesses(hits+misses)
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 7 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 7 # number of SCUpgradeReq accesses(hits+misses)
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 296961 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 296961 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1887169 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 1887169 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 540929 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 540929 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 54602 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 11849 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 1887169 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 837890 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2791510 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 54602 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 11849 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1887169 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 837890 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2791510 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000385 # miss rate for ReadReq accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000675 # miss rate for ReadReq accesses
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadReq_miss_rate::total 0.000436 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988017 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988017 # miss rate for UpgradeReq accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.428571 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.428571 # miss rate for SCUpgradeReq accesses
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.455929 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.455929 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010515 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010515 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024854 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024854 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000385 # miss rate for demand accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000675 # miss rate for demand accesses
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010515 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.177633 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.060437 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000385 # miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000675 # miss rate for overall accesses
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010515 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.177633 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.060437 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 146714.285714 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 132750 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 142862.068966 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 800.992282 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 800.992282 # average UpgradeReq miss latency
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 54000 # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 54000 # average SCUpgradeReq miss latency
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 130019.424933 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 130019.424933 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132353.456964 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132353.456964 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 135340.300506 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 135340.300506 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 146714.285714 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 132750 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132353.456964 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 130500.043672 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 130720.170707 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 146714.285714 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 132750 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132353.456964 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 130500.043672 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 130720.170707 # average overall miss latency
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.writebacks::writebacks 88798 # number of writebacks
system.cpu.l2cache.writebacks::total 88798 # number of writebacks
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 26 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 26 # number of ReadCleanReq MSHR hits
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 113 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 113 # number of ReadSharedReq MSHR hits
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.demand_mshr_hits::cpu.inst 26 # number of demand (read+write) MSHR hits
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.demand_mshr_hits::cpu.data 113 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 139 # number of demand (read+write) MSHR hits
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_mshr_hits::cpu.inst 26 # number of overall MSHR hits
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.overall_mshr_hits::cpu.data 113 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 139 # number of overall MSHR hits
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 21 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 8 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 29 # number of ReadReq MSHR misses
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2721 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2721 # number of UpgradeReq MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 135393 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 135393 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 19818 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19818 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 13331 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 13331 # number of ReadSharedReq MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 21 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 8 # number of demand (read+write) MSHR misses
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 19818 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 148724 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 168571 # number of demand (read+write) MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 21 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 8 # number of overall MSHR misses
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.inst 19818 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 148724 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 168571 # number of overall MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3004 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31129 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34133 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27585 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27585 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3004 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61718 # number of overall MSHR uncacheable misses
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2871000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 982000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3853000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 192556500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 192556500 # number of UpgradeReq MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 212500 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 212500 # number of SCUpgradeReq MSHR miss cycles
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16249790000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16249790000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2425294500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2425294500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1672223500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1672223500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2871000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 982000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2425294500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17922013500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 20351161000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2871000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 982000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2425294500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17922013500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 20351161000 # number of overall MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 340117000 # number of ReadReq MSHR uncacheable cycles
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5887205500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6227322500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4756953000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4756953000 # number of WriteReq MSHR uncacheable cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 340117000 # number of overall MSHR uncacheable cycles
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10644158500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10984275500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000385 # mshr miss rate for ReadReq accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000675 # mshr miss rate for ReadReq accesses
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000436 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.988017 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.988017 # mshr miss rate for UpgradeReq accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.428571 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.428571 # mshr miss rate for SCUpgradeReq accesses
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455929 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455929 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010501 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010501 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024645 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024645 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000385 # mshr miss rate for demand accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000675 # mshr miss rate for demand accesses
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010501 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177498 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.060387 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000385 # mshr miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000675 # mshr miss rate for overall accesses
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010501 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177498 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.060387 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 136714.285714 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122750 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 132862.068966 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70766.813671 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70766.813671 # average UpgradeReq mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70833.333333 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70833.333333 # average SCUpgradeReq mshr miss latency
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 120019.424933 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 120019.424933 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122378.368150 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122378.368150 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125438.714275 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125438.714275 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 136714.285714 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122750 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122378.368150 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120505.187461 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120727.533206 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 136714.285714 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122750 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122378.368150 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120505.187461 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120727.533206 # average overall mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113221.371505 # average ReadReq mshr uncacheable latency
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189122.859713 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182442.870536 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172447.090810 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172447.090810 # average WriteReq mshr uncacheable latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113221.371505 # average overall mshr uncacheable latency
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181288.253228 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177975.234129 # average overall mshr uncacheable latency
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.snoop_filter.tot_requests 5483387 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2758318 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 47114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 382 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 382 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.trans_dist::ReadReq 128004 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2556278 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 27585 # Transaction distribution
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.trans_dist::WritebackDirty 820384 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 1846676 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 142776 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2755 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 296961 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 296961 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1887211 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 541178 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.trans_dist::InvalidateReq 36194 # Transaction distribution
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5627062 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2629120 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31258 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 129064 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 8416504 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 239014016 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98323369 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 47396 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 218408 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 337603189 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 196948 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 3052801 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.025889 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.158805 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.snoop_fanout::0 2973766 97.41% 97.41% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 79035 2.59% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.snoop_fanout::total 3052801 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 5399625997 # Layer occupancy (ticks)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 264877 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.respLayer0.occupancy 2834640846 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 1303359054 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.respLayer2.occupancy 19415986 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.respLayer3.occupancy 74513896 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.trans_dist::ReadReq 30198 # Transaction distribution
system.iobus.trans_dist::ReadResp 30198 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.iobus.trans_dist::WriteResp 59014 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 178424 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2480349 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer0.occupancy 43090500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer1.occupancy 99500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer2.occupancy 325000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer3.occupancy 29000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer4.occupancy 14500 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 91000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer8.occupancy 648000 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer16.occupancy 48500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer18.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer20.occupancy 9500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer23.occupancy 6193500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer24.occupancy 33084000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer25.occupancy 186380025 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2015-03-02 11:04:20 +01:00
system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.respLayer3.occupancy 36770000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iocache.tags.replacements 36409 # number of replacements
2015-12-05 01:11:25 +01:00
system.iocache.tags.tagsinuse 1.005380 # Cycle average of tags in use
2015-11-06 09:26:50 +01:00
system.iocache.tags.total_refs 30 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36425 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000824 # Average number of references to valid blocks.
2015-12-05 01:11:25 +01:00
system.iocache.tags.warmup_cycle 256605907000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 1.005380 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.062836 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.062836 # Average percentage of cache occupancy
2014-10-30 05:18:29 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2015-11-06 09:26:50 +01:00
system.iocache.tags.tag_accesses 328227 # Number of tag accesses
system.iocache.tags.data_accesses 328227 # Number of data accesses
system.iocache.WriteLineReq_hits::realview.ide 29 # number of WriteLineReq hits
system.iocache.WriteLineReq_hits::total 29 # number of WriteLineReq hits
system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses
system.iocache.ReadReq_misses::total 249 # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide 36195 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 36195 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide 249 # number of demand (read+write) misses
system.iocache.demand_misses::total 249 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 249 # number of overall misses
system.iocache.overall_misses::total 249 # number of overall misses
2015-12-05 01:11:25 +01:00
system.iocache.ReadReq_miss_latency::realview.ide 31316876 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 31316876 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 4717082149 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 4717082149 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide 31316876 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 31316876 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 31316876 # number of overall miss cycles
system.iocache.overall_miss_latency::total 31316876 # number of overall miss cycles
2015-11-06 09:26:50 +01:00
system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2015-11-06 09:26:50 +01:00
system.iocache.demand_accesses::realview.ide 249 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 249 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 249 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 249 # number of overall (read+write) accesses
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2015-11-06 09:26:50 +01:00
system.iocache.WriteLineReq_miss_rate::realview.ide 0.999199 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 0.999199 # miss rate for WriteLineReq accesses
2014-10-30 05:18:29 +01:00
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2015-12-05 01:11:25 +01:00
system.iocache.ReadReq_avg_miss_latency::realview.ide 125770.586345 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 125770.586345 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130324.137284 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 130324.137284 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 125770.586345 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 125770.586345 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 125770.586345 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 125770.586345 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 902 # number of cycles access was blocked
2012-08-28 20:30:25 +02:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-12-05 01:11:25 +01:00
system.iocache.blocked::no_mshrs 96 # number of cycles access was blocked
2012-08-28 20:30:25 +02:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2015-12-05 01:11:25 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 9.395833 # average number of cycles each access was blocked
2012-08-28 20:30:25 +02:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
2012-08-28 20:30:25 +02:00
system.iocache.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.iocache.writebacks::writebacks 36160 # number of writebacks
system.iocache.writebacks::total 36160 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide 249 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 36195 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 36195 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide 249 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 249 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 249 # number of overall MSHR misses
2015-12-05 01:11:25 +01:00
system.iocache.ReadReq_mshr_miss_latency::realview.ide 18866876 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 18866876 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2907332149 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 2907332149 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 18866876 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 18866876 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 18866876 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 18866876 # number of overall MSHR miss cycles
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2015-11-06 09:26:50 +01:00
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999199 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 0.999199 # mshr miss rate for WriteLineReq accesses
2014-10-30 05:18:29 +01:00
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2015-12-05 01:11:25 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75770.586345 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 75770.586345 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80324.137284 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80324.137284 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 75770.586345 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 75770.586345 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 75770.586345 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 75770.586345 # average overall mshr miss latency
2012-08-28 20:30:25 +02:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::ReadReq 34133 # Transaction distribution
2015-12-05 01:11:25 +01:00
system.membus.trans_dist::ReadResp 67559 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::WriteReq 27585 # Transaction distribution
system.membus.trans_dist::WriteResp 27585 # Transaction distribution
2015-12-05 01:11:25 +01:00
system.membus.trans_dist::WritebackDirty 124958 # Transaction distribution
system.membus.trans_dist::CleanEvict 7701 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4594 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
2015-12-05 01:11:25 +01:00
system.membus.trans_dist::UpgradeResp 4597 # Transaction distribution
system.membus.trans_dist::ReadExReq 133521 # Transaction distribution
system.membus.trans_dist::ReadExResp 133521 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 33427 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::InvalidateReq 36194 # Transaction distribution
system.membus.trans_dist::InvalidateResp 36194 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2076 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 454663 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 562233 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108826 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 108826 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.membus.pkt_count::total 671059 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16401756 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16565161 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2315200 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2315200 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.membus.pkt_size::total 18880361 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.membus.snoops 513 # Total snoops (count)
2015-12-05 01:11:25 +01:00
system.membus.snoop_fanout::samples 402363 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2015-12-05 01:11:25 +01:00
system.membus.snoop_fanout::1 402363 100.00% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2015-12-05 01:11:25 +01:00
system.membus.snoop_fanout::total 402363 # Request fanout histogram
system.membus.reqLayer0.occupancy 83709500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-03-02 11:04:20 +01:00
system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.membus.reqLayer2.occupancy 1749000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.membus.reqLayer5.occupancy 873720378 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.membus.respLayer2.occupancy 987389399 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.membus.respLayer3.occupancy 64116283 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-12-04 01:19:05 +01:00
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
2014-11-12 15:05:25 +01:00
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
2015-12-04 01:19:05 +01:00
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
2012-08-28 20:30:25 +02:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
2015-09-25 13:27:03 +02:00
system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed
2012-08-28 20:30:25 +02:00
---------- End Simulation Statistics ----------
