2006-10-23 13:57:16 +02:00
---------- Begin Simulation Statistics ----------
2015-11-06 09:26:50 +01:00
sim_seconds 0.000031 # Number of seconds simulated
sim_ticks 30526500 # Number of ticks simulated
final_tick 30526500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2011-06-10 09:45:24 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-01-22 16:42:13 +01:00
host_inst_rate 33063 # Simulator instruction rate (inst/s)
host_op_rate 33056 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 189395194 # Simulator tick rate (ticks/s)
host_mem_usage 228956 # Number of bytes of host memory used
host_seconds 0.16 # Real time elapsed on the host
2012-08-15 16:38:05 +02:00
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2012-06-05 07:23:16 +02:00
system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory
system.physmem.bytes_read::total 24896 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 16320 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 16320 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
system.physmem.num_reads::total 389 # Number of read requests responded to by this memory
2015-11-06 09:26:50 +01:00
system.physmem.bw_read::cpu.inst 534617464 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 280936236 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 815553699 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 534617464 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 534617464 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 534617464 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 280936236 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 815553699 # Total bandwidth to/from this memory (bytes/s)
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2011-06-10 09:45:24 +02:00
system.cpu.workload.num_syscalls 11 # Number of system calls
2015-11-06 09:26:50 +01:00
system.cpu.numCycles 61053 # number of cpu cycles simulated
2011-06-10 09:45:24 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2012-08-15 16:38:05 +02:00
system.cpu.committedInsts 5327 # Number of instructions committed
system.cpu.committedOps 5327 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses
2011-06-10 09:45:24 +02:00
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 146 # number of times a function call or return occured
2012-08-15 16:38:05 +02:00
system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls
system.cpu.num_int_insts 4505 # number of integer instructions
2011-06-10 09:45:24 +02:00
system.cpu.num_fp_insts 0 # number of float instructions
2012-08-15 16:38:05 +02:00
system.cpu.num_int_register_reads 10598 # number of times the integer registers were read
system.cpu.num_int_register_writes 4845 # number of times the integer registers were written
2011-06-10 09:45:24 +02:00
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
2012-08-15 16:38:05 +02:00
system.cpu.num_mem_refs 1401 # number of memory refs
system.cpu.num_load_insts 723 # Number of load instructions
2011-06-10 09:45:24 +02:00
system.cpu.num_store_insts 678 # Number of store instructions
2014-10-20 23:48:19 +02:00
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
2015-11-06 09:26:50 +01:00
system.cpu.num_busy_cycles 61052.998000 # Number of busy cycles
2014-10-20 23:48:19 +02:00
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
2014-02-16 18:40:34 +01:00
system.cpu.Branches 1121 # Number of branches fetched
2014-05-10 00:58:50 +02:00
system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction
system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction
system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction
system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 5370 # Class of executed instruction
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.replacements 0 # number of replacements
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.tagsinuse 81.961543 # Cycle average of tags in use
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.occ_blocks::cpu.data 81.961543 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.020010 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.020010 # Average percentage of cache occupancy
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits
system.cpu.dcache.overall_hits::total 1253 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses
system.cpu.dcache.overall_misses::total 135 # number of overall misses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3300000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 3300000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5022000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 5022000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 8322000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 8322000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 8322000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 8322000 # number of overall miss cycles
2015-03-02 11:04:20 +01:00
system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075524 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.075524 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61111.111111 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 61111.111111 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 61644.444444 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 61644.444444 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 61644.444444 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 61644.444444 # average overall miss latency
2015-03-02 11:04:20 +01:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3246000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3246000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4941000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4941000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8187000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 8187000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8187000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 8187000 # number of overall MSHR miss cycles
2015-03-02 11:04:20 +01:00
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60111.111111 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60111.111111 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60644.444444 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 60644.444444 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60644.444444 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 60644.444444 # average overall mshr miss latency
2015-03-02 11:04:20 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.replacements 0 # number of replacements
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.tagsinuse 116.865384 # Cycle average of tags in use
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 116.865384 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.057063 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.057063 # Average percentage of cache occupancy
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 0.125488 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 10999 # Number of tag accesses
system.cpu.icache.tags.data_accesses 10999 # Number of data accesses
2012-08-15 16:38:05 +02:00
system.cpu.icache.ReadReq_hits::cpu.inst 5114 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 5114 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 5114 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 5114 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 5114 # number of overall hits
system.cpu.icache.overall_hits::total 5114 # number of overall hits
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_misses::cpu.inst 257 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 257 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 257 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses
system.cpu.icache.overall_misses::total 257 # number of overall misses
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15838500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 15838500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 15838500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 15838500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 15838500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 15838500 # number of overall miss cycles
2012-08-15 16:38:05 +02:00
system.cpu.icache.ReadReq_accesses::cpu.inst 5371 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 5371 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 5371 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 5371 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 5371 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 5371 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.047850 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.047850 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.047850 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.047850 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.047850 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.047850 # miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61628.404669 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 61628.404669 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61628.404669 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 61628.404669 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61628.404669 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 61628.404669 # average overall miss latency
2011-06-10 09:45:24 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2011-06-10 09:45:24 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 257 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 257 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 257 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15581500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 15581500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15581500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 15581500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15581500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 15581500 # number of overall MSHR miss cycles
2012-08-15 16:38:05 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047850 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.047850 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.047850 # mshr miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60628.404669 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60628.404669 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60628.404669 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 60628.404669 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60628.404669 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 60628.404669 # average overall mshr miss latency
2011-06-10 09:45:24 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.replacements 0 # number of replacements
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.tagsinuse 141.950442 # Cycle average of tags in use
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.319383 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 25.631059 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003550 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000782 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.004332 # Average percentage of cache occupancy
2014-01-24 22:29:33 +01:00
system.cpu.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id
2014-01-24 22:29:33 +01:00
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009399 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 3525 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 3525 # Number of data accesses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
system.cpu.l2cache.overall_hits::total 3 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 81 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 81 # number of ReadExReq misses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 255 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 255 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 53 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 53 # number of ReadSharedReq misses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_misses::cpu.inst 255 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 389 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 255 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
system.cpu.l2cache.overall_misses::total 389 # number of overall misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4819500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 4819500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 15173000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 15173000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3153500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 3153500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 15173000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 7973000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 23146000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 15173000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 7973000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 23146000 # number of overall miss cycles
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 81 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 81 # number of ReadExReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 257 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 257 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 54 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 54 # number of ReadSharedReq accesses(hits+misses)
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_accesses::cpu.inst 257 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 392 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 257 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 135 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 392 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.992218 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.992218 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.981481 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.981481 # miss rate for ReadSharedReq accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992218 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.demand_miss_rate::total 0.992347 # miss rate for demand accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992218 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.overall_miss_rate::total 0.992347 # miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.960784 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.960784 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.960784 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 59501.285347 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.960784 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 59501.285347 # average overall miss latency
2009-04-22 19:25:17 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2011-06-10 09:45:24 +02:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2011-06-10 09:45:24 +02:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
2006-10-23 13:57:16 +02:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 81 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 81 # number of ReadExReq MSHR misses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 255 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 255 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 53 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 53 # number of ReadSharedReq MSHR misses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 255 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 389 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 255 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 389 # number of overall MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4009500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4009500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12623000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12623000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2623500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2623500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12623000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6633000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 19256000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12623000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6633000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 19256000 # number of overall MSHR miss cycles
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.992218 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.981481 # mshr miss rate for ReadSharedReq accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::total 0.992347 # mshr miss rate for demand accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::total 0.992347 # mshr miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.960784 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.960784 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.960784 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.285347 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.960784 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.285347 # average overall mshr miss latency
2011-06-10 09:45:24 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.tot_requests 392 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 3 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.trans_dist::ReadCleanReq 257 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 54 # Transaction distribution
2013-08-19 09:52:36 +02:00
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 514 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 784 # Packet count per connected master and slave (bytes)
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16448 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 25088 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 392 # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::mean 0.007653 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.087258 # Request fanout histogram
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::0 389 99.23% 99.23% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 3 0.77% 100.00% # Request fanout histogram
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 392 # Request fanout histogram
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 385500 # Layer occupancy (ticks)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
2015-03-02 11:04:20 +01:00
system.membus.trans_dist::ReadResp 308 # Transaction distribution
system.membus.trans_dist::ReadExReq 81 # Transaction distribution
system.membus.trans_dist::ReadExResp 81 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::ReadSharedReq 308 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 389 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 389 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 389 # Request fanout histogram
system.membus.reqLayer0.occupancy 389500 # Layer occupancy (ticks)
2015-11-06 09:26:50 +01:00
system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
system.membus.respLayer1.occupancy 1945000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 6.4 # Layer utilization (%)
2006-10-23 13:57:16 +02:00
---------- End Simulation Statistics ----------
