2007-01-03 06:52:30 +01:00
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// Copyright (c) 2006-2007 The Regents of The University of Michigan
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2006-05-22 20:29:33 +02:00
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Ali Saidi
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// Gabe Black
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// Steve Reinhardt
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2006-01-29 23:25:54 +01:00
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////////////////////////////////////////////////////////////////////
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//
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// The actual decoder specification
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//
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2006-03-16 19:58:50 +01:00
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decode OP default Unknown::unknown()
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{
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0x0: decode OP2
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{
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2010-11-11 11:03:58 +01:00
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// Throw an illegal instruction acception
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2014-10-16 11:49:51 +02:00
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0x0: Trap::illtrap({{fault = std::make_shared<IllegalInstruction>();}});
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2006-07-19 08:07:00 +02:00
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format BranchN
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2006-03-17 20:02:38 +01:00
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{
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2010-11-11 11:03:58 +01:00
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// bpcc
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2006-08-22 04:41:57 +02:00
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0x1: decode COND2
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2006-03-16 19:58:50 +01:00
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{
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2010-11-11 11:03:58 +01:00
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// Branch Always
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2007-09-26 05:05:11 +02:00
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0x8: bpa(19, annul_code={{
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2010-12-08 09:27:43 +01:00
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NPC = PC + disp;
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NNPC = PC + disp + 4;
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2007-09-26 05:05:11 +02:00
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}});
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2010-11-11 11:03:58 +01:00
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// Branch Never
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2007-09-26 05:05:11 +02:00
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0x0: bpn(19, {{;}},
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annul_code={{
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2010-12-08 09:27:43 +01:00
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NNPC = NPC + 8;
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NPC = NPC + 4;
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2007-09-26 05:05:11 +02:00
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}});
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2006-08-22 04:41:57 +02:00
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default: decode BPCC
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{
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2007-09-26 05:05:11 +02:00
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0x0: bpcci(19, test={{passesCondition(Ccr<3:0>, COND2)}});
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0x2: bpccx(19, test={{passesCondition(Ccr<7:4>, COND2)}});
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2006-08-22 04:41:57 +02:00
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}
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2006-03-17 20:02:38 +01:00
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}
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2010-11-11 11:03:58 +01:00
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// bicc
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2006-11-10 21:27:06 +01:00
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0x2: decode COND2
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{
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2010-11-11 11:03:58 +01:00
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// Branch Always
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2007-09-26 05:05:11 +02:00
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0x8: ba(22, annul_code={{
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2010-12-08 09:27:43 +01:00
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NPC = PC + disp;
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NNPC = PC + disp + 4;
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2007-09-26 05:05:11 +02:00
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}});
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2010-11-11 11:03:58 +01:00
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// Branch Never
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2007-09-26 05:05:11 +02:00
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0x0: bn(22, {{;}},
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annul_code={{
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2010-12-08 09:27:43 +01:00
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NNPC = NPC + 8;
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NPC = NPC + 4;
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2007-09-26 05:05:11 +02:00
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}});
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default: bicc(22, test={{passesCondition(Ccr<3:0>, COND2)}});
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2006-11-10 21:27:06 +01:00
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}
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2006-04-01 03:31:53 +02:00
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}
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0x3: decode RCOND2
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{
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format BranchSplit
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2006-03-16 19:58:50 +01:00
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{
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2011-09-27 08:48:54 +02:00
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0x1: bpreq(test={{Rs1_sdw == 0}});
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0x2: bprle(test={{Rs1_sdw <= 0}});
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0x3: bprl(test={{Rs1_sdw < 0}});
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0x5: bprne(test={{Rs1_sdw != 0}});
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0x6: bprg(test={{Rs1_sdw > 0}});
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0x7: bprge(test={{Rs1_sdw >= 0}});
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2006-03-16 19:58:50 +01:00
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}
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2006-03-17 20:02:38 +01:00
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}
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2010-11-11 11:03:58 +01:00
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// SETHI (or NOP if rd == 0 and imm == 0)
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2011-09-27 08:48:54 +02:00
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0x4: SetHi::sethi({{Rd_udw = imm;}});
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2010-11-11 11:03:58 +01:00
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// fbpfcc
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2007-01-30 22:12:38 +01:00
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0x5: decode COND2 {
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format BranchN {
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2010-11-11 11:03:58 +01:00
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// Branch Always
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2007-09-26 05:05:11 +02:00
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0x8: fbpa(22, annul_code={{
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2010-12-08 09:27:43 +01:00
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NPC = PC + disp;
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NNPC = PC + disp + 4;
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2007-09-26 05:05:11 +02:00
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}});
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2010-11-11 11:03:58 +01:00
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// Branch Never
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2007-09-26 05:05:11 +02:00
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0x0: fbpn(22, {{;}},
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annul_code={{
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2010-12-08 09:27:43 +01:00
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NNPC = NPC + 8;
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NPC = NPC + 4;
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2007-09-26 05:05:11 +02:00
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}});
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2007-01-30 22:12:38 +01:00
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default: decode BPCC {
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2007-09-26 05:05:11 +02:00
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0x0: fbpfcc0(19, test=
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{{passesFpCondition(Fsr<11:10>, COND2)}});
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0x1: fbpfcc1(19, test=
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{{passesFpCondition(Fsr<33:32>, COND2)}});
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0x2: fbpfcc2(19, test=
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{{passesFpCondition(Fsr<35:34>, COND2)}});
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0x3: fbpfcc3(19, test=
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{{passesFpCondition(Fsr<37:36>, COND2)}});
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2007-01-30 22:12:38 +01:00
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}
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}
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}
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2010-11-11 11:03:58 +01:00
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// fbfcc
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2007-01-30 22:12:38 +01:00
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0x6: decode COND2 {
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format BranchN {
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2010-11-11 11:03:58 +01:00
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// Branch Always
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2007-09-26 05:05:11 +02:00
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0x8: fba(22, annul_code={{
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2010-12-08 09:27:43 +01:00
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NPC = PC + disp;
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NNPC = PC + disp + 4;
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2007-09-26 05:05:11 +02:00
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}});
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2010-11-11 11:03:58 +01:00
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// Branch Never
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2007-09-26 05:05:11 +02:00
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0x0: fbn(22, {{;}},
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annul_code={{
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2010-12-08 09:27:43 +01:00
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NNPC = NPC + 8;
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NPC = NPC + 4;
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2007-09-26 05:05:11 +02:00
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}});
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default: fbfcc(22, test=
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{{passesFpCondition(Fsr<11:10>, COND2)}});
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2007-01-30 22:12:38 +01:00
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}
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}
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2006-03-16 19:58:50 +01:00
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}
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2006-07-19 08:07:00 +02:00
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0x1: BranchN::call(30, {{
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2011-01-16 00:30:17 +01:00
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IntReg midVal;
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2012-02-11 23:16:38 +01:00
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R15 = midVal = (Pstate.am ? (PC)<31:0> : PC);
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2011-01-16 00:30:17 +01:00
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NNPC = midVal + disp;
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2011-06-09 07:34:06 +02:00
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}},None, None, IsIndirectControl, IsCall);
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2006-03-16 19:58:50 +01:00
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0x2: decode OP3 {
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2006-03-17 20:02:38 +01:00
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format IntOp {
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2011-09-27 08:48:54 +02:00
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0x00: add({{Rd = Rs1_sdw + Rs2_or_imm13;}});
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0x01: and({{Rd = Rs1_sdw & Rs2_or_imm13;}});
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0x02: or({{Rd = Rs1_sdw | Rs2_or_imm13;}});
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0x03: xor({{Rd = Rs1_sdw ^ Rs2_or_imm13;}});
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0x04: sub({{Rd = Rs1_sdw - Rs2_or_imm13;}});
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0x05: andn({{Rd = Rs1_sdw & ~Rs2_or_imm13;}});
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0x06: orn({{Rd = Rs1_sdw | ~Rs2_or_imm13;}});
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0x07: xnor({{Rd = ~(Rs1_sdw ^ Rs2_or_imm13);}});
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0x08: addc({{Rd = Rs1_sdw + Rs2_or_imm13 + Ccr<0:0>;}});
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0x09: mulx({{Rd = Rs1_sdw * Rs2_or_imm13;}});
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2006-03-16 19:58:50 +01:00
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0x0A: umul({{
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2011-09-27 08:48:54 +02:00
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Rd = Rs1_udw<31:0> * Rs2_or_imm13<31:0>;
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2006-05-27 00:40:00 +02:00
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Y = Rd<63:32>;
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2006-03-17 20:02:38 +01:00
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}});
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2006-03-16 19:58:50 +01:00
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0x0B: smul({{
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2011-09-27 08:48:54 +02:00
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Rd_sdw = sext<32>(Rs1_sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>);
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Y = Rd_sdw<63:32>;
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2006-03-17 20:02:38 +01:00
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}});
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2011-09-27 08:48:54 +02:00
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0x0C: subc({{Rd_sdw = Rs1_sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
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2006-03-16 19:58:50 +01:00
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0x0D: udivx({{
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2010-11-11 11:03:58 +01:00
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if (Rs2_or_imm13 == 0)
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2014-10-16 11:49:51 +02:00
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fault = std::make_shared<DivisionByZero>();
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2010-11-11 11:03:58 +01:00
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else
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2011-09-27 08:48:54 +02:00
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Rd_udw = Rs1_udw / Rs2_or_imm13;
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2006-03-17 20:02:38 +01:00
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}});
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2006-03-16 19:58:50 +01:00
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0x0E: udiv({{
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2010-11-11 11:03:58 +01:00
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if (Rs2_or_imm13 == 0) {
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2014-10-16 11:49:51 +02:00
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fault = std::make_shared<DivisionByZero>();
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2010-11-11 11:03:58 +01:00
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} else {
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2011-09-27 08:48:54 +02:00
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Rd_udw = ((Y << 32) | Rs1_udw<31:0>) / Rs2_or_imm13;
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if (Rd_udw >> 32 != 0)
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Rd_udw = 0xFFFFFFFF;
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2006-03-17 20:02:38 +01:00
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}
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}});
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2006-03-16 19:58:50 +01:00
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0x0F: sdiv({{
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2011-09-27 08:48:54 +02:00
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if (Rs2_or_imm13_sdw == 0) {
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2014-10-16 11:49:51 +02:00
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fault = std::make_shared<DivisionByZero>();
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2010-11-11 11:03:58 +01:00
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} else {
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2011-09-27 08:48:54 +02:00
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Rd_udw = ((int64_t)((Y << 32) |
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Rs1_sdw<31:0>)) / Rs2_or_imm13_sdw;
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if ((int64_t)Rd_udw >=
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2010-11-11 11:03:58 +01:00
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std::numeric_limits<int32_t>::max()) {
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2011-09-27 08:48:54 +02:00
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Rd_udw = 0x7FFFFFFF;
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} else if ((int64_t)Rd_udw <=
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2010-11-11 11:03:58 +01:00
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std::numeric_limits<int32_t>::min()) {
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2011-09-27 08:48:54 +02:00
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Rd_udw = ULL(0xFFFFFFFF80000000);
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2010-11-11 11:03:58 +01:00
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}
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2006-03-17 20:02:38 +01:00
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}
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2006-04-06 20:52:44 +02:00
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}});
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2006-01-29 23:25:54 +01:00
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}
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2006-03-17 20:02:38 +01:00
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format IntOpCc {
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2006-03-16 19:58:50 +01:00
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0x10: addcc({{
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2007-09-26 05:08:34 +02:00
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int64_t res, op1 = Rs1, op2 = Rs2_or_imm13;
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Rd = res = op1 + op2;
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}});
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2006-03-17 20:02:38 +01:00
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0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
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0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
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0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
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2006-03-16 19:58:50 +01:00
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0x14: subcc({{
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2007-09-26 05:08:34 +02:00
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int64_t res, op1 = Rs1, op2 = Rs2_or_imm13;
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Rd = res = op1 - op2;
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}}, sub=True);
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2006-03-17 20:02:38 +01:00
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0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
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0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
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0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
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2006-03-16 19:58:50 +01:00
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0x18: addccc({{
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2007-09-26 05:08:34 +02:00
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int64_t res, op1 = Rs1, op2 = Rs2_or_imm13;
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Rd = res = op1 + op2 + Ccr<0:>;
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}});
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2006-12-06 11:43:25 +01:00
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0x1A: IntOpCcRes::umulcc({{
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2006-05-15 05:57:21 +02:00
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uint64_t resTemp;
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2011-09-27 08:48:54 +02:00
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Rd = resTemp = Rs1_udw<31:0> * Rs2_or_imm13_udw<31:0>;
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2006-12-06 11:43:25 +01:00
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Y = resTemp<63:32>;}});
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0x1B: IntOpCcRes::smulcc({{
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2006-05-15 05:57:21 +02:00
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int64_t resTemp;
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2011-09-27 08:48:54 +02:00
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Rd = resTemp = sext<32>(Rs1_sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>);
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2006-12-06 11:43:25 +01:00
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Y = resTemp<63:32>;}});
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2006-03-16 19:58:50 +01:00
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0x1C: subccc({{
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2007-09-26 05:08:34 +02:00
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int64_t res, op1 = Rs1, op2 = Rs2_or_imm13;
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Rd = res = op1 - op2 - Ccr<0:>;
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}}, sub=True);
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2006-12-06 11:43:25 +01:00
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0x1D: IntOpCcRes::udivxcc({{
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2011-09-27 08:48:54 +02:00
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if (Rs2_or_imm13_udw == 0)
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2014-10-16 11:49:51 +02:00
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fault = std::make_shared<DivisionByZero>();
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2010-11-11 11:03:58 +01:00
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else
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2011-09-27 08:48:54 +02:00
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Rd = Rs1_udw / Rs2_or_imm13_udw;}});
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2007-09-26 05:08:34 +02:00
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0x1E: IntOpCcRes::udivcc({{
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2009-09-15 14:48:20 +02:00
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uint64_t resTemp;
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2011-09-27 08:48:54 +02:00
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uint32_t val2 = Rs2_or_imm13_udw;
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2007-09-26 05:08:34 +02:00
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int32_t overflow = 0;
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2010-11-11 11:03:58 +01:00
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if (val2 == 0) {
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2014-10-16 11:49:51 +02:00
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fault = std::make_shared<DivisionByZero>();
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2010-11-11 11:03:58 +01:00
|
|
|
} else {
|
2011-09-27 08:48:54 +02:00
|
|
|
resTemp = (uint64_t)((Y << 32) | Rs1_udw<31:0>) / val2;
|
2007-09-26 05:08:34 +02:00
|
|
|
overflow = (resTemp<63:32> != 0);
|
2010-11-11 11:03:58 +01:00
|
|
|
if (overflow)
|
|
|
|
Rd = resTemp = 0xFFFFFFFF;
|
|
|
|
else
|
|
|
|
Rd = resTemp;
|
2007-09-26 05:08:34 +02:00
|
|
|
}
|
|
|
|
}}, iv={{overflow}});
|
|
|
|
0x1F: IntOpCcRes::sdivcc({{
|
2011-09-27 08:48:54 +02:00
|
|
|
int64_t val2 = Rs2_or_imm13_sdw<31:0>;
|
2007-09-26 05:08:34 +02:00
|
|
|
bool overflow = false, underflow = false;
|
2010-11-11 11:03:58 +01:00
|
|
|
if (val2 == 0) {
|
2014-10-16 11:49:51 +02:00
|
|
|
fault = std::make_shared<DivisionByZero>();
|
2010-11-11 11:03:58 +01:00
|
|
|
} else {
|
2011-09-27 08:48:54 +02:00
|
|
|
Rd = (int64_t)((Y << 32) | Rs1_sdw<31:0>) / val2;
|
2007-09-26 05:08:34 +02:00
|
|
|
overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max());
|
|
|
|
underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min());
|
2010-11-11 11:03:58 +01:00
|
|
|
if (overflow)
|
|
|
|
Rd = 0x7FFFFFFF;
|
|
|
|
else if (underflow)
|
|
|
|
Rd = ULL(0xFFFFFFFF80000000);
|
2007-09-26 05:08:34 +02:00
|
|
|
}
|
|
|
|
}}, iv={{overflow || underflow}});
|
2006-03-16 19:58:50 +01:00
|
|
|
0x20: taddcc({{
|
2007-09-26 05:08:34 +02:00
|
|
|
int64_t res, op1 = Rs1, op2 = Rs2_or_imm13;
|
|
|
|
Rd = res = Rs1 + op2;
|
|
|
|
}}, iv={{
|
|
|
|
(op1 & mask(2)) || (op2 & mask(2)) ||
|
|
|
|
findOverflow(32, res, op1, op2)
|
|
|
|
}});
|
2006-03-16 19:58:50 +01:00
|
|
|
0x21: tsubcc({{
|
2007-09-26 05:08:34 +02:00
|
|
|
int64_t res, op1 = Rs1, op2 = Rs2_or_imm13;
|
|
|
|
Rd = res = Rs1 - op2;
|
|
|
|
}}, iv={{
|
|
|
|
(op1 & mask(2)) || (op2 & mask(2)) ||
|
|
|
|
findOverflow(32, res, op1, ~op2)
|
|
|
|
}}, sub=True);
|
2006-03-16 19:58:50 +01:00
|
|
|
0x22: taddcctv({{
|
2007-09-26 05:08:34 +02:00
|
|
|
int64_t res, op1 = Rs1, op2 = Rs2_or_imm13;
|
|
|
|
Rd = res = op1 + op2;
|
|
|
|
bool overflow = (op1 & mask(2)) || (op2 & mask(2)) ||
|
|
|
|
findOverflow(32, res, op1, op2);
|
2010-11-11 11:03:58 +01:00
|
|
|
if (overflow)
|
2014-10-16 11:49:51 +02:00
|
|
|
fault = std::make_shared<TagOverflow>();
|
2007-09-26 05:08:34 +02:00
|
|
|
}}, iv={{overflow}});
|
2006-03-16 19:58:50 +01:00
|
|
|
0x23: tsubcctv({{
|
2007-09-26 05:08:34 +02:00
|
|
|
int64_t res, op1 = Rs1, op2 = Rs2_or_imm13;
|
|
|
|
Rd = res = op1 - op2;
|
|
|
|
bool overflow = (op1 & mask(2)) || (op2 & mask(2)) ||
|
|
|
|
findOverflow(32, res, op1, ~op2);
|
2010-11-11 11:03:58 +01:00
|
|
|
if (overflow)
|
2014-10-16 11:49:51 +02:00
|
|
|
fault = std::make_shared<TagOverflow>();
|
2007-09-26 05:08:34 +02:00
|
|
|
}}, iv={{overflow}}, sub=True);
|
2006-03-16 19:58:50 +01:00
|
|
|
0x24: mulscc({{
|
2007-09-26 05:08:34 +02:00
|
|
|
int32_t savedLSB = Rs1<0:>;
|
2007-03-12 22:07:10 +01:00
|
|
|
|
2010-11-11 11:03:58 +01:00
|
|
|
// Step 1
|
2007-09-26 05:08:34 +02:00
|
|
|
int64_t multiplicand = Rs2_or_imm13;
|
2010-11-11 11:03:58 +01:00
|
|
|
// Step 2
|
2007-09-26 05:08:34 +02:00
|
|
|
int32_t partialP = Rs1<31:1> |
|
|
|
|
((Ccr<3:3> ^ Ccr<1:1>) << 31);
|
2010-11-11 11:03:58 +01:00
|
|
|
// Step 3
|
2007-09-26 05:08:34 +02:00
|
|
|
int32_t added = Y<0:> ? multiplicand : 0;
|
|
|
|
int64_t res, op1 = partialP, op2 = added;
|
|
|
|
Rd = res = partialP + added;
|
2010-11-11 11:03:58 +01:00
|
|
|
// Steps 4 & 5
|
2007-09-26 05:08:34 +02:00
|
|
|
Y = Y<31:1> | (savedLSB << 31);
|
|
|
|
}});
|
2006-04-06 20:52:44 +02:00
|
|
|
}
|
|
|
|
format IntOp
|
|
|
|
{
|
|
|
|
0x25: decode X {
|
|
|
|
0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
|
|
|
|
0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
|
2006-03-07 10:33:10 +01:00
|
|
|
}
|
2006-04-06 20:52:44 +02:00
|
|
|
0x26: decode X {
|
2011-09-27 08:48:54 +02:00
|
|
|
0x0: srl({{Rd = Rs1_uw >> (I ? SHCNT32 : Rs2<4:0>);}});
|
|
|
|
0x1: srlx({{Rd = Rs1_udw >> (I ? SHCNT64 : Rs2<5:0>);}});
|
2006-04-06 20:52:44 +02:00
|
|
|
}
|
|
|
|
0x27: decode X {
|
2011-09-27 08:48:54 +02:00
|
|
|
0x0: sra({{Rd = Rs1_sw >> (I ? SHCNT32 : Rs2<4:0>);}});
|
|
|
|
0x1: srax({{Rd = Rs1_sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
|
2006-04-06 20:52:44 +02:00
|
|
|
}
|
2006-07-22 21:50:40 +02:00
|
|
|
0x28: decode RS1 {
|
2007-01-25 19:43:46 +01:00
|
|
|
0x00: NoPriv::rdy({{Rd = Y<31:0>;}});
|
2010-11-11 11:03:58 +01:00
|
|
|
// 1 should cause an illegal instruction exception
|
2006-11-10 10:02:39 +01:00
|
|
|
0x02: NoPriv::rdccr({{Rd = Ccr;}});
|
|
|
|
0x03: NoPriv::rdasi({{Rd = Asi;}});
|
2007-09-26 05:09:25 +02:00
|
|
|
0x04: Priv::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
|
2006-11-10 10:02:39 +01:00
|
|
|
0x05: NoPriv::rdpc({{
|
2012-02-11 23:16:38 +01:00
|
|
|
if (Pstate.am)
|
2010-12-08 09:27:43 +01:00
|
|
|
Rd = (PC)<31:0>;
|
2006-11-10 10:02:39 +01:00
|
|
|
else
|
2010-12-08 09:27:43 +01:00
|
|
|
Rd = PC;
|
ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
This change is a low level and pervasive reorganization of how PCs are managed
in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about,
the PC and the NPC, and the lsb of the PC signaled whether or not you were in
PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next
micropc, x86 and ARM introduced variable length instruction sets, and ARM
started to keep track of mode bits in the PC. Each CPU model handled PCs in
its own custom way that needed to be updated individually to handle the new
dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack,
the complexity could be hidden in the ISA at the ISA implementation's expense.
Areas like the branch predictor hadn't been updated to handle branch delay
slots or micropcs, and it turns out that had introduced a significant (10s of
percent) performance bug in SPARC and to a lesser extend MIPS. Rather than
perpetuate the problem by reworking O3 again to handle the PC features needed
by x86, this change was introduced to rework PC handling in a more modular,
transparent, and hopefully efficient way.
PC type:
Rather than having the superset of all possible elements of PC state declared
in each of the CPU models, each ISA defines its own PCState type which has
exactly the elements it needs. A cross product of canned PCState classes are
defined in the new "generic" ISA directory for ISAs with/without delay slots
and microcode. These are either typedef-ed or subclassed by each ISA. To read
or write this structure through a *Context, you use the new pcState() accessor
which reads or writes depending on whether it has an argument. If you just
want the address of the current or next instruction or the current micro PC,
you can get those through read-only accessors on either the PCState type or
the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the
move away from readPC. That name is ambiguous since it's not clear whether or
not it should be the actual address to fetch from, or if it should have extra
bits in it like the PAL mode bit. Each class is free to define its own
functions to get at whatever values it needs however it needs to to be used in
ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the
PC and into a separate field like ARM.
These types can be reset to a particular pc (where npc = pc +
sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as
appropriate), printed, serialized, and compared. There is a branching()
function which encapsulates code in the CPU models that checked if an
instruction branched or not. Exactly what that means in the context of branch
delay slots which can skip an instruction when not taken is ambiguous, and
ideally this function and its uses can be eliminated. PCStates also generally
know how to advance themselves in various ways depending on if they point at
an instruction, a microop, or the last microop of a macroop. More on that
later.
Ideally, accessing all the PCs at once when setting them will improve
performance of M5 even though more data needs to be moved around. This is
because often all the PCs need to be manipulated together, and by getting them
all at once you avoid multiple function calls. Also, the PCs of a particular
thread will have spatial locality in the cache. Previously they were grouped
by element in arrays which spread out accesses.
Advancing the PC:
The PCs were previously managed entirely by the CPU which had to know about PC
semantics, try to figure out which dimension to increment the PC in, what to
set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction
with the PC type itself. Because most of the information about how to
increment the PC (mainly what type of instruction it refers to) is contained
in the instruction object, a new advancePC virtual function was added to the
StaticInst class. Subclasses provide an implementation that moves around the
right element of the PC with a minimal amount of decision making. In ISAs like
Alpha, the instructions always simply assign NPC to PC without having to worry
about micropcs, nnpcs, etc. The added cost of a virtual function call should
be outweighed by not having to figure out as much about what to do with the
PCs and mucking around with the extra elements.
One drawback of making the StaticInsts advance the PC is that you have to
actually have one to advance the PC. This would, superficially, seem to
require decoding an instruction before fetch could advance. This is, as far as
I can tell, realistic. fetch would advance through memory addresses, not PCs,
perhaps predicting new memory addresses using existing ones. More
sophisticated decisions about control flow would be made later on, after the
instruction was decoded, and handed back to fetch. If branching needs to
happen, some amount of decoding needs to happen to see that it's a branch,
what the target is, etc. This could get a little more complicated if that gets
done by the predecoder, but I'm choosing to ignore that for now.
Variable length instructions:
To handle variable length instructions in x86 and ARM, the predecoder now
takes in the current PC by reference to the getExtMachInst function. It can
modify the PC however it needs to (by setting NPC to be the PC + instruction
length, for instance). This could be improved since the CPU doesn't know if
the PC was modified and always has to write it back.
ISA parser:
To support the new API, all PC related operand types were removed from the
parser and replaced with a PCState type. There are two warts on this
implementation. First, as with all the other operand types, the PCState still
has to have a valid operand type even though it doesn't use it. Second, using
syntax like PCS.npc(target) doesn't work for two reasons, this looks like the
syntax for operand type overriding, and the parser can't figure out if you're
reading or writing. Instructions that use the PCS operand (which I've
consistently called it) need to first read it into a local variable,
manipulate it, and then write it back out.
Return address stack:
The return address stack needed a little extra help because, in the presence
of branch delay slots, it has to merge together elements of the return PC and
the call PC. To handle that, a buildRetPC utility function was added. There
are basically only two versions in all the ISAs, but it didn't seem short
enough to put into the generic ISA directory. Also, the branch predictor code
in O3 and InOrder were adjusted so that they always store the PC of the actual
call instruction in the RAS, not the next PC. If the call instruction is a
microop, the next PC refers to the next microop in the same macroop which is
probably not desirable. The buildRetPC function advances the PC intelligently
to the next macroop (in an ISA specific way) so that that case works.
Change in stats:
There were no change in stats except in MIPS and SPARC in the O3 model. MIPS
runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could
likely be improved further by setting call/return instruction flags and taking
advantage of the RAS.
TODO:
Add != operators to the PCState classes, defined trivially to be !(a==b).
Smooth out places where PCs are split apart, passed around, and put back
together later. I think this might happen in SPARC's fault code. Add ISA
specific constructors that allow setting PC elements without calling a bunch
of accessors. Try to eliminate the need for the branching() function. Factor
out Alpha's PAL mode pc bit into a separate flag field, and eliminate places
where it's blindly masked out or tested in the PC.
2010-10-31 08:07:20 +01:00
|
|
|
}});
|
2006-11-10 10:02:39 +01:00
|
|
|
0x06: NoPriv::rdfprs({{
|
2010-11-11 11:03:58 +01:00
|
|
|
// Wait for all fpops to finish.
|
2006-11-10 10:02:39 +01:00
|
|
|
Rd = Fprs;
|
|
|
|
}});
|
2010-11-11 11:03:58 +01:00
|
|
|
// 7-14 should cause an illegal instruction exception
|
2006-11-10 10:02:39 +01:00
|
|
|
0x0F: decode I {
|
2007-02-12 19:06:30 +01:00
|
|
|
0x0: Nop::stbar({{/*stuff*/}}, IsWriteBarrier, MemWriteOp);
|
|
|
|
0x1: Nop::membar({{/*stuff*/}}, IsMemBarrier, MemReadOp);
|
2006-07-22 21:50:40 +02:00
|
|
|
}
|
2006-11-10 10:02:39 +01:00
|
|
|
0x10: Priv::rdpcr({{Rd = Pcr;}});
|
2007-09-26 05:09:25 +02:00
|
|
|
0x11: Priv::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
|
2010-11-11 11:03:58 +01:00
|
|
|
// 0x12 should cause an illegal instruction exception
|
2006-11-10 10:02:39 +01:00
|
|
|
0x13: NoPriv::rdgsr({{
|
2007-02-03 01:02:27 +01:00
|
|
|
fault = checkFpEnableFault(xc);
|
|
|
|
if (fault)
|
|
|
|
return fault;
|
|
|
|
Rd = Gsr;
|
2006-07-22 21:50:40 +02:00
|
|
|
}});
|
2010-11-11 11:03:58 +01:00
|
|
|
// 0x14-0x15 should cause an illegal instruction exception
|
2006-11-10 10:02:39 +01:00
|
|
|
0x16: Priv::rdsoftint({{Rd = Softint;}});
|
2006-12-06 20:29:10 +01:00
|
|
|
0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}});
|
2007-09-26 05:09:25 +02:00
|
|
|
0x18: Priv::rdstick({{Rd = Stick}}, {{Stick<63:>}});
|
2006-12-06 20:29:10 +01:00
|
|
|
0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}});
|
2006-11-10 21:27:06 +01:00
|
|
|
0x1A: Priv::rdstrand_sts_reg({{
|
2012-02-11 23:16:38 +01:00
|
|
|
if (Pstate.am && !Hpstate.hpriv)
|
2006-11-10 21:27:06 +01:00
|
|
|
Rd = StrandStsReg<0:>;
|
|
|
|
else
|
|
|
|
Rd = StrandStsReg;
|
|
|
|
}});
|
2010-11-11 11:03:58 +01:00
|
|
|
// 0x1A is supposed to be reserved, but it reads the strand
|
|
|
|
// status register.
|
|
|
|
// 0x1B-0x1F should cause an illegal instruction exception
|
2006-11-10 10:02:39 +01:00
|
|
|
}
|
|
|
|
0x29: decode RS1 {
|
|
|
|
0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}});
|
2007-09-26 05:09:25 +02:00
|
|
|
0x01: HPriv::rdhprhtstate({{Rd = Htstate;}}, checkTl=true);
|
2010-11-11 11:03:58 +01:00
|
|
|
// 0x02 should cause an illegal instruction exception
|
2006-11-10 10:02:39 +01:00
|
|
|
0x03: HPriv::rdhprhintp({{Rd = Hintp;}});
|
2010-11-11 11:03:58 +01:00
|
|
|
// 0x04 should cause an illegal instruction exception
|
2006-11-10 10:02:39 +01:00
|
|
|
0x05: HPriv::rdhprhtba({{Rd = Htba;}});
|
|
|
|
0x06: HPriv::rdhprhver({{Rd = Hver;}});
|
2010-11-11 11:03:58 +01:00
|
|
|
// 0x07-0x1E should cause an illegal instruction exception
|
2006-12-06 20:29:10 +01:00
|
|
|
0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}});
|
2006-11-10 10:02:39 +01:00
|
|
|
}
|
|
|
|
0x2A: decode RS1 {
|
2007-09-26 05:09:25 +02:00
|
|
|
0x00: Priv::rdprtpc({{Rd = Tpc;}}, checkTl=true);
|
|
|
|
0x01: Priv::rdprtnpc({{Rd = Tnpc;}}, checkTl=true);
|
|
|
|
0x02: Priv::rdprtstate({{Rd = Tstate;}}, checkTl=true);
|
|
|
|
0x03: Priv::rdprtt({{Rd = Tt;}}, checkTl=true);
|
2006-12-06 20:29:10 +01:00
|
|
|
0x04: Priv::rdprtick({{Rd = Tick;}});
|
2006-11-10 10:02:39 +01:00
|
|
|
0x05: Priv::rdprtba({{Rd = Tba;}});
|
|
|
|
0x06: Priv::rdprpstate({{Rd = Pstate;}});
|
|
|
|
0x07: Priv::rdprtl({{Rd = Tl;}});
|
|
|
|
0x08: Priv::rdprpil({{Rd = Pil;}});
|
|
|
|
0x09: Priv::rdprcwp({{Rd = Cwp;}});
|
|
|
|
0x0A: Priv::rdprcansave({{Rd = Cansave;}});
|
|
|
|
0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}});
|
|
|
|
0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}});
|
|
|
|
0x0D: Priv::rdprotherwin({{Rd = Otherwin;}});
|
|
|
|
0x0E: Priv::rdprwstate({{Rd = Wstate;}});
|
2010-11-11 11:03:58 +01:00
|
|
|
// 0x0F should cause an illegal instruction exception
|
2006-11-10 10:02:39 +01:00
|
|
|
0x10: Priv::rdprgl({{Rd = Gl;}});
|
2010-11-11 11:03:58 +01:00
|
|
|
// 0x11-0x1F should cause an illegal instruction exception
|
2006-07-22 21:50:40 +02:00
|
|
|
}
|
2006-04-06 20:52:44 +02:00
|
|
|
0x2B: BasicOperate::flushw({{
|
2010-11-11 11:03:58 +01:00
|
|
|
if (NWindows - 2 - Cansave != 0) {
|
|
|
|
if (Otherwin)
|
2014-10-16 11:49:51 +02:00
|
|
|
fault = std::make_shared<SpillNOther>(4*Wstate<5:3>);
|
2006-04-06 20:52:44 +02:00
|
|
|
else
|
2014-10-16 11:49:51 +02:00
|
|
|
fault = std::make_shared<SpillNNormal>(4*Wstate<2:0>);
|
2006-03-16 19:58:50 +01:00
|
|
|
}
|
2006-04-06 20:52:44 +02:00
|
|
|
}});
|
|
|
|
0x2C: decode MOVCC3
|
|
|
|
{
|
2010-05-14 23:22:51 +02:00
|
|
|
0x0: decode CC
|
|
|
|
{
|
|
|
|
0x0: movccfcc0({{
|
2010-11-11 11:03:58 +01:00
|
|
|
if (passesCondition(Fsr<11:10>, COND4))
|
2010-05-14 23:22:51 +02:00
|
|
|
Rd = Rs2_or_imm11;
|
|
|
|
else
|
|
|
|
Rd = Rd;
|
|
|
|
}});
|
|
|
|
0x1: movccfcc1({{
|
2010-11-11 11:03:58 +01:00
|
|
|
if (passesCondition(Fsr<33:32>, COND4))
|
2010-05-14 23:22:51 +02:00
|
|
|
Rd = Rs2_or_imm11;
|
|
|
|
else
|
|
|
|
Rd = Rd;
|
|
|
|
}});
|
|
|
|
0x2: movccfcc2({{
|
2010-11-11 11:03:58 +01:00
|
|
|
if (passesCondition(Fsr<35:34>, COND4))
|
2010-05-14 23:22:51 +02:00
|
|
|
Rd = Rs2_or_imm11;
|
|
|
|
else
|
|
|
|
Rd = Rd;
|
|
|
|
}});
|
|
|
|
0x3: movccfcc3({{
|
2010-11-11 11:03:58 +01:00
|
|
|
if (passesCondition(Fsr<37:36>, COND4))
|
2010-05-14 23:22:51 +02:00
|
|
|
Rd = Rs2_or_imm11;
|
|
|
|
else
|
|
|
|
Rd = Rd;
|
|
|
|
}});
|
|
|
|
}
|
2006-04-06 20:52:44 +02:00
|
|
|
0x1: decode CC
|
|
|
|
{
|
|
|
|
0x0: movcci({{
|
2010-11-11 11:03:58 +01:00
|
|
|
if (passesCondition(Ccr<3:0>, COND4))
|
2006-04-30 07:46:00 +02:00
|
|
|
Rd = Rs2_or_imm11;
|
|
|
|
else
|
|
|
|
Rd = Rd;
|
2006-04-06 20:52:44 +02:00
|
|
|
}});
|
|
|
|
0x2: movccx({{
|
2010-11-11 11:03:58 +01:00
|
|
|
if (passesCondition(Ccr<7:4>, COND4))
|
2006-04-30 07:46:00 +02:00
|
|
|
Rd = Rs2_or_imm11;
|
|
|
|
else
|
|
|
|
Rd = Rd;
|
2006-04-06 20:52:44 +02:00
|
|
|
}});
|
2006-03-16 19:58:50 +01:00
|
|
|
}
|
2006-04-06 20:52:44 +02:00
|
|
|
}
|
|
|
|
0x2D: sdivx({{
|
2011-09-27 08:48:54 +02:00
|
|
|
if (Rs2_or_imm13_sdw == 0)
|
2014-10-16 11:49:51 +02:00
|
|
|
fault = std::make_shared<DivisionByZero>();
|
2010-11-11 11:03:58 +01:00
|
|
|
else
|
2011-09-27 08:48:54 +02:00
|
|
|
Rd_sdw = Rs1_sdw / Rs2_or_imm13_sdw;
|
2006-04-06 20:52:44 +02:00
|
|
|
}});
|
2014-10-16 11:49:51 +02:00
|
|
|
0x2E: Trap::popc({{fault = std::make_shared<IllegalInstruction>();}});
|
2006-04-06 20:52:44 +02:00
|
|
|
0x2F: decode RCOND3
|
|
|
|
{
|
2011-09-27 08:48:54 +02:00
|
|
|
0x1: movreq({{Rd = (Rs1_sdw == 0) ? Rs2_or_imm10 : Rd;}});
|
|
|
|
0x2: movrle({{Rd = (Rs1_sdw <= 0) ? Rs2_or_imm10 : Rd;}});
|
|
|
|
0x3: movrl({{Rd = (Rs1_sdw < 0) ? Rs2_or_imm10 : Rd;}});
|
|
|
|
0x5: movrne({{Rd = (Rs1_sdw != 0) ? Rs2_or_imm10 : Rd;}});
|
|
|
|
0x6: movrg({{Rd = (Rs1_sdw > 0) ? Rs2_or_imm10 : Rd;}});
|
|
|
|
0x7: movrge({{Rd = (Rs1_sdw >= 0) ? Rs2_or_imm10 : Rd;}});
|
2006-04-06 20:52:44 +02:00
|
|
|
}
|
2006-11-10 10:02:39 +01:00
|
|
|
0x30: decode RD {
|
2007-01-25 19:43:46 +01:00
|
|
|
0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}});
|
2010-11-11 11:03:58 +01:00
|
|
|
// 0x01 should cause an illegal instruction exception
|
2006-11-10 10:02:39 +01:00
|
|
|
0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
|
2010-12-08 01:19:57 +01:00
|
|
|
0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}, false,
|
|
|
|
IsSquashAfter);
|
2010-11-11 11:03:58 +01:00
|
|
|
// 0x04-0x05 should cause an illegal instruction exception
|
2006-11-10 10:02:39 +01:00
|
|
|
0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}});
|
2010-11-11 11:03:58 +01:00
|
|
|
// 0x07-0x0E should cause an illegal instruction exception
|
2014-10-16 11:49:51 +02:00
|
|
|
0x0F: Trap::softreset({{fault = std::make_shared<SoftwareInitiatedReset>();}});
|
2006-11-10 10:02:39 +01:00
|
|
|
0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}});
|
2007-09-26 05:09:25 +02:00
|
|
|
0x11: Priv::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}});
|
2010-11-11 11:03:58 +01:00
|
|
|
// 0x12 should cause an illegal instruction exception
|
2006-11-10 10:02:39 +01:00
|
|
|
0x13: NoPriv::wrgsr({{
|
2012-02-11 23:16:38 +01:00
|
|
|
if (Fprs<2:> == 0 || Pstate.pef == 0)
|
2014-10-16 11:49:51 +02:00
|
|
|
return std::make_shared<FpDisabled>();
|
2006-11-10 10:02:39 +01:00
|
|
|
Gsr = Rs1 ^ Rs2_or_imm13;
|
|
|
|
}});
|
|
|
|
0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}});
|
|
|
|
0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}});
|
|
|
|
0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}});
|
2006-12-06 20:29:10 +01:00
|
|
|
0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}});
|
2006-11-10 10:02:39 +01:00
|
|
|
0x18: NoPriv::wrstick({{
|
2012-02-11 23:16:38 +01:00
|
|
|
if (!Hpstate.hpriv)
|
2014-10-16 11:49:51 +02:00
|
|
|
return std::make_shared<IllegalInstruction>();
|
2006-12-06 20:29:10 +01:00
|
|
|
Stick = Rs1 ^ Rs2_or_imm13;
|
2006-11-10 10:02:39 +01:00
|
|
|
}});
|
2006-12-06 20:29:10 +01:00
|
|
|
0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}});
|
2006-11-10 21:27:06 +01:00
|
|
|
0x1A: Priv::wrstrand_sts_reg({{
|
|
|
|
StrandStsReg = Rs1 ^ Rs2_or_imm13;
|
|
|
|
}});
|
2010-11-11 11:03:58 +01:00
|
|
|
// 0x1A is supposed to be reserved, but it writes the strand
|
|
|
|
// status register.
|
|
|
|
// 0x1B-0x1F should cause an illegal instruction exception
|
2006-11-10 10:02:39 +01:00
|
|
|
}
|
2006-04-06 20:52:44 +02:00
|
|
|
0x31: decode FCN {
|
2006-10-25 23:54:14 +02:00
|
|
|
0x0: Priv::saved({{
|
|
|
|
assert(Cansave < NWindows - 2);
|
|
|
|
assert(Otherwin || Canrestore);
|
|
|
|
Cansave = Cansave + 1;
|
2010-11-11 11:03:58 +01:00
|
|
|
if (Otherwin == 0)
|
2006-10-25 23:54:14 +02:00
|
|
|
Canrestore = Canrestore - 1;
|
|
|
|
else
|
|
|
|
Otherwin = Otherwin - 1;
|
|
|
|
}});
|
2006-11-10 21:27:06 +01:00
|
|
|
0x1: Priv::restored({{
|
2006-10-25 23:54:14 +02:00
|
|
|
assert(Cansave || Otherwin);
|
|
|
|
assert(Canrestore < NWindows - 2);
|
|
|
|
Canrestore = Canrestore + 1;
|
2010-11-11 11:03:58 +01:00
|
|
|
if (Otherwin == 0)
|
2006-10-25 23:54:14 +02:00
|
|
|
Cansave = Cansave - 1;
|
|
|
|
else
|
|
|
|
Otherwin = Otherwin - 1;
|
2007-01-23 21:50:03 +01:00
|
|
|
|
2010-11-11 11:03:58 +01:00
|
|
|
if (Cleanwin < NWindows - 1)
|
2007-01-23 21:50:03 +01:00
|
|
|
Cleanwin = Cleanwin + 1;
|
2006-10-25 23:54:14 +02:00
|
|
|
}});
|
2006-04-06 20:52:44 +02:00
|
|
|
}
|
2006-11-10 10:02:39 +01:00
|
|
|
0x32: decode RD {
|
2007-09-26 05:09:25 +02:00
|
|
|
0x00: Priv::wrprtpc(
|
|
|
|
{{Tpc = Rs1 ^ Rs2_or_imm13;}}, checkTl=true);
|
|
|
|
0x01: Priv::wrprtnpc(
|
|
|
|
{{Tnpc = Rs1 ^ Rs2_or_imm13;}}, checkTl=true);
|
|
|
|
0x02: Priv::wrprtstate(
|
|
|
|
{{Tstate = Rs1 ^ Rs2_or_imm13;}}, checkTl=true);
|
|
|
|
0x03: Priv::wrprtt(
|
|
|
|
{{Tt = Rs1 ^ Rs2_or_imm13;}}, checkTl=true);
|
2006-12-06 20:29:10 +01:00
|
|
|
0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
|
2006-11-10 10:02:39 +01:00
|
|
|
0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
|
|
|
|
0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
|
|
|
|
0x07: Priv::wrprtl({{
|
2012-02-11 23:16:38 +01:00
|
|
|
if (Pstate.priv && !Hpstate.hpriv)
|
2006-11-10 10:02:39 +01:00
|
|
|
Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL);
|
|
|
|
else
|
|
|
|
Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL);
|
|
|
|
}});
|
|
|
|
0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
|
|
|
|
0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
|
|
|
|
0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
|
|
|
|
0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
|
|
|
|
0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
|
|
|
|
0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
|
|
|
|
0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
|
2010-11-11 11:03:58 +01:00
|
|
|
// 0x0F should cause an illegal instruction exception
|
2006-11-10 10:02:39 +01:00
|
|
|
0x10: Priv::wrprgl({{
|
2012-02-11 23:16:38 +01:00
|
|
|
if (Pstate.priv && !Hpstate.hpriv)
|
2006-11-10 10:02:39 +01:00
|
|
|
Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL);
|
|
|
|
else
|
|
|
|
Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL);
|
|
|
|
}});
|
2010-11-11 11:03:58 +01:00
|
|
|
// 0x11-0x1F should cause an illegal instruction exception
|
2006-11-10 10:02:39 +01:00
|
|
|
}
|
|
|
|
0x33: decode RD {
|
|
|
|
0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}});
|
2007-09-26 05:09:25 +02:00
|
|
|
0x01: HPriv::wrhprhtstate(
|
|
|
|
{{Htstate = Rs1 ^ Rs2_or_imm13;}}, checkTl=true);
|
2010-11-11 11:03:58 +01:00
|
|
|
// 0x02 should cause an illegal instruction exception
|
2006-11-10 10:02:39 +01:00
|
|
|
0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}});
|
2010-11-11 11:03:58 +01:00
|
|
|
// 0x04 should cause an illegal instruction exception
|
2006-11-10 10:02:39 +01:00
|
|
|
0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}});
|
2010-11-11 11:03:58 +01:00
|
|
|
// 0x06-0x01D should cause an illegal instruction exception
|
2006-12-06 20:29:10 +01:00
|
|
|
0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}});
|
2006-11-10 10:02:39 +01:00
|
|
|
}
|
2006-07-22 21:50:40 +02:00
|
|
|
0x34: decode OPF{
|
2007-02-03 00:04:42 +01:00
|
|
|
format FpBasic{
|
2011-09-27 08:48:54 +02:00
|
|
|
0x01: fmovs({{Frds_uw = Frs2s_uw;}});
|
|
|
|
0x02: fmovd({{Frd_udw = Frs2_udw;}});
|
2007-01-30 06:08:42 +01:00
|
|
|
0x03: FpUnimpl::fmovq();
|
2011-09-27 08:48:54 +02:00
|
|
|
0x05: fnegs({{Frds_uw = Frs2s_uw ^ (1UL << 31);}});
|
|
|
|
0x06: fnegd({{Frd_udw = Frs2_udw ^ (1ULL << 63);}});
|
2007-01-30 06:08:42 +01:00
|
|
|
0x07: FpUnimpl::fnegq();
|
2011-09-27 08:48:54 +02:00
|
|
|
0x09: fabss({{Frds_uw = ((1UL << 31) - 1) & Frs2s_uw;}});
|
|
|
|
0x0A: fabsd({{Frd_udw = ((1ULL << 63) - 1) & Frs2_udw;}});
|
2007-01-30 06:08:42 +01:00
|
|
|
0x0B: FpUnimpl::fabsq();
|
2011-09-27 08:48:54 +02:00
|
|
|
0x29: fsqrts({{Frds_sf = std::sqrt(Frs2s_sf);}});
|
|
|
|
0x2A: fsqrtd({{Frd_df = std::sqrt(Frs2_df);}});
|
2007-01-30 06:08:42 +01:00
|
|
|
0x2B: FpUnimpl::fsqrtq();
|
2011-09-27 08:48:54 +02:00
|
|
|
0x41: fadds({{Frds_sf = Frs1s_sf + Frs2s_sf;}});
|
|
|
|
0x42: faddd({{Frd_df = Frs1_df + Frs2_df;}});
|
2007-01-30 06:08:42 +01:00
|
|
|
0x43: FpUnimpl::faddq();
|
2011-09-27 08:48:54 +02:00
|
|
|
0x45: fsubs({{Frds_sf = Frs1s_sf - Frs2s_sf;}});
|
|
|
|
0x46: fsubd({{Frd_df = Frs1_df - Frs2_df; }});
|
2007-01-30 06:08:42 +01:00
|
|
|
0x47: FpUnimpl::fsubq();
|
2011-09-27 08:48:54 +02:00
|
|
|
0x49: fmuls({{Frds_sf = Frs1s_sf * Frs2s_sf;}});
|
|
|
|
0x4A: fmuld({{Frd_df = Frs1_df * Frs2_df;}});
|
2007-01-30 06:08:42 +01:00
|
|
|
0x4B: FpUnimpl::fmulq();
|
2011-09-27 08:48:54 +02:00
|
|
|
0x4D: fdivs({{Frds_sf = Frs1s_sf / Frs2s_sf;}});
|
|
|
|
0x4E: fdivd({{Frd_df = Frs1_df / Frs2_df;}});
|
2007-01-30 06:08:42 +01:00
|
|
|
0x4F: FpUnimpl::fdivq();
|
2011-09-27 08:48:54 +02:00
|
|
|
0x69: fsmuld({{Frd_df = Frs1s_sf * Frs2s_sf;}});
|
2007-01-30 06:08:42 +01:00
|
|
|
0x6E: FpUnimpl::fdmulq();
|
2011-09-27 08:48:54 +02:00
|
|
|
0x81: fstox({{Frd_sdw = static_cast<int64_t>(Frs2s_sf);}});
|
|
|
|
0x82: fdtox({{Frd_sdw = static_cast<int64_t>(Frs2_df);}});
|
2007-01-30 06:08:42 +01:00
|
|
|
0x83: FpUnimpl::fqtox();
|
2011-09-27 08:48:54 +02:00
|
|
|
0x84: fxtos({{Frds_sf = static_cast<float>(Frs2_sdw);}});
|
|
|
|
0x88: fxtod({{Frd_df = static_cast<double>(Frs2_sdw);}});
|
2007-01-30 06:08:42 +01:00
|
|
|
0x8C: FpUnimpl::fxtoq();
|
2011-09-27 08:48:54 +02:00
|
|
|
0xC4: fitos({{Frds_sf = static_cast<float>(Frs2s_sw);}});
|
|
|
|
0xC6: fdtos({{Frds_sf = Frs2_df;}});
|
2007-01-30 06:08:42 +01:00
|
|
|
0xC7: FpUnimpl::fqtos();
|
2011-09-27 08:48:54 +02:00
|
|
|
0xC8: fitod({{Frd_df = static_cast<double>(Frs2s_sw);}});
|
|
|
|
0xC9: fstod({{Frd_df = Frs2s_sf;}});
|
2007-01-30 06:08:42 +01:00
|
|
|
0xCB: FpUnimpl::fqtod();
|
|
|
|
0xCC: FpUnimpl::fitoq();
|
|
|
|
0xCD: FpUnimpl::fstoq();
|
|
|
|
0xCE: FpUnimpl::fdtoq();
|
2006-07-26 09:42:16 +02:00
|
|
|
0xD1: fstoi({{
|
2011-09-27 08:48:54 +02:00
|
|
|
Frds_sw = static_cast<int32_t>(Frs2s_sf);
|
|
|
|
float t = Frds_sw;
|
|
|
|
if (t != Frs2s_sf)
|
2007-02-03 00:04:42 +01:00
|
|
|
Fsr = insertBits(Fsr, 4,0, 0x01);
|
2006-07-26 09:42:16 +02:00
|
|
|
}});
|
|
|
|
0xD2: fdtoi({{
|
2011-09-27 08:48:54 +02:00
|
|
|
Frds_sw = static_cast<int32_t>(Frs2_df);
|
|
|
|
double t = Frds_sw;
|
|
|
|
if (t != Frs2_df)
|
2007-02-03 00:04:42 +01:00
|
|
|
Fsr = insertBits(Fsr, 4,0, 0x01);
|
2006-07-26 09:42:16 +02:00
|
|
|
}});
|
2007-01-30 06:08:42 +01:00
|
|
|
0xD3: FpUnimpl::fqtoi();
|
2007-01-28 21:42:01 +01:00
|
|
|
default: FailUnimpl::fpop1();
|
2006-07-26 09:42:16 +02:00
|
|
|
}
|
2006-07-22 21:50:40 +02:00
|
|
|
}
|
2007-01-30 04:52:54 +01:00
|
|
|
0x35: decode OPF{
|
2007-02-03 00:04:42 +01:00
|
|
|
format FpBasic{
|
2007-03-11 01:26:54 +01:00
|
|
|
0x01: fmovs_fcc0({{
|
2010-11-11 11:03:58 +01:00
|
|
|
if (passesFpCondition(Fsr<11:10>, COND4))
|
2007-03-11 01:26:54 +01:00
|
|
|
Frds = Frs2s;
|
|
|
|
else
|
|
|
|
Frds = Frds;
|
|
|
|
}});
|
|
|
|
0x02: fmovd_fcc0({{
|
2010-11-11 11:03:58 +01:00
|
|
|
if (passesFpCondition(Fsr<11:10>, COND4))
|
2007-03-11 01:26:54 +01:00
|
|
|
Frd = Frs2;
|
|
|
|
else
|
|
|
|
Frd = Frd;
|
|
|
|
}});
|
|
|
|
0x03: FpUnimpl::fmovq_fcc0();
|
|
|
|
0x25: fmovrsz({{
|
2010-11-11 11:03:58 +01:00
|
|
|
if (Rs1 == 0)
|
2007-03-11 01:26:54 +01:00
|
|
|
Frds = Frs2s;
|
|
|
|
else
|
|
|
|
Frds = Frds;
|
|
|
|
}});
|
|
|
|
0x26: fmovrdz({{
|
2010-11-11 11:03:58 +01:00
|
|
|
if (Rs1 == 0)
|
2007-03-11 01:26:54 +01:00
|
|
|
Frd = Frs2;
|
|
|
|
else
|
|
|
|
Frd = Frd;
|
|
|
|
}});
|
|
|
|
0x27: FpUnimpl::fmovrqz();
|
|
|
|
0x41: fmovs_fcc1({{
|
2010-11-11 11:03:58 +01:00
|
|
|
if (passesFpCondition(Fsr<33:32>, COND4))
|
2007-03-11 01:26:54 +01:00
|
|
|
Frds = Frs2s;
|
|
|
|
else
|
|
|
|
Frds = Frds;
|
|
|
|
}});
|
|
|
|
0x42: fmovd_fcc1({{
|
2010-11-11 11:03:58 +01:00
|
|
|
if (passesFpCondition(Fsr<33:32>, COND4))
|
2007-03-11 01:26:54 +01:00
|
|
|
Frd = Frs2;
|
|
|
|
else
|
|
|
|
Frd = Frd;
|
|
|
|
}});
|
|
|
|
0x43: FpUnimpl::fmovq_fcc1();
|
|
|
|
0x45: fmovrslez({{
|
2016-01-11 11:52:20 +01:00
|
|
|
if ((int64_t)Rs1 <= 0)
|
2007-03-11 01:26:54 +01:00
|
|
|
Frds = Frs2s;
|
|
|
|
else
|
|
|
|
Frds = Frds;
|
|
|
|
}});
|
|
|
|
0x46: fmovrdlez({{
|
2016-01-11 11:52:20 +01:00
|
|
|
if ((int64_t)Rs1 <= 0)
|
2007-03-11 01:26:54 +01:00
|
|
|
Frd = Frs2;
|
|
|
|
else
|
|
|
|
Frd = Frd;
|
|
|
|
}});
|
|
|
|
0x47: FpUnimpl::fmovrqlez();
|
2007-01-30 04:52:54 +01:00
|
|
|
0x51: fcmps({{
|
|
|
|
uint8_t fcc;
|
clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6
This patch addresses a number of minor issues that cause problems when
compiling with clang >= 3.0 and gcc >= 4.6. Most importantly, it
avoids using the deprecated ext/hash_map and instead uses
unordered_map (and similarly so for the hash_set). To make use of the
new STL containers, g++ and clang has to be invoked with "-std=c++0x",
and this is now added for all gcc versions >= 4.6, and for clang >=
3.0. For gcc >= 4.3 and <= 4.5 and clang <= 3.0 we use the tr1
unordered_map to avoid the deprecation warning.
The addition of c++0x in turn causes a few problems, as the
compiler is more stringent and adds a number of new warnings. Below,
the most important issues are enumerated:
1) the use of namespaces is more strict, e.g. for isnan, and all
headers opening the entire namespace std are now fixed.
2) another other issue caused by the more stringent compiler is the
narrowing of the embedded python, which used to be a char array,
and is now unsigned char since there were values larger than 128.
3) a particularly odd issue that arose with the new c++0x behaviour is
found in range.hh, where the operator< causes gcc to complain about
the template type parsing (the "<" is interpreted as the beginning
of a template argument), and the problem seems to be related to the
begin/end members introduced for the range-type iteration, which is
a new feature in c++11.
As a minor update, this patch also fixes the build flags for the clang
debug target that used to be shared with gcc and incorrectly use
"-ggdb".
2012-04-14 11:43:31 +02:00
|
|
|
if (std::isnan(Frs1s) || std::isnan(Frs2s))
|
2007-01-30 04:52:54 +01:00
|
|
|
fcc = 3;
|
2010-11-11 11:03:58 +01:00
|
|
|
else if (Frs1s < Frs2s)
|
2007-01-30 04:52:54 +01:00
|
|
|
fcc = 1;
|
2010-11-11 11:03:58 +01:00
|
|
|
else if (Frs1s > Frs2s)
|
2007-01-30 04:52:54 +01:00
|
|
|
fcc = 2;
|
|
|
|
else
|
|
|
|
fcc = 0;
|
|
|
|
uint8_t firstbit = 10;
|
2010-11-11 11:03:58 +01:00
|
|
|
if (FCMPCC)
|
2007-01-30 04:52:54 +01:00
|
|
|
firstbit = FCMPCC * 2 + 30;
|
|
|
|
Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
|
|
|
|
}});
|
|
|
|
0x52: fcmpd({{
|
|
|
|
uint8_t fcc;
|
clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6
This patch addresses a number of minor issues that cause problems when
compiling with clang >= 3.0 and gcc >= 4.6. Most importantly, it
avoids using the deprecated ext/hash_map and instead uses
unordered_map (and similarly so for the hash_set). To make use of the
new STL containers, g++ and clang has to be invoked with "-std=c++0x",
and this is now added for all gcc versions >= 4.6, and for clang >=
3.0. For gcc >= 4.3 and <= 4.5 and clang <= 3.0 we use the tr1
unordered_map to avoid the deprecation warning.
The addition of c++0x in turn causes a few problems, as the
compiler is more stringent and adds a number of new warnings. Below,
the most important issues are enumerated:
1) the use of namespaces is more strict, e.g. for isnan, and all
headers opening the entire namespace std are now fixed.
2) another other issue caused by the more stringent compiler is the
narrowing of the embedded python, which used to be a char array,
and is now unsigned char since there were values larger than 128.
3) a particularly odd issue that arose with the new c++0x behaviour is
found in range.hh, where the operator< causes gcc to complain about
the template type parsing (the "<" is interpreted as the beginning
of a template argument), and the problem seems to be related to the
begin/end members introduced for the range-type iteration, which is
a new feature in c++11.
As a minor update, this patch also fixes the build flags for the clang
debug target that used to be shared with gcc and incorrectly use
"-ggdb".
2012-04-14 11:43:31 +02:00
|
|
|
if (std::isnan(Frs1) || std::isnan(Frs2))
|
2007-01-30 04:52:54 +01:00
|
|
|
fcc = 3;
|
2010-11-11 11:03:58 +01:00
|
|
|
else if (Frs1 < Frs2)
|
2007-01-30 04:52:54 +01:00
|
|
|
fcc = 1;
|
2010-11-11 11:03:58 +01:00
|
|
|
else if (Frs1 > Frs2)
|
2007-01-30 04:52:54 +01:00
|
|
|
fcc = 2;
|
|
|
|
else
|
|
|
|
fcc = 0;
|
|
|
|
uint8_t firstbit = 10;
|
2010-11-11 11:03:58 +01:00
|
|
|
if (FCMPCC)
|
2007-01-30 04:52:54 +01:00
|
|
|
firstbit = FCMPCC * 2 + 30;
|
|
|
|
Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
|
|
|
|
}});
|
2007-01-30 06:08:42 +01:00
|
|
|
0x53: FpUnimpl::fcmpq();
|
2007-01-30 17:22:22 +01:00
|
|
|
0x55: fcmpes({{
|
2007-01-30 04:52:54 +01:00
|
|
|
uint8_t fcc = 0;
|
clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6
This patch addresses a number of minor issues that cause problems when
compiling with clang >= 3.0 and gcc >= 4.6. Most importantly, it
avoids using the deprecated ext/hash_map and instead uses
unordered_map (and similarly so for the hash_set). To make use of the
new STL containers, g++ and clang has to be invoked with "-std=c++0x",
and this is now added for all gcc versions >= 4.6, and for clang >=
3.0. For gcc >= 4.3 and <= 4.5 and clang <= 3.0 we use the tr1
unordered_map to avoid the deprecation warning.
The addition of c++0x in turn causes a few problems, as the
compiler is more stringent and adds a number of new warnings. Below,
the most important issues are enumerated:
1) the use of namespaces is more strict, e.g. for isnan, and all
headers opening the entire namespace std are now fixed.
2) another other issue caused by the more stringent compiler is the
narrowing of the embedded python, which used to be a char array,
and is now unsigned char since there were values larger than 128.
3) a particularly odd issue that arose with the new c++0x behaviour is
found in range.hh, where the operator< causes gcc to complain about
the template type parsing (the "<" is interpreted as the beginning
of a template argument), and the problem seems to be related to the
begin/end members introduced for the range-type iteration, which is
a new feature in c++11.
As a minor update, this patch also fixes the build flags for the clang
debug target that used to be shared with gcc and incorrectly use
"-ggdb".
2012-04-14 11:43:31 +02:00
|
|
|
if (std::isnan(Frs1s) || std::isnan(Frs2s))
|
2014-10-16 11:49:51 +02:00
|
|
|
fault = std::make_shared<FpExceptionIEEE754>();
|
2010-11-11 11:03:58 +01:00
|
|
|
if (Frs1s < Frs2s)
|
2007-01-30 04:52:54 +01:00
|
|
|
fcc = 1;
|
2010-11-11 11:03:58 +01:00
|
|
|
else if (Frs1s > Frs2s)
|
2007-01-30 04:52:54 +01:00
|
|
|
fcc = 2;
|
|
|
|
uint8_t firstbit = 10;
|
2010-11-11 11:03:58 +01:00
|
|
|
if (FCMPCC)
|
2007-01-30 04:52:54 +01:00
|
|
|
firstbit = FCMPCC * 2 + 30;
|
|
|
|
Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
|
|
|
|
}});
|
2007-01-30 17:22:22 +01:00
|
|
|
0x56: fcmped({{
|
2007-01-30 04:52:54 +01:00
|
|
|
uint8_t fcc = 0;
|
clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6
This patch addresses a number of minor issues that cause problems when
compiling with clang >= 3.0 and gcc >= 4.6. Most importantly, it
avoids using the deprecated ext/hash_map and instead uses
unordered_map (and similarly so for the hash_set). To make use of the
new STL containers, g++ and clang has to be invoked with "-std=c++0x",
and this is now added for all gcc versions >= 4.6, and for clang >=
3.0. For gcc >= 4.3 and <= 4.5 and clang <= 3.0 we use the tr1
unordered_map to avoid the deprecation warning.
The addition of c++0x in turn causes a few problems, as the
compiler is more stringent and adds a number of new warnings. Below,
the most important issues are enumerated:
1) the use of namespaces is more strict, e.g. for isnan, and all
headers opening the entire namespace std are now fixed.
2) another other issue caused by the more stringent compiler is the
narrowing of the embedded python, which used to be a char array,
and is now unsigned char since there were values larger than 128.
3) a particularly odd issue that arose with the new c++0x behaviour is
found in range.hh, where the operator< causes gcc to complain about
the template type parsing (the "<" is interpreted as the beginning
of a template argument), and the problem seems to be related to the
begin/end members introduced for the range-type iteration, which is
a new feature in c++11.
As a minor update, this patch also fixes the build flags for the clang
debug target that used to be shared with gcc and incorrectly use
"-ggdb".
2012-04-14 11:43:31 +02:00
|
|
|
if (std::isnan(Frs1) || std::isnan(Frs2))
|
2014-10-16 11:49:51 +02:00
|
|
|
fault = std::make_shared<FpExceptionIEEE754>();
|
2010-11-11 11:03:58 +01:00
|
|
|
if (Frs1 < Frs2)
|
2007-01-30 04:52:54 +01:00
|
|
|
fcc = 1;
|
2010-11-11 11:03:58 +01:00
|
|
|
else if (Frs1 > Frs2)
|
2007-01-30 04:52:54 +01:00
|
|
|
fcc = 2;
|
|
|
|
uint8_t firstbit = 10;
|
2010-11-11 11:03:58 +01:00
|
|
|
if (FCMPCC)
|
2007-01-30 04:52:54 +01:00
|
|
|
firstbit = FCMPCC * 2 + 30;
|
|
|
|
Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
|
|
|
|
}});
|
2007-01-30 17:22:22 +01:00
|
|
|
0x57: FpUnimpl::fcmpeq();
|
2007-03-11 01:26:54 +01:00
|
|
|
0x65: fmovrslz({{
|
2016-01-11 11:52:20 +01:00
|
|
|
if ((int64_t)Rs1 < 0)
|
2007-03-11 01:26:54 +01:00
|
|
|
Frds = Frs2s;
|
|
|
|
else
|
|
|
|
Frds = Frds;
|
|
|
|
}});
|
|
|
|
0x66: fmovrdlz({{
|
2016-01-11 11:52:20 +01:00
|
|
|
if ((int64_t)Rs1 < 0)
|
2007-03-11 01:26:54 +01:00
|
|
|
Frd = Frs2;
|
|
|
|
else
|
|
|
|
Frd = Frd;
|
|
|
|
}});
|
|
|
|
0x67: FpUnimpl::fmovrqlz();
|
|
|
|
0x81: fmovs_fcc2({{
|
2010-11-11 11:03:58 +01:00
|
|
|
if (passesFpCondition(Fsr<35:34>, COND4))
|
2007-03-11 01:26:54 +01:00
|
|
|
Frds = Frs2s;
|
|
|
|
else
|
|
|
|
Frds = Frds;
|
|
|
|
}});
|
|
|
|
0x82: fmovd_fcc2({{
|
2010-11-11 11:03:58 +01:00
|
|
|
if (passesFpCondition(Fsr<35:34>, COND4))
|
2007-03-11 01:26:54 +01:00
|
|
|
Frd = Frs2;
|
|
|
|
else
|
|
|
|
Frd = Frd;
|
|
|
|
}});
|
|
|
|
0x83: FpUnimpl::fmovq_fcc2();
|
|
|
|
0xA5: fmovrsnz({{
|
2010-11-11 11:03:58 +01:00
|
|
|
if (Rs1 != 0)
|
2007-03-11 01:26:54 +01:00
|
|
|
Frds = Frs2s;
|
|
|
|
else
|
|
|
|
Frds = Frds;
|
|
|
|
}});
|
|
|
|
0xA6: fmovrdnz({{
|
2010-11-11 11:03:58 +01:00
|
|
|
if (Rs1 != 0)
|
2007-03-11 01:26:54 +01:00
|
|
|
Frd = Frs2;
|
|
|
|
else
|
|
|
|
Frd = Frd;
|
|
|
|
}});
|
|
|
|
0xA7: FpUnimpl::fmovrqnz();
|
|
|
|
0xC1: fmovs_fcc3({{
|
2010-11-11 11:03:58 +01:00
|
|
|
if (passesFpCondition(Fsr<37:36>, COND4))
|
2007-03-11 01:26:54 +01:00
|
|
|
Frds = Frs2s;
|
|
|
|
else
|
|
|
|
Frds = Frds;
|
|
|
|
}});
|
|
|
|
0xC2: fmovd_fcc3({{
|
2010-11-11 11:03:58 +01:00
|
|
|
if (passesFpCondition(Fsr<37:36>, COND4))
|
2007-03-11 01:26:54 +01:00
|
|
|
Frd = Frs2;
|
|
|
|
else
|
|
|
|
Frd = Frd;
|
|
|
|
}});
|
|
|
|
0xC3: FpUnimpl::fmovq_fcc3();
|
|
|
|
0xC5: fmovrsgz({{
|
2016-01-11 11:52:20 +01:00
|
|
|
if ((int64_t)Rs1 > 0)
|
2007-03-11 01:26:54 +01:00
|
|
|
Frds = Frs2s;
|
|
|
|
else
|
|
|
|
Frds = Frds;
|
|
|
|
}});
|
|
|
|
0xC6: fmovrdgz({{
|
2016-01-11 11:52:20 +01:00
|
|
|
if ((int64_t)Rs1 > 0)
|
2007-03-11 01:26:54 +01:00
|
|
|
Frd = Frs2;
|
|
|
|
else
|
|
|
|
Frd = Frd;
|
|
|
|
}});
|
|
|
|
0xC7: FpUnimpl::fmovrqgz();
|
|
|
|
0xE5: fmovrsgez({{
|
2016-01-11 11:52:20 +01:00
|
|
|
if ((int64_t)Rs1 >= 0)
|
2007-03-11 01:26:54 +01:00
|
|
|
Frds = Frs2s;
|
|
|
|
else
|
|
|
|
Frds = Frds;
|
|
|
|
}});
|
|
|
|
0xE6: fmovrdgez({{
|
2016-01-11 11:52:20 +01:00
|
|
|
if ((int64_t)Rs1 >= 0)
|
2007-03-11 01:26:54 +01:00
|
|
|
Frd = Frs2;
|
|
|
|
else
|
|
|
|
Frd = Frd;
|
|
|
|
}});
|
|
|
|
0xE7: FpUnimpl::fmovrqgez();
|
|
|
|
0x101: fmovs_icc({{
|
2010-11-11 11:03:58 +01:00
|
|
|
if (passesCondition(Ccr<3:0>, COND4))
|
2007-03-11 01:26:54 +01:00
|
|
|
Frds = Frs2s;
|
|
|
|
else
|
|
|
|
Frds = Frds;
|
|
|
|
}});
|
|
|
|
0x102: fmovd_icc({{
|
2010-11-11 11:03:58 +01:00
|
|
|
if (passesCondition(Ccr<3:0>, COND4))
|
2007-03-11 01:26:54 +01:00
|
|
|
Frd = Frs2;
|
|
|
|
else
|
|
|
|
Frd = Frd;
|
|
|
|
}});
|
|
|
|
0x103: FpUnimpl::fmovq_icc();
|
|
|
|
0x181: fmovs_xcc({{
|
2010-11-11 11:03:58 +01:00
|
|
|
if (passesCondition(Ccr<7:4>, COND4))
|
2007-03-11 01:26:54 +01:00
|
|
|
Frds = Frs2s;
|
|
|
|
else
|
|
|
|
Frds = Frds;
|
|
|
|
}});
|
|
|
|
0x182: fmovd_xcc({{
|
2010-11-11 11:03:58 +01:00
|
|
|
if (passesCondition(Ccr<7:4>, COND4))
|
2007-03-11 01:26:54 +01:00
|
|
|
Frd = Frs2;
|
|
|
|
else
|
|
|
|
Frd = Frd;
|
|
|
|
}});
|
|
|
|
0x183: FpUnimpl::fmovq_xcc();
|
2007-01-30 04:52:54 +01:00
|
|
|
default: FailUnimpl::fpop2();
|
|
|
|
}
|
|
|
|
}
|
2010-11-11 11:03:58 +01:00
|
|
|
// This used to be just impdep1, but now it's a whole bunch
|
|
|
|
// of instructions
|
2006-07-22 21:50:40 +02:00
|
|
|
0x36: decode OPF{
|
2007-01-28 21:42:01 +01:00
|
|
|
0x00: FailUnimpl::edge8();
|
|
|
|
0x01: FailUnimpl::edge8n();
|
|
|
|
0x02: FailUnimpl::edge8l();
|
|
|
|
0x03: FailUnimpl::edge8ln();
|
|
|
|
0x04: FailUnimpl::edge16();
|
|
|
|
0x05: FailUnimpl::edge16n();
|
|
|
|
0x06: FailUnimpl::edge16l();
|
|
|
|
0x07: FailUnimpl::edge16ln();
|
|
|
|
0x08: FailUnimpl::edge32();
|
|
|
|
0x09: FailUnimpl::edge32n();
|
|
|
|
0x0A: FailUnimpl::edge32l();
|
|
|
|
0x0B: FailUnimpl::edge32ln();
|
|
|
|
0x10: FailUnimpl::array8();
|
|
|
|
0x12: FailUnimpl::array16();
|
|
|
|
0x14: FailUnimpl::array32();
|
2006-08-21 20:23:39 +02:00
|
|
|
0x18: BasicOperate::alignaddr({{
|
2006-07-26 09:42:16 +02:00
|
|
|
uint64_t sum = Rs1 + Rs2;
|
2006-08-21 20:23:39 +02:00
|
|
|
Rd = sum & ~7;
|
2006-07-26 09:42:16 +02:00
|
|
|
Gsr = (Gsr & ~7) | (sum & 7);
|
|
|
|
}});
|
2007-01-28 21:42:01 +01:00
|
|
|
0x19: FailUnimpl::bmask();
|
2006-07-26 09:42:16 +02:00
|
|
|
0x1A: BasicOperate::alignaddresslittle({{
|
|
|
|
uint64_t sum = Rs1 + Rs2;
|
2006-08-21 20:23:39 +02:00
|
|
|
Rd = sum & ~7;
|
2006-07-26 09:42:16 +02:00
|
|
|
Gsr = (Gsr & ~7) | ((~sum + 1) & 7);
|
|
|
|
}});
|
2007-01-28 21:42:01 +01:00
|
|
|
0x20: FailUnimpl::fcmple16();
|
|
|
|
0x22: FailUnimpl::fcmpne16();
|
|
|
|
0x24: FailUnimpl::fcmple32();
|
|
|
|
0x26: FailUnimpl::fcmpne32();
|
|
|
|
0x28: FailUnimpl::fcmpgt16();
|
|
|
|
0x2A: FailUnimpl::fcmpeq16();
|
|
|
|
0x2C: FailUnimpl::fcmpgt32();
|
|
|
|
0x2E: FailUnimpl::fcmpeq32();
|
|
|
|
0x31: FailUnimpl::fmul8x16();
|
|
|
|
0x33: FailUnimpl::fmul8x16au();
|
|
|
|
0x35: FailUnimpl::fmul8x16al();
|
|
|
|
0x36: FailUnimpl::fmul8sux16();
|
|
|
|
0x37: FailUnimpl::fmul8ulx16();
|
|
|
|
0x38: FailUnimpl::fmuld8sux16();
|
|
|
|
0x39: FailUnimpl::fmuld8ulx16();
|
2014-10-16 11:49:51 +02:00
|
|
|
0x3A: Trap::fpack32({{fault = std::make_shared<IllegalInstruction>();}});
|
|
|
|
0x3B: Trap::fpack16({{fault = std::make_shared<IllegalInstruction>();}});
|
|
|
|
0x3D: Trap::fpackfix({{fault = std::make_shared<IllegalInstruction>();}});
|
|
|
|
0x3E: Trap::pdist({{fault = std::make_shared<IllegalInstruction>();}});
|
2006-07-26 09:42:16 +02:00
|
|
|
0x48: BasicOperate::faligndata({{
|
2011-09-27 08:48:54 +02:00
|
|
|
uint64_t msbX = Frs1_udw;
|
|
|
|
uint64_t lsbX = Frs2_udw;
|
2010-11-11 11:03:58 +01:00
|
|
|
// Some special cases need to be split out, first
|
|
|
|
// because they're the most likely to be used, and
|
|
|
|
// second because otherwise, we end up shifting by
|
|
|
|
// greater than the width of the type being shifted,
|
|
|
|
// namely 64, which produces undefined results
|
|
|
|
// according to the C standard.
|
|
|
|
switch (Gsr<2:0>) {
|
|
|
|
case 0:
|
2011-09-27 08:48:54 +02:00
|
|
|
Frd_udw = msbX;
|
2010-11-11 11:03:58 +01:00
|
|
|
break;
|
|
|
|
case 8:
|
2011-09-27 08:48:54 +02:00
|
|
|
Frd_udw = lsbX;
|
2010-11-11 11:03:58 +01:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
uint64_t msbShift = Gsr<2:0> * 8;
|
|
|
|
uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
|
|
|
|
uint64_t msbMask = ((uint64_t)(-1)) >> msbShift;
|
|
|
|
uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
|
2011-09-27 08:48:54 +02:00
|
|
|
Frd_udw = ((msbX & msbMask) << msbShift) |
|
2010-11-11 11:03:58 +01:00
|
|
|
((lsbX & lsbMask) >> lsbShift);
|
2006-08-29 08:40:24 +02:00
|
|
|
}
|
2006-07-26 09:42:16 +02:00
|
|
|
}});
|
2014-10-16 11:49:51 +02:00
|
|
|
0x4B: Trap::fpmerge({{fault = std::make_shared<IllegalInstruction>();}});
|
2007-01-28 21:42:01 +01:00
|
|
|
0x4C: FailUnimpl::bshuffle();
|
|
|
|
0x4D: FailUnimpl::fexpand();
|
|
|
|
0x50: FailUnimpl::fpadd16();
|
|
|
|
0x51: FailUnimpl::fpadd16s();
|
|
|
|
0x52: FailUnimpl::fpadd32();
|
|
|
|
0x53: FailUnimpl::fpadd32s();
|
|
|
|
0x54: FailUnimpl::fpsub16();
|
|
|
|
0x55: FailUnimpl::fpsub16s();
|
|
|
|
0x56: FailUnimpl::fpsub32();
|
|
|
|
0x57: FailUnimpl::fpsub32s();
|
2011-09-27 08:48:54 +02:00
|
|
|
0x60: FpBasic::fzero({{Frd_df = 0;}});
|
|
|
|
0x61: FpBasic::fzeros({{Frds_sf = 0;}});
|
2007-01-28 21:42:01 +01:00
|
|
|
0x62: FailUnimpl::fnor();
|
|
|
|
0x63: FailUnimpl::fnors();
|
|
|
|
0x64: FailUnimpl::fandnot2();
|
|
|
|
0x65: FailUnimpl::fandnot2s();
|
2007-02-03 00:04:42 +01:00
|
|
|
0x66: FpBasic::fnot2({{
|
2011-09-27 08:48:54 +02:00
|
|
|
Frd_df = (double)(~((uint64_t)Frs2_df));
|
2006-07-26 09:42:16 +02:00
|
|
|
}});
|
2007-02-03 00:04:42 +01:00
|
|
|
0x67: FpBasic::fnot2s({{
|
2011-09-27 08:48:54 +02:00
|
|
|
Frds_sf = (float)(~((uint32_t)Frs2s_sf));
|
2006-07-26 09:42:16 +02:00
|
|
|
}});
|
2007-01-28 21:42:01 +01:00
|
|
|
0x68: FailUnimpl::fandnot1();
|
|
|
|
0x69: FailUnimpl::fandnot1s();
|
2007-02-03 00:04:42 +01:00
|
|
|
0x6A: FpBasic::fnot1({{
|
2011-09-27 08:48:54 +02:00
|
|
|
Frd_df = (double)(~((uint64_t)Frs1_df));
|
2006-07-26 09:42:16 +02:00
|
|
|
}});
|
2007-02-03 00:04:42 +01:00
|
|
|
0x6B: FpBasic::fnot1s({{
|
2011-09-27 08:48:54 +02:00
|
|
|
Frds_sf = (float)(~((uint32_t)Frs1s_sf));
|
2006-07-26 09:42:16 +02:00
|
|
|
}});
|
2007-01-28 21:42:01 +01:00
|
|
|
0x6C: FailUnimpl::fxor();
|
|
|
|
0x6D: FailUnimpl::fxors();
|
|
|
|
0x6E: FailUnimpl::fnand();
|
|
|
|
0x6F: FailUnimpl::fnands();
|
|
|
|
0x70: FailUnimpl::fand();
|
|
|
|
0x71: FailUnimpl::fands();
|
|
|
|
0x72: FailUnimpl::fxnor();
|
|
|
|
0x73: FailUnimpl::fxnors();
|
2011-09-27 08:48:54 +02:00
|
|
|
0x74: FpBasic::fsrc1({{Frd_udw = Frs1_udw;}});
|
|
|
|
0x75: FpBasic::fsrc1s({{Frds_uw = Frs1s_uw;}});
|
2007-01-28 21:42:01 +01:00
|
|
|
0x76: FailUnimpl::fornot2();
|
|
|
|
0x77: FailUnimpl::fornot2s();
|
2011-09-27 08:48:54 +02:00
|
|
|
0x78: FpBasic::fsrc2({{Frd_udw = Frs2_udw;}});
|
|
|
|
0x79: FpBasic::fsrc2s({{Frds_uw = Frs2s_uw;}});
|
2007-01-28 21:42:01 +01:00
|
|
|
0x7A: FailUnimpl::fornot1();
|
|
|
|
0x7B: FailUnimpl::fornot1s();
|
|
|
|
0x7C: FailUnimpl::for();
|
|
|
|
0x7D: FailUnimpl::fors();
|
2011-09-27 08:48:54 +02:00
|
|
|
0x7E: FpBasic::fone({{Frd_udw = std::numeric_limits<uint64_t>::max();}});
|
|
|
|
0x7F: FpBasic::fones({{Frds_uw = std::numeric_limits<uint32_t>::max();}});
|
2014-10-16 11:49:51 +02:00
|
|
|
0x80: Trap::shutdown({{fault = std::make_shared<IllegalInstruction>();}});
|
2007-01-28 21:42:01 +01:00
|
|
|
0x81: FailUnimpl::siam();
|
2006-07-22 21:50:40 +02:00
|
|
|
}
|
2007-02-22 03:06:17 +01:00
|
|
|
// M5 special opcodes use the reserved IMPDEP2A opcode space
|
|
|
|
0x37: decode M5FUNC {
|
2007-02-28 17:49:17 +01:00
|
|
|
format BasicOperate {
|
|
|
|
// we have 7 bits of space here to play with...
|
2010-12-08 09:27:43 +01:00
|
|
|
0x21: m5exit({{
|
|
|
|
PseudoInst::m5exit(xc->tcBase(), O0);
|
|
|
|
}}, No_OpClass, IsNonSpeculative);
|
2007-02-28 17:49:17 +01:00
|
|
|
0x50: m5readfile({{
|
2010-12-08 09:27:43 +01:00
|
|
|
O0 = PseudoInst::readfile(xc->tcBase(), O0, O1, O2);
|
|
|
|
}}, IsNonSpeculative);
|
|
|
|
0x51: m5break({{
|
|
|
|
PseudoInst::debugbreak(xc->tcBase());
|
|
|
|
}}, IsNonSpeculative);
|
2007-02-28 17:49:17 +01:00
|
|
|
0x54: m5panic({{
|
2010-12-08 09:27:43 +01:00
|
|
|
panic("M5 panic instruction called at pc = %#x.", PC);
|
|
|
|
}}, No_OpClass, IsNonSpeculative);
|
2007-02-28 17:49:17 +01:00
|
|
|
}
|
2014-10-16 11:49:51 +02:00
|
|
|
default: Trap::impdep2({{fault = std::make_shared<IllegalInstruction>();}});
|
2007-02-22 03:06:17 +01:00
|
|
|
}
|
2006-04-06 20:52:44 +02:00
|
|
|
0x38: Branch::jmpl({{
|
|
|
|
Addr target = Rs1 + Rs2_or_imm13;
|
2010-11-11 11:03:58 +01:00
|
|
|
if (target & 0x3) {
|
2014-10-16 11:49:51 +02:00
|
|
|
fault = std::make_shared<MemAddressNotAligned>();
|
2010-11-11 11:03:58 +01:00
|
|
|
} else {
|
2012-02-11 23:16:38 +01:00
|
|
|
if (Pstate.am)
|
2010-12-08 09:27:43 +01:00
|
|
|
Rd = (PC)<31:0>;
|
2007-01-23 21:50:03 +01:00
|
|
|
else
|
2010-12-08 09:27:43 +01:00
|
|
|
Rd = PC;
|
|
|
|
NNPC = target;
|
2006-03-16 19:58:50 +01:00
|
|
|
}
|
2011-06-09 07:34:06 +02:00
|
|
|
}}, IsUncondControl, IsIndirectControl);
|
2006-04-06 20:52:44 +02:00
|
|
|
0x39: Branch::return({{
|
|
|
|
Addr target = Rs1 + Rs2_or_imm13;
|
2010-11-11 11:03:58 +01:00
|
|
|
if (fault == NoFault) {
|
|
|
|
// Check for fills which are higher priority than alignment
|
|
|
|
// faults.
|
|
|
|
if (Canrestore == 0) {
|
|
|
|
if (Otherwin)
|
2014-10-16 11:49:51 +02:00
|
|
|
fault = std::make_shared<FillNOther>(4*Wstate<5:3>);
|
2006-04-18 15:27:22 +02:00
|
|
|
else
|
2014-10-16 11:49:51 +02:00
|
|
|
fault = std::make_shared<FillNNormal>(4*Wstate<2:0>);
|
2010-11-11 11:03:58 +01:00
|
|
|
} else if (target & 0x3) { // Check for alignment faults
|
2014-10-16 11:49:51 +02:00
|
|
|
fault = std::make_shared<MemAddressNotAligned>();
|
2010-11-11 11:03:58 +01:00
|
|
|
} else {
|
2010-12-08 09:27:43 +01:00
|
|
|
NNPC = target;
|
2006-10-25 23:54:14 +02:00
|
|
|
Cwp = (Cwp - 1 + NWindows) % NWindows;
|
2006-04-18 15:27:22 +02:00
|
|
|
Cansave = Cansave + 1;
|
|
|
|
Canrestore = Canrestore - 1;
|
|
|
|
}
|
|
|
|
}
|
2011-06-09 07:34:06 +02:00
|
|
|
}}, IsUncondControl, IsIndirectControl, IsReturn);
|
2006-04-06 20:52:44 +02:00
|
|
|
0x3A: decode CC
|
|
|
|
{
|
|
|
|
0x0: Trap::tcci({{
|
2010-11-11 11:03:58 +01:00
|
|
|
if (passesCondition(Ccr<3:0>, COND2)) {
|
2006-04-18 15:27:22 +02:00
|
|
|
int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
|
|
|
|
DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
|
2014-10-16 11:49:51 +02:00
|
|
|
fault = std::make_shared<TrapInstruction>(lTrapNum);
|
2006-04-18 15:27:22 +02:00
|
|
|
}
|
2007-08-01 02:34:08 +02:00
|
|
|
}}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
|
2006-04-06 20:52:44 +02:00
|
|
|
0x2: Trap::tccx({{
|
2010-11-11 11:03:58 +01:00
|
|
|
if (passesCondition(Ccr<7:4>, COND2)) {
|
2006-04-18 15:27:22 +02:00
|
|
|
int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
|
|
|
|
DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
|
2014-10-16 11:49:51 +02:00
|
|
|
fault = std::make_shared<TrapInstruction>(lTrapNum);
|
2006-04-18 15:27:22 +02:00
|
|
|
}
|
2007-08-01 02:34:08 +02:00
|
|
|
}}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
|
2006-04-06 20:52:44 +02:00
|
|
|
}
|
2007-02-22 03:06:17 +01:00
|
|
|
0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier,
|
|
|
|
MemWriteOp);
|
2006-04-06 20:52:44 +02:00
|
|
|
0x3C: save({{
|
2010-11-11 11:03:58 +01:00
|
|
|
if (Cansave == 0) {
|
|
|
|
if (Otherwin)
|
2014-10-16 11:49:51 +02:00
|
|
|
fault = std::make_shared<SpillNOther>(4*Wstate<5:3>);
|
2006-04-01 03:31:53 +02:00
|
|
|
else
|
2014-10-16 11:49:51 +02:00
|
|
|
fault = std::make_shared<SpillNNormal>(4*Wstate<2:0>);
|
2010-11-11 11:03:58 +01:00
|
|
|
} else if (Cleanwin - Canrestore == 0) {
|
2014-10-16 11:49:51 +02:00
|
|
|
fault = std::make_shared<CleanWindow>();
|
2010-11-11 11:03:58 +01:00
|
|
|
} else {
|
2006-04-06 20:52:44 +02:00
|
|
|
Cwp = (Cwp + 1) % NWindows;
|
2006-12-06 11:43:25 +01:00
|
|
|
Rd_next = Rs1 + Rs2_or_imm13;
|
2006-04-18 15:27:22 +02:00
|
|
|
Cansave = Cansave - 1;
|
|
|
|
Canrestore = Canrestore + 1;
|
2006-04-06 20:52:44 +02:00
|
|
|
}
|
|
|
|
}});
|
|
|
|
0x3D: restore({{
|
2010-11-11 11:03:58 +01:00
|
|
|
if (Canrestore == 0) {
|
|
|
|
if (Otherwin)
|
2014-10-16 11:49:51 +02:00
|
|
|
fault = std::make_shared<FillNOther>(4*Wstate<5:3>);
|
2006-04-06 20:52:44 +02:00
|
|
|
else
|
2014-10-16 11:49:51 +02:00
|
|
|
fault = std::make_shared<FillNNormal>(4*Wstate<2:0>);
|
2010-11-11 11:03:58 +01:00
|
|
|
} else {
|
2006-10-25 23:54:14 +02:00
|
|
|
Cwp = (Cwp - 1 + NWindows) % NWindows;
|
2006-12-06 11:43:25 +01:00
|
|
|
Rd_prev = Rs1 + Rs2_or_imm13;
|
2006-04-18 15:27:22 +02:00
|
|
|
Cansave = Cansave + 1;
|
|
|
|
Canrestore = Canrestore - 1;
|
2006-03-16 19:58:50 +01:00
|
|
|
}
|
2006-04-06 20:52:44 +02:00
|
|
|
}});
|
|
|
|
0x3E: decode FCN {
|
|
|
|
0x0: Priv::done({{
|
2006-05-27 00:40:00 +02:00
|
|
|
Cwp = Tstate<4:0>;
|
|
|
|
Pstate = Tstate<20:8>;
|
|
|
|
Asi = Tstate<31:24>;
|
|
|
|
Ccr = Tstate<39:32>;
|
|
|
|
Gl = Tstate<42:40>;
|
2006-12-08 00:50:33 +01:00
|
|
|
Hpstate = Htstate;
|
2010-12-08 09:27:43 +01:00
|
|
|
NPC = Tnpc;
|
|
|
|
NNPC = Tnpc + 4;
|
2006-04-06 20:52:44 +02:00
|
|
|
Tl = Tl - 1;
|
2007-09-26 05:09:25 +02:00
|
|
|
}}, checkTl=true);
|
2006-05-29 05:49:29 +02:00
|
|
|
0x1: Priv::retry({{
|
2006-05-27 00:40:00 +02:00
|
|
|
Cwp = Tstate<4:0>;
|
|
|
|
Pstate = Tstate<20:8>;
|
|
|
|
Asi = Tstate<31:24>;
|
|
|
|
Ccr = Tstate<39:32>;
|
|
|
|
Gl = Tstate<42:40>;
|
2006-12-10 00:00:40 +01:00
|
|
|
Hpstate = Htstate;
|
2010-12-08 09:27:43 +01:00
|
|
|
NPC = Tpc;
|
|
|
|
NNPC = Tnpc;
|
2006-04-06 20:52:44 +02:00
|
|
|
Tl = Tl - 1;
|
2007-09-26 05:09:25 +02:00
|
|
|
}}, checkTl=true);
|
2006-03-16 19:58:50 +01:00
|
|
|
}
|
2006-04-06 20:52:44 +02:00
|
|
|
}
|
2006-03-16 19:58:50 +01:00
|
|
|
}
|
|
|
|
0x3: decode OP3 {
|
2006-04-06 20:52:44 +02:00
|
|
|
format Load {
|
2011-09-27 08:48:54 +02:00
|
|
|
0x00: lduw({{Rd = Mem_uw;}});
|
|
|
|
0x01: ldub({{Rd = Mem_ub;}});
|
|
|
|
0x02: lduh({{Rd = Mem_uhw;}});
|
2006-12-16 18:54:28 +01:00
|
|
|
0x03: ldtw({{
|
2011-09-27 08:48:54 +02:00
|
|
|
RdLow = (Mem_tuw).a;
|
|
|
|
RdHigh = (Mem_tuw).b;
|
2006-10-12 23:38:06 +02:00
|
|
|
}});
|
2006-04-06 20:52:44 +02:00
|
|
|
}
|
|
|
|
format Store {
|
2011-09-27 08:48:54 +02:00
|
|
|
0x04: stw({{Mem_uw = Rd_sw;}});
|
|
|
|
0x05: stb({{Mem_ub = Rd_sb;}});
|
|
|
|
0x06: sth({{Mem_uhw = Rd_shw;}});
|
2007-03-11 23:12:33 +01:00
|
|
|
0x07: sttw({{
|
2010-11-11 11:03:58 +01:00
|
|
|
// This temporary needs to be here so that the parser
|
|
|
|
// will correctly identify this instruction as a store.
|
|
|
|
// It's probably either the parenthesis or referencing
|
|
|
|
// the member variable that throws confuses it.
|
2007-03-18 02:23:03 +01:00
|
|
|
Twin32_t temp;
|
|
|
|
temp.a = RdLow<31:0>;
|
|
|
|
temp.b = RdHigh<31:0>;
|
2011-09-27 08:48:54 +02:00
|
|
|
Mem_tuw = temp;
|
2007-03-11 23:12:33 +01:00
|
|
|
}});
|
2006-04-06 20:52:44 +02:00
|
|
|
}
|
|
|
|
format Load {
|
2011-09-27 08:48:54 +02:00
|
|
|
0x08: ldsw({{Rd = Mem_sw;}});
|
|
|
|
0x09: ldsb({{Rd = Mem_sb;}});
|
|
|
|
0x0A: ldsh({{Rd = Mem_shw;}});
|
|
|
|
0x0B: ldx({{Rd = Mem_sdw;}});
|
2006-04-06 20:52:44 +02:00
|
|
|
}
|
2011-09-27 08:48:54 +02:00
|
|
|
0x0D: Swap::ldstub({{Mem_ub = 0xFF;}},
|
2007-02-12 19:06:30 +01:00
|
|
|
{{
|
|
|
|
uint8_t tmp = mem_data;
|
2011-09-27 08:48:54 +02:00
|
|
|
Rd_ub = tmp;
|
2007-02-12 19:06:30 +01:00
|
|
|
}}, MEM_SWAP);
|
2011-09-27 08:48:54 +02:00
|
|
|
0x0E: Store::stx({{Mem_udw = Rd}});
|
|
|
|
0x0F: Swap::swap({{Mem_uw = Rd_uw}},
|
2007-02-12 19:06:30 +01:00
|
|
|
{{
|
|
|
|
uint32_t tmp = mem_data;
|
2011-09-27 08:48:54 +02:00
|
|
|
Rd_uw = tmp;
|
2007-02-12 19:06:30 +01:00
|
|
|
}}, MEM_SWAP);
|
2006-12-05 01:55:52 +01:00
|
|
|
format LoadAlt {
|
2011-09-27 08:48:54 +02:00
|
|
|
0x10: lduwa({{Rd = Mem_uw;}});
|
|
|
|
0x11: lduba({{Rd = Mem_ub;}});
|
|
|
|
0x12: lduha({{Rd = Mem_uhw;}});
|
2006-12-18 09:37:52 +01:00
|
|
|
0x13: decode EXT_ASI {
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_LDTD_AIUP
|
2007-01-23 03:55:43 +01:00
|
|
|
0x22: TwinLoad::ldtx_aiup(
|
2011-09-27 08:48:54 +02:00
|
|
|
{{RdLow_udw = (Mem_tudw).a;
|
|
|
|
RdHigh_udw = (Mem_tudw).b;}});
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_LDTD_AIUS
|
2007-01-23 03:55:43 +01:00
|
|
|
0x23: TwinLoad::ldtx_aius(
|
2011-09-27 08:48:54 +02:00
|
|
|
{{RdLow_udw = (Mem_tudw).a;
|
|
|
|
RdHigh_udw = (Mem_tudw).b;}});
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_QUAD_LDD
|
2006-12-18 09:37:52 +01:00
|
|
|
0x24: TwinLoad::ldtx_quad_ldd(
|
2011-09-27 08:48:54 +02:00
|
|
|
{{RdLow_udw = (Mem_tudw).a;
|
|
|
|
RdHigh_udw = (Mem_tudw).b;}});
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_LDTX_REAL
|
2006-12-18 09:37:52 +01:00
|
|
|
0x26: TwinLoad::ldtx_real(
|
2011-09-27 08:48:54 +02:00
|
|
|
{{RdLow_udw = (Mem_tudw).a;
|
|
|
|
RdHigh_udw = (Mem_tudw).b;}});
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_LDTX_N
|
2007-02-12 19:06:30 +01:00
|
|
|
0x27: TwinLoad::ldtx_n(
|
2011-09-27 08:48:54 +02:00
|
|
|
{{RdLow_udw = (Mem_tudw).a;
|
|
|
|
RdHigh_udw = (Mem_tudw).b;}});
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_LDTX_AIUP_L
|
2007-02-12 19:06:30 +01:00
|
|
|
0x2A: TwinLoad::ldtx_aiup_l(
|
2011-09-27 08:48:54 +02:00
|
|
|
{{RdLow_udw = (Mem_tudw).a;
|
|
|
|
RdHigh_udw = (Mem_tudw).b;}});
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_LDTX_AIUS_L
|
2007-02-12 19:06:30 +01:00
|
|
|
0x2B: TwinLoad::ldtx_aius_l(
|
2011-09-27 08:48:54 +02:00
|
|
|
{{RdLow_udw = (Mem_tudw).a;
|
|
|
|
RdHigh_udw = (Mem_tudw).b;}});
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_LDTX_L
|
2007-02-12 19:06:30 +01:00
|
|
|
0x2C: TwinLoad::ldtx_l(
|
2011-09-27 08:48:54 +02:00
|
|
|
{{RdLow_udw = (Mem_tudw).a;
|
|
|
|
RdHigh_udw = (Mem_tudw).b;}});
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_LDTX_REAL_L
|
2006-12-18 09:37:52 +01:00
|
|
|
0x2E: TwinLoad::ldtx_real_l(
|
2011-09-27 08:48:54 +02:00
|
|
|
{{RdLow_udw = (Mem_tudw).a;
|
|
|
|
RdHigh_udw = (Mem_tudw).b;}});
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_LDTX_N_L
|
2006-12-18 09:37:52 +01:00
|
|
|
0x2F: TwinLoad::ldtx_n_l(
|
2011-09-27 08:48:54 +02:00
|
|
|
{{RdLow_udw = (Mem_tudw).a;
|
|
|
|
RdHigh_udw = (Mem_tudw).b;}});
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_LDTX_P
|
2007-01-17 01:06:05 +01:00
|
|
|
0xE2: TwinLoad::ldtx_p(
|
2011-09-27 08:48:54 +02:00
|
|
|
{{RdLow_udw = (Mem_tudw).a;
|
|
|
|
RdHigh_udw = (Mem_tudw).b;}});
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_LDTX_S
|
2007-01-23 03:55:43 +01:00
|
|
|
0xE3: TwinLoad::ldtx_s(
|
2011-09-27 08:48:54 +02:00
|
|
|
{{RdLow_udw = (Mem_tudw).a;
|
|
|
|
RdHigh_udw = (Mem_tudw).b;}});
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_LDTX_PL
|
2007-02-12 19:06:30 +01:00
|
|
|
0xEA: TwinLoad::ldtx_pl(
|
2011-09-27 08:48:54 +02:00
|
|
|
{{RdLow_udw = (Mem_tudw).a;
|
|
|
|
RdHigh_udw = (Mem_tudw).b;}});
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_LDTX_SL
|
2007-02-12 19:06:30 +01:00
|
|
|
0xEB: TwinLoad::ldtx_sl(
|
2011-09-27 08:48:54 +02:00
|
|
|
{{RdLow_udw = (Mem_tudw).a;
|
|
|
|
RdHigh_udw = (Mem_tudw).b;}});
|
2006-12-18 09:37:52 +01:00
|
|
|
default: ldtwa({{
|
2011-09-27 08:48:54 +02:00
|
|
|
RdLow = (Mem_tuw).a;
|
|
|
|
RdHigh = (Mem_tuw).b;}});
|
2006-12-18 09:37:52 +01:00
|
|
|
}
|
2006-04-06 20:52:44 +02:00
|
|
|
}
|
2006-12-05 01:55:52 +01:00
|
|
|
format StoreAlt {
|
2011-09-27 08:48:54 +02:00
|
|
|
0x14: stwa({{Mem_uw = Rd;}});
|
|
|
|
0x15: stba({{Mem_ub = Rd;}});
|
|
|
|
0x16: stha({{Mem_uhw = Rd;}});
|
2007-03-11 23:12:33 +01:00
|
|
|
0x17: sttwa({{
|
2010-11-11 11:03:58 +01:00
|
|
|
// This temporary needs to be here so that the parser
|
|
|
|
// will correctly identify this instruction as a store.
|
|
|
|
// It's probably either the parenthesis or referencing
|
|
|
|
// the member variable that throws confuses it.
|
2007-03-18 02:23:03 +01:00
|
|
|
Twin32_t temp;
|
|
|
|
temp.a = RdLow<31:0>;
|
|
|
|
temp.b = RdHigh<31:0>;
|
2011-09-27 08:48:54 +02:00
|
|
|
Mem_tuw = temp;
|
2007-09-26 05:11:03 +02:00
|
|
|
}});
|
2006-04-06 20:52:44 +02:00
|
|
|
}
|
2006-12-05 01:55:52 +01:00
|
|
|
format LoadAlt {
|
2011-09-27 08:48:54 +02:00
|
|
|
0x18: ldswa({{Rd = Mem_sw;}});
|
|
|
|
0x19: ldsba({{Rd = Mem_sb;}});
|
|
|
|
0x1A: ldsha({{Rd = Mem_shw;}});
|
|
|
|
0x1B: ldxa({{Rd = Mem_sdw;}});
|
2006-04-06 20:52:44 +02:00
|
|
|
}
|
2011-09-27 08:48:54 +02:00
|
|
|
0x1D: SwapAlt::ldstuba({{Mem_ub = 0xFF;}},
|
2007-02-12 19:06:30 +01:00
|
|
|
{{
|
|
|
|
uint8_t tmp = mem_data;
|
2011-09-27 08:48:54 +02:00
|
|
|
Rd_ub = tmp;
|
2007-09-26 05:11:03 +02:00
|
|
|
}}, MEM_SWAP);
|
2011-09-27 08:48:54 +02:00
|
|
|
0x1E: StoreAlt::stxa({{Mem_udw = Rd}});
|
|
|
|
0x1F: SwapAlt::swapa({{Mem_uw = Rd_uw}},
|
2007-02-12 19:06:30 +01:00
|
|
|
{{
|
|
|
|
uint32_t tmp = mem_data;
|
2011-09-27 08:48:54 +02:00
|
|
|
Rd_uw = tmp;
|
2007-09-26 05:11:03 +02:00
|
|
|
}}, MEM_SWAP);
|
2007-02-12 19:06:30 +01:00
|
|
|
|
2006-04-06 20:52:44 +02:00
|
|
|
format Trap {
|
2011-09-27 08:48:54 +02:00
|
|
|
0x20: Load::ldf({{Frds_uw = Mem_uw;}});
|
2007-02-03 00:04:42 +01:00
|
|
|
0x21: decode RD {
|
2007-02-06 21:52:33 +01:00
|
|
|
0x0: Load::ldfsr({{fault = checkFpEnableFault(xc);
|
|
|
|
if (fault)
|
|
|
|
return fault;
|
2011-09-27 08:48:54 +02:00
|
|
|
Fsr = Mem_uw | Fsr<63:32>;}});
|
2007-02-06 21:52:33 +01:00
|
|
|
0x1: Load::ldxfsr({{fault = checkFpEnableFault(xc);
|
|
|
|
if (fault)
|
|
|
|
return fault;
|
2011-09-27 08:48:54 +02:00
|
|
|
Fsr = Mem_udw;}});
|
2007-02-03 00:04:42 +01:00
|
|
|
default: FailUnimpl::ldfsrOther();
|
2006-04-06 20:52:44 +02:00
|
|
|
}
|
2014-10-16 11:49:51 +02:00
|
|
|
0x22: ldqf({{fault = std::make_shared<FpDisabled>();}});
|
2011-09-27 08:48:54 +02:00
|
|
|
0x23: Load::lddf({{Frd_udw = Mem_udw;}});
|
|
|
|
0x24: Store::stf({{Mem_uw = Frds_uw;}});
|
2007-02-03 00:04:42 +01:00
|
|
|
0x25: decode RD {
|
2009-02-25 19:16:04 +01:00
|
|
|
0x0: StoreFsr::stfsr({{fault = checkFpEnableFault(xc);
|
|
|
|
if (fault)
|
|
|
|
return fault;
|
2011-09-27 08:48:54 +02:00
|
|
|
Mem_uw = Fsr<31:0>;}});
|
2009-02-25 19:16:04 +01:00
|
|
|
0x1: StoreFsr::stxfsr({{fault = checkFpEnableFault(xc);
|
|
|
|
if (fault)
|
|
|
|
return fault;
|
2011-09-27 08:48:54 +02:00
|
|
|
Mem_udw = Fsr;}});
|
2007-02-03 00:04:42 +01:00
|
|
|
default: FailUnimpl::stfsrOther();
|
2006-03-16 19:58:50 +01:00
|
|
|
}
|
2014-10-16 11:49:51 +02:00
|
|
|
0x26: stqf({{fault = std::make_shared<FpDisabled>();}});
|
2011-09-27 08:48:54 +02:00
|
|
|
0x27: Store::stdf({{Mem_udw = Frd_udw;}});
|
2006-04-06 20:52:44 +02:00
|
|
|
0x2D: Nop::prefetch({{ }});
|
2011-09-27 08:48:54 +02:00
|
|
|
0x30: LoadAlt::ldfa({{Frds_uw = Mem_uw;}});
|
2014-10-16 11:49:51 +02:00
|
|
|
0x32: ldqfa({{fault = std::make_shared<FpDisabled>();}});
|
2006-10-12 23:38:06 +02:00
|
|
|
format LoadAlt {
|
|
|
|
0x33: decode EXT_ASI {
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_NUCLEUS
|
2006-10-12 23:38:06 +02:00
|
|
|
0x04: FailUnimpl::lddfa_n();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_NUCLEUS_LITTLE
|
2006-10-12 23:38:06 +02:00
|
|
|
0x0C: FailUnimpl::lddfa_nl();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_AS_IF_USER_PRIMARY
|
2006-10-12 23:38:06 +02:00
|
|
|
0x10: FailUnimpl::lddfa_aiup();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_AS_IF_USER_PRIMARY_LITTLE
|
2006-10-12 23:38:06 +02:00
|
|
|
0x18: FailUnimpl::lddfa_aiupl();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_AS_IF_USER_SECONDARY
|
2006-10-12 23:38:06 +02:00
|
|
|
0x11: FailUnimpl::lddfa_aius();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_AS_IF_USER_SECONDARY_LITTLE
|
2006-10-12 23:38:06 +02:00
|
|
|
0x19: FailUnimpl::lddfa_aiusl();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_REAL
|
2006-10-12 23:38:06 +02:00
|
|
|
0x14: FailUnimpl::lddfa_real();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_REAL_LITTLE
|
2006-10-12 23:38:06 +02:00
|
|
|
0x1C: FailUnimpl::lddfa_real_l();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_REAL_IO
|
2006-10-12 23:38:06 +02:00
|
|
|
0x15: FailUnimpl::lddfa_real_io();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_REAL_IO_LITTLE
|
2006-10-12 23:38:06 +02:00
|
|
|
0x1D: FailUnimpl::lddfa_real_io_l();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_PRIMARY
|
2006-10-12 23:38:06 +02:00
|
|
|
0x80: FailUnimpl::lddfa_p();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_PRIMARY_LITTLE
|
2006-10-12 23:38:06 +02:00
|
|
|
0x88: FailUnimpl::lddfa_pl();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_SECONDARY
|
2006-10-12 23:38:06 +02:00
|
|
|
0x81: FailUnimpl::lddfa_s();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_SECONDARY_LITTLE
|
2006-10-12 23:38:06 +02:00
|
|
|
0x89: FailUnimpl::lddfa_sl();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_PRIMARY_NO_FAULT
|
2006-10-12 23:38:06 +02:00
|
|
|
0x82: FailUnimpl::lddfa_pnf();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_PRIMARY_NO_FAULT_LITTLE
|
2006-10-12 23:38:06 +02:00
|
|
|
0x8A: FailUnimpl::lddfa_pnfl();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_SECONDARY_NO_FAULT
|
2006-10-12 23:38:06 +02:00
|
|
|
0x83: FailUnimpl::lddfa_snf();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_SECONDARY_NO_FAULT_LITTLE
|
2006-10-12 23:38:06 +02:00
|
|
|
0x8B: FailUnimpl::lddfa_snfl();
|
|
|
|
|
|
|
|
format BlockLoad {
|
|
|
|
// LDBLOCKF
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_BLOCK_AS_IF_USER_PRIMARY
|
2006-10-12 23:38:06 +02:00
|
|
|
0x16: FailUnimpl::ldblockf_aiup();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_BLOCK_AS_IF_USER_SECONDARY
|
2006-10-12 23:38:06 +02:00
|
|
|
0x17: FailUnimpl::ldblockf_aius();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
|
2006-10-12 23:38:06 +02:00
|
|
|
0x1E: FailUnimpl::ldblockf_aiupl();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
|
2006-10-12 23:38:06 +02:00
|
|
|
0x1F: FailUnimpl::ldblockf_aiusl();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_BLOCK_PRIMARY
|
2011-09-27 08:48:54 +02:00
|
|
|
0xF0: ldblockf_p({{Frd_N_udw = Mem_udw;}});
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_BLOCK_SECONDARY
|
2006-10-12 23:38:06 +02:00
|
|
|
0xF1: FailUnimpl::ldblockf_s();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_BLOCK_PRIMARY_LITTLE
|
2006-10-12 23:38:06 +02:00
|
|
|
0xF8: FailUnimpl::ldblockf_pl();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_BLOCK_SECONDARY_LITTLE
|
2006-10-12 23:38:06 +02:00
|
|
|
0xF9: FailUnimpl::ldblockf_sl();
|
|
|
|
}
|
|
|
|
|
2010-11-11 11:03:58 +01:00
|
|
|
// LDSHORTF
|
|
|
|
// ASI_FL8_PRIMARY
|
2006-10-12 23:38:06 +02:00
|
|
|
0xD0: FailUnimpl::ldshortf_8p();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_FL8_SECONDARY
|
2006-10-12 23:38:06 +02:00
|
|
|
0xD1: FailUnimpl::ldshortf_8s();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_FL8_PRIMARY_LITTLE
|
2006-10-12 23:38:06 +02:00
|
|
|
0xD8: FailUnimpl::ldshortf_8pl();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_FL8_SECONDARY_LITTLE
|
2006-10-12 23:38:06 +02:00
|
|
|
0xD9: FailUnimpl::ldshortf_8sl();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_FL16_PRIMARY
|
2006-10-12 23:38:06 +02:00
|
|
|
0xD2: FailUnimpl::ldshortf_16p();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_FL16_SECONDARY
|
2006-10-12 23:38:06 +02:00
|
|
|
0xD3: FailUnimpl::ldshortf_16s();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_FL16_PRIMARY_LITTLE
|
2006-10-12 23:38:06 +02:00
|
|
|
0xDA: FailUnimpl::ldshortf_16pl();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_FL16_SECONDARY_LITTLE
|
2006-10-12 23:38:06 +02:00
|
|
|
0xDB: FailUnimpl::ldshortf_16sl();
|
2010-11-11 11:03:58 +01:00
|
|
|
// Not an ASI which is legal with lddfa
|
2006-10-19 02:44:51 +02:00
|
|
|
default: Trap::lddfa_bad_asi(
|
2014-10-16 11:49:51 +02:00
|
|
|
{{fault = std::make_shared<DataAccessException>();}});
|
2006-10-12 23:38:06 +02:00
|
|
|
}
|
|
|
|
}
|
2011-09-27 08:48:54 +02:00
|
|
|
0x34: Store::stfa({{Mem_uw = Frds_uw;}});
|
2014-10-16 11:49:51 +02:00
|
|
|
0x36: stqfa({{fault = std::make_shared<FpDisabled>();}});
|
2006-10-19 02:44:51 +02:00
|
|
|
format StoreAlt {
|
|
|
|
0x37: decode EXT_ASI {
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_NUCLEUS
|
2006-10-19 02:44:51 +02:00
|
|
|
0x04: FailUnimpl::stdfa_n();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_NUCLEUS_LITTLE
|
2006-10-19 02:44:51 +02:00
|
|
|
0x0C: FailUnimpl::stdfa_nl();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_AS_IF_USER_PRIMARY
|
2006-10-19 02:44:51 +02:00
|
|
|
0x10: FailUnimpl::stdfa_aiup();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_AS_IF_USER_PRIMARY_LITTLE
|
2006-10-19 02:44:51 +02:00
|
|
|
0x18: FailUnimpl::stdfa_aiupl();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_AS_IF_USER_SECONDARY
|
2006-10-19 02:44:51 +02:00
|
|
|
0x11: FailUnimpl::stdfa_aius();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_AS_IF_USER_SECONDARY_LITTLE
|
2006-10-19 02:44:51 +02:00
|
|
|
0x19: FailUnimpl::stdfa_aiusl();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_REAL
|
2006-10-19 02:44:51 +02:00
|
|
|
0x14: FailUnimpl::stdfa_real();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_REAL_LITTLE
|
2006-10-19 02:44:51 +02:00
|
|
|
0x1C: FailUnimpl::stdfa_real_l();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_REAL_IO
|
2006-10-19 02:44:51 +02:00
|
|
|
0x15: FailUnimpl::stdfa_real_io();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_REAL_IO_LITTLE
|
2006-10-19 02:44:51 +02:00
|
|
|
0x1D: FailUnimpl::stdfa_real_io_l();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_PRIMARY
|
2006-10-19 02:44:51 +02:00
|
|
|
0x80: FailUnimpl::stdfa_p();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_PRIMARY_LITTLE
|
2006-10-19 02:44:51 +02:00
|
|
|
0x88: FailUnimpl::stdfa_pl();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_SECONDARY
|
2006-10-19 02:44:51 +02:00
|
|
|
0x81: FailUnimpl::stdfa_s();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_SECONDARY_LITTLE
|
2006-10-19 02:44:51 +02:00
|
|
|
0x89: FailUnimpl::stdfa_sl();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_PRIMARY_NO_FAULT
|
2006-10-19 02:44:51 +02:00
|
|
|
0x82: FailUnimpl::stdfa_pnf();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_PRIMARY_NO_FAULT_LITTLE
|
2006-10-19 02:44:51 +02:00
|
|
|
0x8A: FailUnimpl::stdfa_pnfl();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_SECONDARY_NO_FAULT
|
2006-10-19 02:44:51 +02:00
|
|
|
0x83: FailUnimpl::stdfa_snf();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_SECONDARY_NO_FAULT_LITTLE
|
2006-10-19 02:44:51 +02:00
|
|
|
0x8B: FailUnimpl::stdfa_snfl();
|
|
|
|
|
|
|
|
format BlockStore {
|
|
|
|
// STBLOCKF
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_BLOCK_AS_IF_USER_PRIMARY
|
2006-10-19 02:44:51 +02:00
|
|
|
0x16: FailUnimpl::stblockf_aiup();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_BLOCK_AS_IF_USER_SECONDARY
|
2006-10-19 02:44:51 +02:00
|
|
|
0x17: FailUnimpl::stblockf_aius();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
|
2006-10-19 02:44:51 +02:00
|
|
|
0x1E: FailUnimpl::stblockf_aiupl();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
|
2006-10-19 02:44:51 +02:00
|
|
|
0x1F: FailUnimpl::stblockf_aiusl();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_BLOCK_PRIMARY
|
2011-09-27 08:48:54 +02:00
|
|
|
0xF0: stblockf_p({{Mem_udw = Frd_N_udw;}});
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_BLOCK_SECONDARY
|
2006-10-19 02:44:51 +02:00
|
|
|
0xF1: FailUnimpl::stblockf_s();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_BLOCK_PRIMARY_LITTLE
|
2006-10-19 02:44:51 +02:00
|
|
|
0xF8: FailUnimpl::stblockf_pl();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_BLOCK_SECONDARY_LITTLE
|
2006-10-19 02:44:51 +02:00
|
|
|
0xF9: FailUnimpl::stblockf_sl();
|
|
|
|
}
|
|
|
|
|
2010-11-11 11:03:58 +01:00
|
|
|
// STSHORTF
|
|
|
|
// ASI_FL8_PRIMARY
|
2006-10-19 02:44:51 +02:00
|
|
|
0xD0: FailUnimpl::stshortf_8p();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_FL8_SECONDARY
|
2006-10-19 02:44:51 +02:00
|
|
|
0xD1: FailUnimpl::stshortf_8s();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_FL8_PRIMARY_LITTLE
|
2006-10-19 02:44:51 +02:00
|
|
|
0xD8: FailUnimpl::stshortf_8pl();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_FL8_SECONDARY_LITTLE
|
2006-10-19 02:44:51 +02:00
|
|
|
0xD9: FailUnimpl::stshortf_8sl();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_FL16_PRIMARY
|
2006-10-19 02:44:51 +02:00
|
|
|
0xD2: FailUnimpl::stshortf_16p();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_FL16_SECONDARY
|
2006-10-19 02:44:51 +02:00
|
|
|
0xD3: FailUnimpl::stshortf_16s();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_FL16_PRIMARY_LITTLE
|
2006-10-19 02:44:51 +02:00
|
|
|
0xDA: FailUnimpl::stshortf_16pl();
|
2010-11-11 11:03:58 +01:00
|
|
|
// ASI_FL16_SECONDARY_LITTLE
|
2006-10-19 02:44:51 +02:00
|
|
|
0xDB: FailUnimpl::stshortf_16sl();
|
2010-11-11 11:03:58 +01:00
|
|
|
// Not an ASI which is legal with lddfa
|
2006-10-19 02:44:51 +02:00
|
|
|
default: Trap::stdfa_bad_asi(
|
2014-10-16 11:49:51 +02:00
|
|
|
{{fault = std::make_shared<DataAccessException>();}});
|
2006-10-19 02:44:51 +02:00
|
|
|
}
|
|
|
|
}
|
2007-02-12 19:06:30 +01:00
|
|
|
0x3C: CasAlt::casa({{
|
2011-09-27 08:48:54 +02:00
|
|
|
mem_data = htog(Rs2_uw);
|
|
|
|
Mem_uw = Rd_uw;}},
|
2007-02-12 19:06:30 +01:00
|
|
|
{{
|
|
|
|
uint32_t tmp = mem_data;
|
2011-09-27 08:48:54 +02:00
|
|
|
Rd_uw = tmp;
|
2007-09-26 05:11:03 +02:00
|
|
|
}}, MEM_SWAP_COND);
|
2006-04-06 20:52:44 +02:00
|
|
|
0x3D: Nop::prefetcha({{ }});
|
2007-02-12 19:06:30 +01:00
|
|
|
0x3E: CasAlt::casxa({{mem_data = gtoh(Rs2);
|
2011-09-27 08:48:54 +02:00
|
|
|
Mem_udw = Rd_udw; }},
|
|
|
|
{{ Rd_udw = mem_data; }}, MEM_SWAP_COND);
|
2006-04-06 20:52:44 +02:00
|
|
|
}
|
2006-03-16 19:58:50 +01:00
|
|
|
}
|
2006-01-29 23:25:54 +01:00
|
|
|
}
|