Got hello world to work!
arch/sparc/isa/decoder.isa:
Made sure if a register was assigned to along some control path, then all paths on which no exception would block commit set a value as well. Also, Rs1 is treated as signed for bpr instructions.
arch/sparc/isa/formats/integerop.isa:
Added an IntOpImm11 class which sign extends the SIMM11 immediate field.
arch/sparc/isa/formats/mem.isa:
Fixed how offsets are used, and how disassembly is generated.
arch/sparc/linux/process.cc:
Added fstat and exit_group syscalls.
--HG--
extra : convert_revision : 3b4427d239d254a92179a4137441125b8a364264
This commit is contained in:
Gabe Black
parent
6a2e0388cf
commit
a8fbc4ec76
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@ -38,37 +38,37 @@ decode OP default Unknown::unknown()
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format BranchSplit
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{
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0x1: bpreq({{
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if(Rs1 == 0)
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if(Rs1.sdw == 0)
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NNPC = xc->readPC() + disp;
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else
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handle_annul
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}});
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0x2: bprle({{
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if(Rs1 <= 0)
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if(Rs1.sdw <= 0)
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NNPC = xc->readPC() + disp;
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else
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handle_annul
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}});
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0x3: bprl({{
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if(Rs1 < 0)
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if(Rs1.sdw < 0)
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NNPC = xc->readPC() + disp;
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else
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handle_annul
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}});
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0x5: bprne({{
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if(Rs1 != 0)
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if(Rs1.sdw != 0)
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NNPC = xc->readPC() + disp;
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else
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handle_annul
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}});
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0x6: bprg({{
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if(Rs1 > 0)
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if(Rs1.sdw > 0)
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NNPC = xc->readPC() + disp;
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else
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handle_annul
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}});
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0x7: bprge({{
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if(Rs1 >= 0)
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if(Rs1.sdw >= 0)
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NNPC = xc->readPC() + disp;
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else
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handle_annul
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@ -350,11 +350,15 @@ decode OP default Unknown::unknown()
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{
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0x0: movcci({{
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if(passesCondition(CcrIcc, COND4))
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Rd = (I ? SIMM11 : RS2);
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Rd = Rs2_or_imm11;
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else
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Rd = Rd;
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}});
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0x2: movccx({{
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if(passesCondition(CcrXcc, COND4))
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Rd = (I ? SIMM11 : RS2);
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Rd = Rs2_or_imm11;
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else
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Rd = Rd;
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}});
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}
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}
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@ -373,16 +377,17 @@ decode OP default Unknown::unknown()
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count += oneBits[temp & 0xF];
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temp = temp >> 4;
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}
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Rd = count;
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}});
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}
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0x2F: decode RCOND3
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{
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0x1: movreq({{if(Rs1 == 0) Rd = Rs2_or_imm10;}});
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0x2: movrle({{if(Rs1 <= 0) Rd = Rs2_or_imm10;}});
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0x3: movrl({{if(Rs1 < 0) Rd = Rs2_or_imm10;}});
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0x5: movrne({{if(Rs1 != 0) Rd = Rs2_or_imm10;}});
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0x6: movrg({{if(Rs1 > 0) Rd = Rs2_or_imm10;}});
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0x7: movrge({{if(Rs1 >= 0) Rd = Rs2_or_imm10;}});
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0x1: movreq({{Rd = (Rs1 == 0) ? Rs2_or_imm10 : Rd;}});
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0x2: movrle({{Rd = (Rs1 <= 0) ? Rs2_or_imm10 : Rd;}});
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0x3: movrl({{Rd = (Rs1 < 0) ? Rs2_or_imm10 : Rd;}});
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0x5: movrne({{Rd = (Rs1 != 0) ? Rs2_or_imm10 : Rd;}});
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0x6: movrg({{Rd = (Rs1 > 0) ? Rs2_or_imm10 : Rd;}});
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0x7: movrge({{Rd = (Rs1 >= 0) ? Rs2_or_imm10 : Rd;}});
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}
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0x30: decode RD {
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0x0: wry({{Y = Rs1 ^ Rs2_or_imm13;}});
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@ -61,6 +61,21 @@ output header {{
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}
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};
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/**
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* Base class for 11 bit immediate integer operations.
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*/
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class IntOpImm11 : public IntOpImm
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{
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protected:
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// Constructor
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IntOpImm11(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass) :
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IntOpImm(mnem, _machInst, __opClass)
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{
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imm = sign_ext(SIMM11, 11);
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}
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};
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/**
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* Base class for 13 bit immediate integer operations.
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*/
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@ -30,8 +30,9 @@ output header {{
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// Constructor
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MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
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Mem(mnem, _machInst, __opClass), imm(SIMM13)
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Mem(mnem, _machInst, __opClass)
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{
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imm = sign_ext(SIMM13, 13);
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}
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std::string generateDisassembly(Addr pc,
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@ -84,7 +85,10 @@ output decoder {{
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}
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ccprintf(response, "[ ");
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printReg(response, _srcRegIdx[!save ? 0 : 1]);
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ccprintf(response, " + 0x%x ]", imm);
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if(imm >= 0)
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ccprintf(response, " + 0x%x ]", imm);
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else
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ccprintf(response, " + -0x%x ]", -imm);
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if(load)
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{
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ccprintf(response, ", ");
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@ -127,7 +131,7 @@ let {{
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def doMemFormat(code, load, store, name, Name, opt_flags):
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addrCalcReg = 'EA = Rs1 + Rs2;'
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addrCalcImm = 'EA = Rs1 + SIMM13;'
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addrCalcImm = 'EA = Rs1 + imm;'
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iop = InstObjParams(name, Name, 'Mem', code,
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opt_flags, ("ea_code", addrCalcReg),
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("load", load), ("store", store))
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@ -155,7 +155,7 @@ SyscallDesc SparcLinuxProcess::syscallDescs[] = {
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/* 59 */ SyscallDesc("execve", unimplementedFunc),
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/* 60 */ SyscallDesc("umask", unimplementedFunc),
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/* 61 */ SyscallDesc("chroot", unimplementedFunc),
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/* 62 */ SyscallDesc("fstat", unimplementedFunc),
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/* 62 */ SyscallDesc("fstat", fstatFunc<SparcLinux>),
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/* 63 */ SyscallDesc("fstat64", unimplementedFunc),
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/* 64 */ SyscallDesc("getpagesize", unimplementedFunc),
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/* 65 */ SyscallDesc("msync", unimplementedFunc),
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@ -281,7 +281,7 @@ SyscallDesc SparcLinuxProcess::syscallDescs[] = {
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/* 185 */ SyscallDesc("setpgid", unimplementedFunc),
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/* 186 */ SyscallDesc("fremovexattr", unimplementedFunc),
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/* 187 */ SyscallDesc("tkill", unimplementedFunc),
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/* 188 */ SyscallDesc("exit_group", unimplementedFunc),
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/* 188 */ SyscallDesc("exit_group", exitFunc),
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/* 189 */ SyscallDesc("uname", unameFunc),
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/* 190 */ SyscallDesc("init_module", unimplementedFunc),
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/* 191 */ SyscallDesc("personality", unimplementedFunc),
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