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gem5/src/cpu
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Andreas Sandberg abe7ef95cb sim: Remove redundant export_method_cxx_predecls 
The headers declared in export_method_cxx_predecls are redundant since a
SimObject's main header is automatically included.

Change-Id: Ied9e84630b36960e54efe91d16f8c66fba7e0da0
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Joe Gross <joseph.gross@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-01-03 12:03:06 +00:00
..
checker cpu, arch: fix the type used for the request flags 2016-08-15 12:00:35 +01:00
kvm sim: Remove redundant export_method_cxx_predecls 2017-01-03 12:03:06 +00:00
minor cpu: disallow speculative update of branch predictor tables (o3) 2016-12-21 15:07:16 -06:00
nocpu arch, cpu: Factor out the ExecContext into a proper base class 2014-09-03 07:42:22 -04:00
o3 cpu: Resolve targets of predicted 'taken' decode for O3 2016-12-21 15:05:24 -06:00
pred cpu: implement an L-TAGE branch predictor 2016-12-21 15:25:13 -06:00
simple cpu, arch: fix the type used for the request flags 2016-08-15 12:00:35 +01:00
testers cpu: Change traffic generators to use different values for writes 2016-12-05 16:48:20 -05:00
trace cpu: Support exit when any one Trace CPU completes replay 2016-09-15 18:01:20 +01:00
activity.cc Fix: Address a few benign memory leaks 2012-07-09 12:35:30 -04:00
activity.hh cpu: Useful getters for ActivityRecorder 2014-05-09 18:58:48 -04:00
base.cc pwr: Low-power idle power state for idle CPUs 2016-06-06 17:16:43 +01:00
base.hh pwr: Low-power idle power state for idle CPUs 2016-06-06 17:16:43 +01:00
base_dyn_inst.hh cpu, arch: fix the type used for the request flags 2016-08-15 12:00:35 +01:00
base_dyn_inst_impl.hh cpu, o3: consider split requests for LSQ checksnoop operations 2015-09-15 08:14:06 -05:00
BaseCPU.py arch: [Patch 1/5] Added RISC-V base instruction set RV64I 2016-11-30 17:10:28 -05:00
CheckerCPU.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
cpuevent.cc
cpuevent.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
CPUTracers.py cpu: Put all CPU instruction tracers in a single file 2015-01-25 07:22:17 -05:00
decode_cache.hh misc: Remove redundant compiler-specific defines 2015-10-12 04:07:59 -04:00
dummy_checker.cc isa,cpu: Add support for FS SMT Interrupts 2015-09-30 11:14:19 -05:00
dummy_checker.hh cpu: Add header files for checker CPUs 2012-11-02 11:32:01 -05:00
DummyChecker.py cpu: Make checker CPUs inherit from CheckerCPU in the Python hierarchy 2013-02-15 17:40:08 -05:00
exec_context.cc arch, cpu: Factor out the ExecContext into a proper base class 2014-09-03 07:42:22 -04:00
exec_context.hh cpu, arch: fix the type used for the request flags 2016-08-15 12:00:35 +01:00
exetrace.cc sim: Clean up InstRecord 2015-01-25 07:22:44 -05:00
exetrace.hh base: remove Trace::enabled flag 2015-09-30 15:21:55 -05:00
func_unit.cc cpu: Fix issue identified by UBSan 2015-07-30 03:41:22 -04:00
func_unit.hh cpu: Fix issue identified by UBSan 2015-07-30 03:41:22 -04:00
FuncUnit.py cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass 2016-10-15 14:58:45 -05:00
inst_pb_trace.cc base: remove Trace::enabled flag 2015-09-30 15:21:55 -05:00
inst_pb_trace.hh misc: Remove redundant compiler-specific defines 2015-10-12 04:07:59 -04:00
inst_seq.hh build: fix compile problems pointed out by gcc 4.4 2009-11-04 16:57:01 -08:00
InstPBTrace.py cpu: add support for outputing a protobuf formatted CPU trace 2015-02-16 03:32:38 -05:00
inteltrace.cc gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
inteltrace.hh base: remove Trace::enabled flag 2015-09-30 15:21:55 -05:00
intr_control.cc isa,cpu: Add support for FS SMT Interrupts 2015-09-30 11:14:19 -05:00
intr_control.hh arch: Header clean up for NOISA resurrection 2013-09-04 13:22:55 -04:00
intr_control_noisa.cc arch: Resurrect the NOISA build target and rename it NULL 2013-09-04 13:22:57 -04:00
IntrControl.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
nativetrace.cc style: fix missing spaces in control statements 2016-02-06 17:21:19 -08:00
nativetrace.hh style: fix missing spaces in control statements 2016-02-06 17:21:19 -08:00
op_class.hh cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass 2016-10-15 14:58:45 -05:00
pc_event.cc arm: Enable support for triggering a sim panic on kernel panics 2013-04-22 13:20:31 -04:00
pc_event.hh arm: Enable support for triggering a sim panic on kernel panics 2013-04-22 13:20:31 -04:00
profile.cc includes: sort all includes 2011-04-15 10:44:06 -07:00
profile.hh arch: Use const StaticInstPtr references where possible 2014-09-27 09:08:36 -04:00
quiesce_event.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
quiesce_event.hh clang: Enable compiling gem5 using clang 2.9 and 3.0 2012-01-31 12:05:52 -05:00
reg_class.cc revert 5af8f40d8f2c 2015-07-28 01:58:04 -05:00
reg_class.hh revert 5af8f40d8f2c 2015-07-28 01:58:04 -05:00
SConscript sim: add ExecMacro to Exec* compound debug flags 2015-10-06 17:26:50 -07:00
simple_thread.cc sim: Refactor quiesce and remove FS asserts 2016-09-13 23:17:42 -04:00
simple_thread.hh misc: Remove redundant compiler-specific defines 2015-10-12 04:07:59 -04:00
smt.hh includes: fix up code after sorting 2011-04-15 10:44:14 -07:00
static_inst.cc cpu: Add flag name printing to StaticInst 2014-05-09 18:58:47 -04:00
static_inst.hh revert 5af8f40d8f2c 2015-07-28 01:58:04 -05:00
static_inst_fwd.hh cpu: Don't forward declare RefCountingPtr 2014-08-13 06:57:26 -04:00
StaticInstFlags.py revert 5af8f40d8f2c 2015-07-28 01:58:04 -05:00
thread_context.cc sim: Refactor quiesce and remove FS asserts 2016-09-13 23:17:42 -04:00
thread_context.hh sim: Refactor quiesce and remove FS asserts 2016-09-13 23:17:42 -04:00
thread_state.cc sim: Refactor the serialization base class 2015-07-07 09:51:03 +01:00
thread_state.hh misc: Remove redundant compiler-specific defines 2015-10-12 04:07:59 -04:00
timebuf.hh style: remove trailing whitespace 2016-02-06 17:21:18 -08:00
timing_expr.cc arch: Use const StaticInstPtr references where possible 2014-09-27 09:08:36 -04:00
timing_expr.hh arch: Use const StaticInstPtr references where possible 2014-09-27 09:08:36 -04:00
TimingExpr.py cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
translation.hh mem, cpu: Add a separate flag for strictly ordered memory 2015-05-05 03:22:33 -04:00