cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass
Modify the opClass assigned to AArch64 FP instructions from SimdFloat* to Float*. Also create the FloatMemRead and FloatMemWrite opClasses, which distinguishes writes to the INT and FP register banks. Change the latency of (Simd)FloatMultAcc to 5, based on the Cortex-A72, where the "latency" of FMADD is 3 if the next instruction is a FMADD and has only the augend to destination dependency, otherwise it's 7 cycles. Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
This commit is contained in:
Fernando Endo
parent
2f5262eb67
commit
6c72c35519
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@ -62,24 +62,28 @@ class O3_ARM_v7a_FP(FUDesc):
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OpDesc(opClass='SimdFloatDiv', opLat=3),
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OpDesc(opClass='SimdFloatMisc', opLat=3),
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OpDesc(opClass='SimdFloatMult', opLat=3),
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OpDesc(opClass='SimdFloatMultAcc',opLat=1),
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OpDesc(opClass='SimdFloatMultAcc',opLat=5),
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OpDesc(opClass='SimdFloatSqrt', opLat=9),
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OpDesc(opClass='FloatAdd', opLat=5),
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OpDesc(opClass='FloatCmp', opLat=5),
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OpDesc(opClass='FloatCvt', opLat=5),
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OpDesc(opClass='FloatDiv', opLat=9, pipelined=False),
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OpDesc(opClass='FloatSqrt', opLat=33, pipelined=False),
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OpDesc(opClass='FloatMult', opLat=4) ]
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OpDesc(opClass='FloatMult', opLat=4),
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OpDesc(opClass='FloatMultAcc', opLat=5),
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OpDesc(opClass='FloatMisc', opLat=3) ]
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count = 2
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# Load/Store Units
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class O3_ARM_v7a_Load(FUDesc):
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opList = [ OpDesc(opClass='MemRead',opLat=2) ]
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opList = [ OpDesc(opClass='MemRead',opLat=2),
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OpDesc(opClass='FloatMemRead',opLat=2) ]
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count = 1
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class O3_ARM_v7a_Store(FUDesc):
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opList = [OpDesc(opClass='MemWrite',opLat=2) ]
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opList = [ OpDesc(opClass='MemWrite',opLat=2),
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OpDesc(opClass='FloatMemWrite',opLat=2) ]
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count = 1
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# Functional Units for this CPU
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@ -52,7 +52,7 @@ let {{
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'''
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fmovImmSIop = InstObjParams("fmov", "FmovImmS", "FpRegImmOp",
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{ "code": fmovImmSCode,
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"op_class": "SimdFloatMiscOp" }, [])
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"op_class": "FloatMiscOp" }, [])
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header_output += FpRegImmOpDeclare.subst(fmovImmSIop);
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decoder_output += FpRegImmOpConstructor.subst(fmovImmSIop);
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exec_output += BasicExecute.subst(fmovImmSIop);
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@ -65,7 +65,7 @@ let {{
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'''
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fmovImmDIop = InstObjParams("fmov", "FmovImmD", "FpRegImmOp",
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{ "code": fmovImmDCode,
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"op_class": "SimdFloatMiscOp" }, [])
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"op_class": "FloatMiscOp" }, [])
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header_output += FpRegImmOpDeclare.subst(fmovImmDIop);
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decoder_output += AA64FpRegImmOpConstructor.subst(fmovImmDIop);
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exec_output += BasicExecute.subst(fmovImmDIop);
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@ -78,7 +78,7 @@ let {{
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'''
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fmovRegSIop = InstObjParams("fmov", "FmovRegS", "FpRegRegOp",
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{ "code": fmovRegSCode,
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"op_class": "SimdFloatMiscOp" }, [])
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"op_class": "FloatMiscOp" }, [])
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header_output += FpRegRegOpDeclare.subst(fmovRegSIop);
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decoder_output += AA64FpRegRegOpConstructor.subst(fmovRegSIop);
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exec_output += BasicExecute.subst(fmovRegSIop);
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@ -91,7 +91,7 @@ let {{
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'''
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fmovRegDIop = InstObjParams("fmov", "FmovRegD", "FpRegRegOp",
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{ "code": fmovRegDCode,
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"op_class": "SimdFloatMiscOp" }, [])
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"op_class": "FloatMiscOp" }, [])
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header_output += FpRegRegOpDeclare.subst(fmovRegDIop);
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decoder_output += AA64FpRegRegOpConstructor.subst(fmovRegDIop);
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exec_output += BasicExecute.subst(fmovRegDIop);
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@ -104,7 +104,7 @@ let {{
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'''
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fmovCoreRegWIop = InstObjParams("fmov", "FmovCoreRegW", "FpRegRegOp",
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{ "code": fmovCoreRegWCode,
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"op_class": "SimdFloatMiscOp" }, [])
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"op_class": "FloatMiscOp" }, [])
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header_output += FpRegRegOpDeclare.subst(fmovCoreRegWIop);
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decoder_output += AA64FpRegRegOpConstructor.subst(fmovCoreRegWIop);
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exec_output += BasicExecute.subst(fmovCoreRegWIop);
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@ -117,7 +117,7 @@ let {{
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'''
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fmovCoreRegXIop = InstObjParams("fmov", "FmovCoreRegX", "FpRegRegOp",
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{ "code": fmovCoreRegXCode,
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"op_class": "SimdFloatMiscOp" }, [])
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"op_class": "FloatMiscOp" }, [])
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header_output += FpRegRegOpDeclare.subst(fmovCoreRegXIop);
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decoder_output += AA64FpRegRegOpConstructor.subst(fmovCoreRegXIop);
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exec_output += BasicExecute.subst(fmovCoreRegXIop);
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@ -128,7 +128,7 @@ let {{
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'''
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fmovUCoreRegXIop = InstObjParams("fmov", "FmovUCoreRegX", "FpRegRegOp",
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{ "code": fmovUCoreRegXCode,
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"op_class": "SimdFloatMiscOp" }, [])
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"op_class": "FloatMiscOp" }, [])
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header_output += FpRegRegOpDeclare.subst(fmovUCoreRegXIop);
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decoder_output += AA64FpRegRegOpConstructor.subst(fmovUCoreRegXIop);
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exec_output += BasicExecute.subst(fmovUCoreRegXIop);
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@ -138,7 +138,7 @@ let {{
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'''
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fmovRegCoreWIop = InstObjParams("fmov", "FmovRegCoreW", "FpRegRegOp",
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{ "code": fmovRegCoreWCode,
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"op_class": "SimdFloatMiscOp" }, [])
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"op_class": "FloatMiscOp" }, [])
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header_output += FpRegRegOpDeclare.subst(fmovRegCoreWIop);
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decoder_output += AA64FpRegRegOpConstructor.subst(fmovRegCoreWIop);
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exec_output += BasicExecute.subst(fmovRegCoreWIop);
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@ -148,7 +148,7 @@ let {{
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'''
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fmovRegCoreXIop = InstObjParams("fmov", "FmovRegCoreX", "FpRegRegOp",
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{ "code": fmovRegCoreXCode,
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"op_class": "SimdFloatMiscOp" }, [])
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"op_class": "FloatMiscOp" }, [])
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header_output += FpRegRegOpDeclare.subst(fmovRegCoreXIop);
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decoder_output += AA64FpRegRegOpConstructor.subst(fmovRegCoreXIop);
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exec_output += BasicExecute.subst(fmovRegCoreXIop);
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@ -158,7 +158,7 @@ let {{
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'''
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fmovURegCoreXIop = InstObjParams("fmov", "FmovURegCoreX", "FpRegRegOp",
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{ "code": fmovURegCoreXCode,
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"op_class": "SimdFloatMiscOp" }, [])
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"op_class": "FloatMiscOp" }, [])
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header_output += FpRegRegOpDeclare.subst(fmovURegCoreXIop);
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decoder_output += AA64FpRegRegOpConstructor.subst(fmovURegCoreXIop);
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exec_output += BasicExecute.subst(fmovURegCoreXIop);
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@ -270,16 +270,16 @@ let {{
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decoder_output += AA64FpRegRegRegRegOpConstructor.subst(iop)
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exec_output += BasicExecute.subst(iop)
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buildTernaryFpOp("FMAdd", "SimdFloatMultAccOp",
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buildTernaryFpOp("FMAdd", "FloatMultAccOp",
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"fplibMulAdd<uint32_t>(cOp3, cOp1, cOp2, fpscr)",
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"fplibMulAdd<uint64_t>(cOp3, cOp1, cOp2, fpscr)" )
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buildTernaryFpOp("FMSub", "SimdFloatMultAccOp",
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buildTernaryFpOp("FMSub", "FloatMultAccOp",
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"fplibMulAdd<uint32_t>(cOp3, fplibNeg<uint32_t>(cOp1), cOp2, fpscr)",
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"fplibMulAdd<uint64_t>(cOp3, fplibNeg<uint64_t>(cOp1), cOp2, fpscr)" )
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buildTernaryFpOp("FNMAdd", "SimdFloatMultAccOp",
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buildTernaryFpOp("FNMAdd", "FloatMultAccOp",
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"fplibMulAdd<uint32_t>(fplibNeg<uint32_t>(cOp3), fplibNeg<uint32_t>(cOp1), cOp2, fpscr)",
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"fplibMulAdd<uint64_t>(fplibNeg<uint64_t>(cOp3), fplibNeg<uint64_t>(cOp1), cOp2, fpscr)" )
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buildTernaryFpOp("FNMSub", "SimdFloatMultAccOp",
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buildTernaryFpOp("FNMSub", "FloatMultAccOp",
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"fplibMulAdd<uint32_t>(fplibNeg<uint32_t>(cOp3), cOp1, cOp2, fpscr)",
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"fplibMulAdd<uint64_t>(fplibNeg<uint64_t>(cOp3), cOp1, cOp2, fpscr)" )
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@ -304,31 +304,31 @@ let {{
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decoder_output += constructorTempl.subst(iop)
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exec_output += BasicExecute.subst(iop)
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buildBinFpOp("fadd", "FAdd", "FpRegRegRegOp", "SimdFloatAddOp",
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buildBinFpOp("fadd", "FAdd", "FpRegRegRegOp", "FloatAddOp",
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"fplibAdd<uint32_t>(cOp1, cOp2, fpscr)",
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"fplibAdd<uint64_t>(cOp1, cOp2, fpscr)")
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buildBinFpOp("fsub", "FSub", "FpRegRegRegOp", "SimdFloatAddOp",
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buildBinFpOp("fsub", "FSub", "FpRegRegRegOp", "FloatAddOp",
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"fplibSub<uint32_t>(cOp1, cOp2, fpscr)",
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"fplibSub<uint64_t>(cOp1, cOp2, fpscr)")
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buildBinFpOp("fdiv", "FDiv", "FpRegRegRegOp", "SimdFloatDivOp",
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buildBinFpOp("fdiv", "FDiv", "FpRegRegRegOp", "FloatDivOp",
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"fplibDiv<uint32_t>(cOp1, cOp2, fpscr)",
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"fplibDiv<uint64_t>(cOp1, cOp2, fpscr)")
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buildBinFpOp("fmul", "FMul", "FpRegRegRegOp", "SimdFloatMultOp",
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buildBinFpOp("fmul", "FMul", "FpRegRegRegOp", "FloatMultOp",
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"fplibMul<uint32_t>(cOp1, cOp2, fpscr)",
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"fplibMul<uint64_t>(cOp1, cOp2, fpscr)")
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buildBinFpOp("fnmul", "FNMul", "FpRegRegRegOp", "SimdFloatMultOp",
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buildBinFpOp("fnmul", "FNMul", "FpRegRegRegOp", "FloatMultOp",
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"fplibNeg<uint32_t>(fplibMul<uint32_t>(cOp1, cOp2, fpscr))",
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"fplibNeg<uint64_t>(fplibMul<uint64_t>(cOp1, cOp2, fpscr))")
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buildBinFpOp("fmin", "FMin", "FpRegRegRegOp", "SimdFloatCmpOp",
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buildBinFpOp("fmin", "FMin", "FpRegRegRegOp", "FloatCmpOp",
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"fplibMin<uint32_t>(cOp1, cOp2, fpscr)",
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"fplibMin<uint64_t>(cOp1, cOp2, fpscr)")
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buildBinFpOp("fmax", "FMax", "FpRegRegRegOp", "SimdFloatCmpOp",
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buildBinFpOp("fmax", "FMax", "FpRegRegRegOp", "FloatCmpOp",
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"fplibMax<uint32_t>(cOp1, cOp2, fpscr)",
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"fplibMax<uint64_t>(cOp1, cOp2, fpscr)")
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buildBinFpOp("fminnm", "FMinNM", "FpRegRegRegOp", "SimdFloatCmpOp",
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buildBinFpOp("fminnm", "FMinNM", "FpRegRegRegOp", "FloatCmpOp",
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"fplibMinNum<uint32_t>(cOp1, cOp2, fpscr)",
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"fplibMinNum<uint64_t>(cOp1, cOp2, fpscr)")
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buildBinFpOp("fmaxnm", "FMaxNM", "FpRegRegRegOp", "SimdFloatCmpOp",
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buildBinFpOp("fmaxnm", "FMaxNM", "FpRegRegRegOp", "FloatCmpOp",
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"fplibMaxNum<uint32_t>(cOp1, cOp2, fpscr)",
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"fplibMaxNum<uint64_t>(cOp1, cOp2, fpscr)")
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@ -354,7 +354,7 @@ let {{
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decoder_output += constructorTempl.subst(iop)
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exec_output += BasicExecute.subst(iop)
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buildUnaryFpOp("fsqrt", "FSqrt", "FpRegRegOp", "SimdFloatSqrtOp",
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buildUnaryFpOp("fsqrt", "FSqrt", "FpRegRegOp", "FloatSqrtOp",
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"fplibSqrt<uint32_t>(cOp1, fpscr)", "fplibSqrt<uint64_t>(cOp1, fpscr)")
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def buildSimpleUnaryFpOp(name, Name, base, opClass, singleOp,
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@ -383,29 +383,29 @@ let {{
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decoder_output += constructorTempl.subst(iop)
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exec_output += BasicExecute.subst(iop)
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buildSimpleUnaryFpOp("fneg", "FNeg", "FpRegRegOp", "SimdFloatMiscOp",
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buildSimpleUnaryFpOp("fneg", "FNeg", "FpRegRegOp", "FloatMiscOp",
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"fplibNeg<uint32_t>(cOp1)", "fplibNeg<uint64_t>(cOp1)")
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buildSimpleUnaryFpOp("fabs", "FAbs", "FpRegRegOp", "SimdFloatMiscOp",
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buildSimpleUnaryFpOp("fabs", "FAbs", "FpRegRegOp", "FloatMiscOp",
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"fplibAbs<uint32_t>(cOp1)", "fplibAbs<uint64_t>(cOp1)")
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buildSimpleUnaryFpOp("frintn", "FRIntN", "FpRegRegOp", "SimdFloatMiscOp",
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buildSimpleUnaryFpOp("frintn", "FRIntN", "FpRegRegOp", "FloatMiscOp",
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"fplibRoundInt<uint32_t>(cOp1, FPRounding_TIEEVEN, false, fpscr)",
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"fplibRoundInt<uint64_t>(cOp1, FPRounding_TIEEVEN, false, fpscr)")
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buildSimpleUnaryFpOp("frintp", "FRIntP", "FpRegRegOp", "SimdFloatMiscOp",
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buildSimpleUnaryFpOp("frintp", "FRIntP", "FpRegRegOp", "FloatMiscOp",
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"fplibRoundInt<uint32_t>(cOp1, FPRounding_POSINF, false, fpscr)",
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"fplibRoundInt<uint64_t>(cOp1, FPRounding_POSINF, false, fpscr)")
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buildSimpleUnaryFpOp("frintm", "FRIntM", "FpRegRegOp", "SimdFloatMiscOp",
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buildSimpleUnaryFpOp("frintm", "FRIntM", "FpRegRegOp", "FloatMiscOp",
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"fplibRoundInt<uint32_t>(cOp1, FPRounding_NEGINF, false, fpscr)",
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"fplibRoundInt<uint64_t>(cOp1, FPRounding_NEGINF, false, fpscr)")
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buildSimpleUnaryFpOp("frintz", "FRIntZ", "FpRegRegOp", "SimdFloatMiscOp",
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buildSimpleUnaryFpOp("frintz", "FRIntZ", "FpRegRegOp", "FloatMiscOp",
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"fplibRoundInt<uint32_t>(cOp1, FPRounding_ZERO, false, fpscr)",
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"fplibRoundInt<uint64_t>(cOp1, FPRounding_ZERO, false, fpscr)")
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buildSimpleUnaryFpOp("frinta", "FRIntA", "FpRegRegOp", "SimdFloatMiscOp",
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buildSimpleUnaryFpOp("frinta", "FRIntA", "FpRegRegOp", "FloatMiscOp",
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"fplibRoundInt<uint32_t>(cOp1, FPRounding_TIEAWAY, false, fpscr)",
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"fplibRoundInt<uint64_t>(cOp1, FPRounding_TIEAWAY, false, fpscr)")
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buildSimpleUnaryFpOp("frinti", "FRIntI", "FpRegRegOp", "SimdFloatMiscOp",
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buildSimpleUnaryFpOp("frinti", "FRIntI", "FpRegRegOp", "FloatMiscOp",
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"fplibRoundInt<uint32_t>(cOp1, FPCRRounding(fpscr), false, fpscr)",
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"fplibRoundInt<uint64_t>(cOp1, FPCRRounding(fpscr), false, fpscr)")
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buildSimpleUnaryFpOp("frintx", "FRIntX", "FpRegRegOp", "SimdFloatMiscOp",
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buildSimpleUnaryFpOp("frintx", "FRIntX", "FpRegRegOp", "FloatMiscOp",
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"fplibRoundInt<uint32_t>(cOp1, FPCRRounding(fpscr), true, fpscr)",
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"fplibRoundInt<uint64_t>(cOp1, FPCRRounding(fpscr), true, fpscr)")
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}};
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@ -451,8 +451,8 @@ let {{
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instName = "Fcvt%s%sIntFp%s" %(regL, us, "D" if isDouble else "S")
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mnem = "%scvtf" %(us.lower())
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fcvtIntFpDIop = InstObjParams(mnem, instName, "FpRegRegOp",
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{ "code": fcvtIntFpDCode,
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"op_class": "SimdFloatCvtOp" }, [])
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{ "code": fcvtIntFpDCode,
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"op_class": "FloatCvtOp" }, [])
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header_output += FpRegRegOpDeclare.subst(fcvtIntFpDIop);
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decoder_output += AA64FpRegRegOpConstructor.subst(fcvtIntFpDIop);
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exec_output += BasicExecute.subst(fcvtIntFpDIop);
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@ -491,7 +491,7 @@ let {{
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mnem = "fcvt%s%s" %(rmode, "s" if isSigned else "u")
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fcvtFpIntIop = InstObjParams(mnem, instName, "FpRegRegOp",
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{ "code": fcvtFpIntCode,
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"op_class": "SimdFloatCvtOp" }, [])
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"op_class": "FloatCvtOp" }, [])
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header_output += FpRegRegOpDeclare.subst(fcvtFpIntIop);
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decoder_output += FpRegRegOpConstructor.subst(fcvtFpIntIop);
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exec_output += BasicExecute.subst(fcvtFpIntIop);
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@ -514,7 +514,7 @@ let {{
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'''
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fcvtFpSFpDIop = InstObjParams("fcvt", "FCvtFpSFpD", "FpRegRegOp",
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{ "code": fcvtFpSFpDCode,
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"op_class": "SimdFloatCvtOp" }, [])
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"op_class": "FloatCvtOp" }, [])
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header_output += FpRegRegOpDeclare.subst(fcvtFpSFpDIop);
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decoder_output += AA64FpRegRegOpConstructor.subst(fcvtFpSFpDIop);
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exec_output += BasicExecute.subst(fcvtFpSFpDIop);
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@ -531,7 +531,7 @@ let {{
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'''
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fcvtFpDFpSIop = InstObjParams("fcvt", "FcvtFpDFpS", "FpRegRegOp",
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{"code": fcvtFpDFpSCode,
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"op_class": "SimdFloatCvtOp" }, [])
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"op_class": "FloatCvtOp" }, [])
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header_output += FpRegRegOpDeclare.subst(fcvtFpDFpSIop);
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decoder_output += AA64FpRegRegOpConstructor.subst(fcvtFpDFpSIop);
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exec_output += BasicExecute.subst(fcvtFpDFpSIop);
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@ -563,7 +563,7 @@ let {{
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instName = "FcvtFpHFp%s" %("D" if isDouble else "S")
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fcvtFpHFpIop = InstObjParams("fcvt", instName, "FpRegRegOp",
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{ "code": code,
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"op_class": "SimdFloatCvtOp" }, [])
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"op_class": "FloatCvtOp" }, [])
|
||||
header_output += FpRegRegOpDeclare.subst(fcvtFpHFpIop);
|
||||
decoder_output += AA64FpRegRegOpConstructor.subst(fcvtFpHFpIop);
|
||||
exec_output += BasicExecute.subst(fcvtFpHFpIop);
|
||||
|
|
@ -586,7 +586,7 @@ let {{
|
|||
instName = "FcvtFp%sFpH" %("D" if isDouble else "S")
|
||||
fcvtFpFpHIop = InstObjParams("fcvt", instName, "FpRegRegOp",
|
||||
{ "code": code,
|
||||
"op_class": "SimdFloatCvtOp" }, [])
|
||||
"op_class": "FloatCvtOp" }, [])
|
||||
header_output += FpRegRegOpDeclare.subst(fcvtFpFpHIop);
|
||||
decoder_output += AA64FpRegRegOpConstructor.subst(fcvtFpFpHIop);
|
||||
exec_output += BasicExecute.subst(fcvtFpFpHIop);
|
||||
|
|
@ -626,7 +626,7 @@ let {{
|
|||
fcmpIop = InstObjParams("fcmp%s" %("" if isQuiet else "e"), instName,
|
||||
"FpReg%sOp" %(typeName),
|
||||
{"code": fcmpCode,
|
||||
"op_class": "SimdFloatCmpOp"}, [])
|
||||
"op_class": "FloatCmpOp"}, [])
|
||||
|
||||
declareTemp = eval("FpReg%sOpDeclare" %(typeName));
|
||||
constructorTemp = eval("AA64FpReg%sOpConstructor" %(typeName));
|
||||
|
|
@ -673,7 +673,7 @@ let {{
|
|||
fccmpIop = InstObjParams("fccmp%s" %("" if isQuiet else "e"),
|
||||
instName, "FpCondCompRegOp",
|
||||
{"code": fccmpCode,
|
||||
"op_class": "SimdFloatCmpOp"}, [])
|
||||
"op_class": "FloatCmpOp"}, [])
|
||||
header_output += DataXCondCompRegDeclare.subst(fccmpIop);
|
||||
decoder_output += DataXCondCompRegConstructor.subst(fccmpIop);
|
||||
exec_output += BasicExecute.subst(fccmpIop);
|
||||
|
|
@ -718,7 +718,7 @@ let {{
|
|||
mnem = "fcvtz%s" %("s" if isSigned else "u")
|
||||
fcvtFpFixedIop = InstObjParams(mnem, instName, "FpRegRegImmOp",
|
||||
{ "code": fcvtFpFixedCode,
|
||||
"op_class": "SimdFloatCvtOp" }, [])
|
||||
"op_class": "FloatCvtOp" }, [])
|
||||
header_output += FpRegRegImmOpDeclare.subst(fcvtFpFixedIop);
|
||||
decoder_output += AA64FpRegRegImmOpConstructor.subst(fcvtFpFixedIop);
|
||||
exec_output += BasicExecute.subst(fcvtFpFixedIop);
|
||||
|
|
@ -759,7 +759,7 @@ let {{
|
|||
mnem = "%scvtf" %("s" if isSigned else "u")
|
||||
fcvtFixedFpIop = InstObjParams(mnem, instName, "FpRegRegImmOp",
|
||||
{ "code": fcvtFixedFpCode,
|
||||
"op_class": "SimdFloatCvtOp" }, [])
|
||||
"op_class": "FloatCvtOp" }, [])
|
||||
header_output += FpRegRegImmOpDeclare.subst(fcvtFixedFpIop);
|
||||
decoder_output += FpRegRegImmOpConstructor.subst(fcvtFixedFpIop);
|
||||
exec_output += BasicExecute.subst(fcvtFixedFpIop);
|
||||
|
|
@ -804,7 +804,8 @@ let {{
|
|||
'''
|
||||
|
||||
iop = InstObjParams("fcsel", "FCSel%s" %("D" if isDouble else "S"),
|
||||
"FpCondSelOp", code)
|
||||
"FpCondSelOp", { "code": code,
|
||||
"op_class": "FloatCvtOp" })
|
||||
header_output += DataXCondSelDeclare.subst(iop)
|
||||
decoder_output += DataXCondSelConstructor.subst(iop)
|
||||
exec_output += BasicExecute.subst(iop)
|
||||
|
|
|
|||
|
|
@ -1130,9 +1130,21 @@ class InstObjParams(object):
|
|||
# These are good enough for most cases.
|
||||
if not self.op_class:
|
||||
if 'IsStore' in self.flags:
|
||||
self.op_class = 'MemWriteOp'
|
||||
# The order matters here: 'IsFloating' and 'IsInteger' are
|
||||
# usually set in FP instructions because of the base
|
||||
# register
|
||||
if 'IsFloating' in self.flags:
|
||||
self.op_class = 'FloatMemWriteOp'
|
||||
else:
|
||||
self.op_class = 'MemWriteOp'
|
||||
elif 'IsLoad' in self.flags or 'IsPrefetch' in self.flags:
|
||||
self.op_class = 'MemReadOp'
|
||||
# The order matters here: 'IsFloating' and 'IsInteger' are
|
||||
# usually set in FP instructions because of the base
|
||||
# register
|
||||
if 'IsFloating' in self.flags:
|
||||
self.op_class = 'FloatMemReadOp'
|
||||
else:
|
||||
self.op_class = 'MemReadOp'
|
||||
elif 'IsFloating' in self.flags:
|
||||
self.op_class = 'FloatAddOp'
|
||||
else:
|
||||
|
|
|
|||
|
|
@ -43,13 +43,15 @@ from m5.params import *
|
|||
|
||||
class OpClass(Enum):
|
||||
vals = ['No_OpClass', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd',
|
||||
'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatDiv', 'FloatSqrt',
|
||||
'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatMultAcc', 'FloatDiv',
|
||||
'FloatMisc', 'FloatSqrt',
|
||||
'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt',
|
||||
'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc',
|
||||
'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp',
|
||||
'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc', 'SimdFloatMult',
|
||||
'SimdFloatMultAcc', 'SimdFloatSqrt',
|
||||
'MemRead', 'MemWrite', 'IprAccess', 'InstPrefetch']
|
||||
'MemRead', 'MemWrite', 'FloatMemRead', 'FloatMemWrite',
|
||||
'IprAccess', 'InstPrefetch']
|
||||
|
||||
class OpDesc(SimObject):
|
||||
type = 'OpDesc'
|
||||
|
|
|
|||
|
|
@ -142,8 +142,8 @@ class MinorDefaultIntDivFU(MinorFU):
|
|||
|
||||
class MinorDefaultFloatSimdFU(MinorFU):
|
||||
opClasses = minorMakeOpClassSet([
|
||||
'FloatAdd', 'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatDiv',
|
||||
'FloatSqrt',
|
||||
'FloatAdd', 'FloatCmp', 'FloatCvt', 'FloatMisc', 'FloatMult',
|
||||
'FloatMultAcc', 'FloatDiv', 'FloatSqrt',
|
||||
'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt',
|
||||
'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc',
|
||||
'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp',
|
||||
|
|
@ -154,7 +154,8 @@ class MinorDefaultFloatSimdFU(MinorFU):
|
|||
opLat = 6
|
||||
|
||||
class MinorDefaultMemFU(MinorFU):
|
||||
opClasses = minorMakeOpClassSet(['MemRead', 'MemWrite'])
|
||||
opClasses = minorMakeOpClassSet(['MemRead', 'MemWrite', 'FloatMemRead',
|
||||
'FloatMemWrite'])
|
||||
timings = [MinorFUTiming(description='Mem',
|
||||
srcRegsRelativeLats=[1], extraAssumedLat=2)]
|
||||
opLat = 1
|
||||
|
|
|
|||
|
|
@ -68,6 +68,8 @@ class FP_ALU(FUDesc):
|
|||
|
||||
class FP_MultDiv(FUDesc):
|
||||
opList = [ OpDesc(opClass='FloatMult', opLat=4),
|
||||
OpDesc(opClass='FloatMultAcc', opLat=5),
|
||||
OpDesc(opClass='FloatMisc', opLat=3),
|
||||
OpDesc(opClass='FloatDiv', opLat=12, pipelined=False),
|
||||
OpDesc(opClass='FloatSqrt', opLat=24, pipelined=False) ]
|
||||
count = 2
|
||||
|
|
@ -96,15 +98,18 @@ class SIMD_Unit(FUDesc):
|
|||
count = 4
|
||||
|
||||
class ReadPort(FUDesc):
|
||||
opList = [ OpDesc(opClass='MemRead') ]
|
||||
opList = [ OpDesc(opClass='MemRead'),
|
||||
OpDesc(opClass='FloatMemRead') ]
|
||||
count = 0
|
||||
|
||||
class WritePort(FUDesc):
|
||||
opList = [ OpDesc(opClass='MemWrite') ]
|
||||
opList = [ OpDesc(opClass='MemWrite'),
|
||||
OpDesc(opClass='FloatMemWrite') ]
|
||||
count = 0
|
||||
|
||||
class RdWrPort(FUDesc):
|
||||
opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite') ]
|
||||
opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite'),
|
||||
OpDesc(opClass='FloatMemRead'), OpDesc(opClass='FloatMemWrite')]
|
||||
count = 4
|
||||
|
||||
class IprPort(FUDesc):
|
||||
|
|
|
|||
|
|
@ -59,7 +59,9 @@ static const OpClass FloatAddOp = Enums::FloatAdd;
|
|||
static const OpClass FloatCmpOp = Enums::FloatCmp;
|
||||
static const OpClass FloatCvtOp = Enums::FloatCvt;
|
||||
static const OpClass FloatMultOp = Enums::FloatMult;
|
||||
static const OpClass FloatMultAccOp = Enums::FloatMultAcc;
|
||||
static const OpClass FloatDivOp = Enums::FloatDiv;
|
||||
static const OpClass FloatMiscOp = Enums::FloatMisc;
|
||||
static const OpClass FloatSqrtOp = Enums::FloatSqrt;
|
||||
static const OpClass SimdAddOp = Enums::SimdAdd;
|
||||
static const OpClass SimdAddAccOp = Enums::SimdAddAcc;
|
||||
|
|
@ -83,6 +85,8 @@ static const OpClass SimdFloatMultAccOp = Enums::SimdFloatMultAcc;
|
|||
static const OpClass SimdFloatSqrtOp = Enums::SimdFloatSqrt;
|
||||
static const OpClass MemReadOp = Enums::MemRead;
|
||||
static const OpClass MemWriteOp = Enums::MemWrite;
|
||||
static const OpClass FloatMemReadOp = Enums::FloatMemRead;
|
||||
static const OpClass FloatMemWriteOp = Enums::FloatMemWrite;
|
||||
static const OpClass IprAccessOp = Enums::IprAccess;
|
||||
static const OpClass InstPrefetchOp = Enums::InstPrefetch;
|
||||
static const OpClass Num_OpClasses = Enums::Num_OpClass;
|
||||
|
|
|
|||
Loading…
Reference in a new issue