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arch: Use const StaticInstPtr references where possible

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This patch optimises the passing of StaticInstPtr by avoiding copying
the reference-counting pointer. This avoids first incrementing and
then decrementing the reference-counting pointer.
This commit is contained in:
Andreas Hansson 2014-09-27 09:08:36 -04:00
parent deb2200671
commit 341dbf2662
47 changed files with 194 additions and 191 deletions
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12
src/arch/alpha/faults.cc
View file

@ -106,7 +106,7 @@ FaultVect IntegerOverflowFault::_vect = 0x0501;
FaultStat IntegerOverflowFault::_count;
void
AlphaFault::invoke(ThreadContext *tc, StaticInstPtr inst)
AlphaFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
FaultBase::invoke(tc);
if (!FullSystem)
@ -130,7 +130,7 @@ AlphaFault::invoke(ThreadContext *tc, StaticInstPtr inst)
}
void
ArithmeticFault::invoke(ThreadContext *tc, StaticInstPtr inst)
ArithmeticFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
FaultBase::invoke(tc);
if (!FullSystem)
@ -139,7 +139,7 @@ ArithmeticFault::invoke(ThreadContext *tc, StaticInstPtr inst)
}
void
DtbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
DtbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
if (FullSystem) {
// Set fault address and flags. Even though we're modeling an
@ -169,7 +169,7 @@ DtbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
}
void
ItbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
ItbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
if (FullSystem) {
if (!tc->misspeculating()) {
@ -183,7 +183,7 @@ ItbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
}
void
ItbPageFault::invoke(ThreadContext *tc, StaticInstPtr inst)
ItbPageFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
if (FullSystem) {
ItbFault::invoke(tc);
@ -202,7 +202,7 @@ ItbPageFault::invoke(ThreadContext *tc, StaticInstPtr inst)
}
void
NDtbMissFault::invoke(ThreadContext *tc, StaticInstPtr inst)
NDtbMissFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
if (FullSystem) {
DtbFault::invoke(tc, inst);

24
src/arch/alpha/faults.hh
View file

@ -48,8 +48,8 @@ class AlphaFault : public FaultBase
virtual bool skipFaultingInstruction() {return false;}
virtual bool setRestartAddress() {return true;}
public:
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
virtual FaultVect vect() = 0;
virtual FaultStat & countStat() = 0;
};
@ -108,8 +108,8 @@ class ArithmeticFault : public AlphaFault
FaultName name() const {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
};
class InterruptFault : public AlphaFault
@ -142,8 +142,8 @@ class DtbFault : public AlphaFault
FaultName name() const = 0;
FaultVect vect() = 0;
FaultStat & countStat() = 0;
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
};
class NDtbMissFault : public DtbFault
@ -160,8 +160,8 @@ class NDtbMissFault : public DtbFault
FaultName name() const {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
};
class PDtbMissFault : public DtbFault
@ -238,8 +238,8 @@ class ItbFault : public AlphaFault
FaultName name() const = 0;
FaultVect vect() = 0;
FaultStat & countStat() = 0;
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
};
class ItbPageFault : public ItbFault
@ -254,8 +254,8 @@ class ItbPageFault : public ItbFault
FaultName name() const {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
};
class ItbAcvFault : public ItbFault

2
src/arch/alpha/stacktrace.cc
View file

@ -122,7 +122,7 @@ StackTrace::StackTrace()
{
}
StackTrace::StackTrace(ThreadContext *_tc, StaticInstPtr inst)
StackTrace::StackTrace(ThreadContext *_tc, const StaticInstPtr &inst)
: tc(0), stack(64)
{
trace(_tc, inst);

6
src/arch/alpha/stacktrace.hh
View file

@ -76,7 +76,7 @@ class StackTrace
public:
StackTrace();
StackTrace(ThreadContext *tc, StaticInstPtr inst);
StackTrace(ThreadContext *tc, const StaticInstPtr &inst);
~StackTrace();
void
@ -87,7 +87,7 @@ class StackTrace
}
bool valid() const { return tc != NULL; }
bool trace(ThreadContext *tc, StaticInstPtr inst);
bool trace(ThreadContext *tc, const StaticInstPtr &inst);
public:
const std::vector<Addr> &getstack() const { return stack; }
@ -111,7 +111,7 @@ class StackTrace
};
inline bool
StackTrace::trace(ThreadContext *tc, StaticInstPtr inst)
StackTrace::trace(ThreadContext *tc, const StaticInstPtr &inst)
{
if (!inst->isCall() && !inst->isReturn())
return false;

2
src/arch/alpha/utility.hh
View file

@ -105,7 +105,7 @@ void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
void skipFunction(ThreadContext *tc);
inline void
advancePC(PCState &pc, const StaticInstPtr inst)
advancePC(PCState &pc, const StaticInstPtr &inst)
{
pc.advance();
}

24
src/arch/arm/faults.cc
View file

@ -426,7 +426,7 @@ ArmFault::setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg)
}
void
ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst)
ArmFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
@ -587,7 +587,7 @@ ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst)
}
void
ArmFault::invoke64(ThreadContext *tc, StaticInstPtr inst)
ArmFault::invoke64(ThreadContext *tc, const StaticInstPtr &inst)
{
// Determine actual misc. register indices for ELR_ELx and SPSR_ELx
MiscRegIndex elr_idx, spsr_idx;
@ -678,7 +678,7 @@ ArmFault::invoke64(ThreadContext *tc, StaticInstPtr inst)
}
void
Reset::invoke(ThreadContext *tc, StaticInstPtr inst)
Reset::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
if (FullSystem) {
tc->getCpuPtr()->clearInterrupts();
@ -706,7 +706,7 @@ Reset::invoke(ThreadContext *tc, StaticInstPtr inst)
}
void
UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
UndefinedInstruction::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
if (FullSystem) {
ArmFault::invoke(tc, inst);
@ -767,7 +767,7 @@ UndefinedInstruction::iss() const
}
void
SupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst)
SupervisorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
if (FullSystem) {
ArmFault::invoke(tc, inst);
@ -884,7 +884,7 @@ ArmFaultVals<T>::offset(ThreadContext *tc)
// }
void
SecureMonitorCall::invoke(ThreadContext *tc, StaticInstPtr inst)
SecureMonitorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
if (FullSystem) {
ArmFault::invoke(tc, inst);
@ -913,7 +913,7 @@ SecureMonitorTrap::ec(ThreadContext *tc) const
template<class T>
void
AbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst)
AbortFault<T>::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
if (tranMethod == ArmFault::UnknownTran) {
tranMethod = longDescFormatInUse(tc) ? ArmFault::LpaeTran
@ -1237,7 +1237,7 @@ DataAbort::annotate(AnnotationIDs id, uint64_t val)
}
void
VirtualDataAbort::invoke(ThreadContext *tc, StaticInstPtr inst)
VirtualDataAbort::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
AbortFault<VirtualDataAbort>::invoke(tc, inst);
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
@ -1336,7 +1336,7 @@ VirtualFastInterrupt::VirtualFastInterrupt()
{}
void
PCAlignmentFault::invoke(ThreadContext *tc, StaticInstPtr inst)
PCAlignmentFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
ArmFaultVals<PCAlignmentFault>::invoke(tc, inst);
assert(from64);
@ -1351,7 +1351,7 @@ SystemError::SystemError()
{}
void
SystemError::invoke(ThreadContext *tc, StaticInstPtr inst)
SystemError::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
tc->getCpuPtr()->clearInterrupt(INT_ABT, 0);
ArmFault::invoke(tc, inst);
@ -1382,7 +1382,7 @@ SystemError::routeToHyp(ThreadContext *tc) const
}
void
FlushPipe::invoke(ThreadContext *tc, StaticInstPtr inst) {
FlushPipe::invoke(ThreadContext *tc, const StaticInstPtr &inst) {
DPRINTF(Faults, "Invoking FlushPipe Fault\n");
// Set the PC to the next instruction of the faulting instruction.
@ -1395,7 +1395,7 @@ FlushPipe::invoke(ThreadContext *tc, StaticInstPtr inst) {
}
void
ArmSev::invoke(ThreadContext *tc, StaticInstPtr inst) {
ArmSev::invoke(ThreadContext *tc, const StaticInstPtr &inst) {
DPRINTF(Faults, "Invoking ArmSev Fault\n");
if (!FullSystem)
return;

46
src/arch/arm/faults.hh
View file

@ -181,10 +181,10 @@ class ArmFault : public FaultBase
// exception level
MiscRegIndex getFaultAddrReg64() const;
void invoke(ThreadContext *tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke64(ThreadContext *tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
void invoke64(ThreadContext *tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
virtual void annotate(AnnotationIDs id, uint64_t val) {}
virtual FaultStat& countStat() = 0;
virtual FaultOffset offset(ThreadContext *tc) = 0;
@ -249,8 +249,8 @@ class ArmFaultVals : public ArmFault
class Reset : public ArmFaultVals<Reset>
{
public:
void invoke(ThreadContext *tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
};
class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
@ -277,8 +277,8 @@ class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
mnemonic(_mnemonic)
{}
void invoke(ThreadContext *tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
bool routeToHyp(ThreadContext *tc) const;
ExceptionClass ec(ThreadContext *tc) const;
uint32_t iss() const;
@ -295,8 +295,8 @@ class SupervisorCall : public ArmFaultVals<SupervisorCall>
overrideEc(_overrideEc)
{}
void invoke(ThreadContext *tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
bool routeToHyp(ThreadContext *tc) const;
ExceptionClass ec(ThreadContext *tc) const;
uint32_t iss() const;
@ -309,8 +309,8 @@ class SecureMonitorCall : public ArmFaultVals<SecureMonitorCall>
ArmFaultVals<SecureMonitorCall>(_machInst)
{}
void invoke(ThreadContext *tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
ExceptionClass ec(ThreadContext *tc) const;
uint32_t iss() const;
};
@ -401,8 +401,8 @@ class AbortFault : public ArmFaultVals<T>
stage2(_stage2), s1ptw(false), tranMethod(_tranMethod)
{}
void invoke(ThreadContext *tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
FSR getFsr(ThreadContext *tc);
bool abortDisable(ThreadContext *tc);
@ -473,7 +473,7 @@ class VirtualDataAbort : public AbortFault<VirtualDataAbort>
AbortFault<VirtualDataAbort>(_addr, _write, _domain, _source, false)
{}
void invoke(ThreadContext *tc, StaticInstPtr inst);
void invoke(ThreadContext *tc, const StaticInstPtr &inst);
};
class Interrupt : public ArmFaultVals<Interrupt>
@ -514,8 +514,8 @@ class PCAlignmentFault : public ArmFaultVals<PCAlignmentFault>
public:
PCAlignmentFault(Addr _faultPC) : faultPC(_faultPC)
{}
void invoke(ThreadContext *tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
};
/// Stack pointer alignment fault (AArch64 only)
@ -530,8 +530,8 @@ class SystemError : public ArmFaultVals<SystemError>
{
public:
SystemError();
void invoke(ThreadContext *tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
bool routeToMonitor(ThreadContext *tc) const;
bool routeToHyp(ThreadContext *tc) const;
};
@ -541,8 +541,8 @@ class FlushPipe : public ArmFaultVals<FlushPipe>
{
public:
FlushPipe() {}
void invoke(ThreadContext *tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
};
// A fault that flushes the pipe, excluding the faulting instructions
@ -550,8 +550,8 @@ class ArmSev : public ArmFaultVals<ArmSev>
{
public:
ArmSev () {}
void invoke(ThreadContext *tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
};
/// Illegal Instruction Set State fault (AArch64 only)

2
src/arch/arm/stacktrace.cc
View file

@ -121,7 +121,7 @@ namespace ArmISA
{
}
StackTrace::StackTrace(ThreadContext *_tc, StaticInstPtr inst)
StackTrace::StackTrace(ThreadContext *_tc, const StaticInstPtr &inst)
: tc(0), stack(64)
{
trace(_tc, inst);

6
src/arch/arm/stacktrace.hh
View file

@ -78,7 +78,7 @@ class StackTrace
public:
StackTrace();
StackTrace(ThreadContext *tc, StaticInstPtr inst);
StackTrace(ThreadContext *tc, const StaticInstPtr &inst);
~StackTrace();
void clear()
@ -88,7 +88,7 @@ class StackTrace
}
bool valid() const { return tc != NULL; }
bool trace(ThreadContext *tc, StaticInstPtr inst);
bool trace(ThreadContext *tc, const StaticInstPtr &inst);
public:
const std::vector<Addr> &getstack() const { return stack; }
@ -106,7 +106,7 @@ class StackTrace
};
inline bool
StackTrace::trace(ThreadContext *tc, StaticInstPtr inst)
StackTrace::trace(ThreadContext *tc, const StaticInstPtr &inst)
{
if (!inst->isCall() && !inst->isReturn())
return false;

2
src/arch/arm/utility.hh
View file

@ -279,7 +279,7 @@ uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
void skipFunction(ThreadContext *tc);
inline void
advancePC(PCState &pc, const StaticInstPtr inst)
advancePC(PCState &pc, const StaticInstPtr &inst)
{
inst->advancePC(pc);
}

4
src/arch/generic/debugfaults.hh
View file

@ -86,8 +86,8 @@ class M5DebugFault : public FaultBase
}
void
invoke(ThreadContext *tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr)
invoke(ThreadContext *tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr)
{
switch (func) {
case PanicFunc:

8
src/arch/mips/faults.cc
View file

@ -131,7 +131,7 @@ MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode)
}
void
MipsFaultBase::invoke(ThreadContext *tc, StaticInstPtr inst)
MipsFaultBase::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
if (FullSystem) {
DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
@ -143,7 +143,7 @@ MipsFaultBase::invoke(ThreadContext *tc, StaticInstPtr inst)
}
void
ResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
ResetFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
if (FullSystem) {
DPRINTF(MipsPRA, "%s encountered.\n", name());
@ -160,13 +160,13 @@ ResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
}
void
SoftResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
SoftResetFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
panic("Soft reset not implemented.\n");
}
void
NonMaskableInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
NonMaskableInterrupt::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
panic("Non maskable interrupt not implemented.\n");
}

28
src/arch/mips/faults.hh
View file

@ -102,8 +102,8 @@ class MipsFaultBase : public FaultBase
return base(tc) + offset(tc);
}
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
};
template <typename T>
@ -134,23 +134,23 @@ class MachineCheckFault : public MipsFault<MachineCheckFault>
class ResetFault : public MipsFault<ResetFault>
{
public:
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
};
class SoftResetFault : public MipsFault<SoftResetFault>
{
public:
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
};
class NonMaskableInterrupt : public MipsFault<NonMaskableInterrupt>
{
public:
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
};
class CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault>
@ -162,8 +162,8 @@ class CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault>
{}
void
invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr)
invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr)
{
MipsFault<CoprocessorUnusableFault>::invoke(tc, inst);
if (FullSystem) {
@ -197,8 +197,8 @@ class AddressFault : public MipsFault<T>
{}
void
invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr)
invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr)
{
MipsFault<T>::invoke(tc, inst);
if (FullSystem)
@ -250,8 +250,8 @@ class TlbFault : public AddressFault<T>
}
void
invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr)
invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr)
{
if (FullSystem) {
DPRINTF(MipsPRA, "Fault %s encountered.\n", this->name());

2
src/arch/mips/stacktrace.cc
View file

@ -96,7 +96,7 @@ StackTrace::StackTrace()
{
}
StackTrace::StackTrace(ThreadContext *_tc, StaticInstPtr inst)
StackTrace::StackTrace(ThreadContext *_tc, const StaticInstPtr &inst)
: tc(0), stack(64)
{
trace(_tc, inst);

6
src/arch/mips/stacktrace.hh
View file

@ -75,7 +75,7 @@ class StackTrace
public:
StackTrace();
StackTrace(ThreadContext *tc, StaticInstPtr inst);
StackTrace(ThreadContext *tc, const StaticInstPtr &inst);
~StackTrace();
void clear()
@ -85,7 +85,7 @@ class StackTrace
}
bool valid() const { return tc != NULL; }
bool trace(ThreadContext *tc, StaticInstPtr inst);
bool trace(ThreadContext *tc, const StaticInstPtr &inst);
public:
const std::vector<Addr> &getstack() const { return stack; }
@ -107,7 +107,7 @@ class StackTrace
};
inline bool
StackTrace::trace(ThreadContext *tc, StaticInstPtr inst)
StackTrace::trace(ThreadContext *tc, const StaticInstPtr &inst)
{
if (!inst->isCall() && !inst->isReturn())
return false;

2
src/arch/mips/utility.hh
View file

@ -115,7 +115,7 @@ void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
void skipFunction(ThreadContext *tc);
inline void
advancePC(PCState &pc, const StaticInstPtr inst)
advancePC(PCState &pc, const StaticInstPtr &inst)
{
pc.advance();
}

2
src/arch/power/stacktrace.cc
View file

@ -69,7 +69,7 @@ StackTrace::StackTrace()
panic("StackTrace constructor not implemented.\n");
}
StackTrace::StackTrace(ThreadContext *_tc, StaticInstPtr inst)
StackTrace::StackTrace(ThreadContext *_tc, const StaticInstPtr &inst)
: tc(0), stack(64)
{
panic("StackTrace constructor not implemented.\n");

6
src/arch/power/stacktrace.hh
View file

@ -73,7 +73,7 @@ class StackTrace
public:
StackTrace();
StackTrace(ThreadContext *tc, StaticInstPtr inst);
StackTrace(ThreadContext *tc, const StaticInstPtr &inst);
~StackTrace();
void
@ -89,7 +89,7 @@ class StackTrace
return tc != NULL;
}
bool trace(ThreadContext *tc, StaticInstPtr inst);
bool trace(ThreadContext *tc, const StaticInstPtr &inst);
public:
const std::vector<Addr> &
@ -123,7 +123,7 @@ class StackTrace
};
inline bool
StackTrace::trace(ThreadContext *tc, StaticInstPtr inst)
StackTrace::trace(ThreadContext *tc, const StaticInstPtr &inst)
{
if (!inst->isCall() && !inst->isReturn())
return false;

2
src/arch/power/utility.hh
View file

@ -73,7 +73,7 @@ copyMiscRegs(ThreadContext *src, ThreadContext *dest)
void skipFunction(ThreadContext *tc);
inline void
advancePC(PCState &pc, const StaticInstPtr inst)
advancePC(PCState &pc, const StaticInstPtr &inst)
{
pc.advance();
}

15
src/arch/sparc/faults.cc
View file

@ -490,7 +490,7 @@ getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, MiscReg TT, MiscReg TL)
}
void
SparcFaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
SparcFaultBase::invoke(ThreadContext * tc, const StaticInstPtr &inst)
{
FaultBase::invoke(tc);
if (!FullSystem)
@ -551,7 +551,7 @@ SparcFaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
}
void
PowerOnReset::invoke(ThreadContext *tc, StaticInstPtr inst)
PowerOnReset::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
// For SPARC, when a system is first started, there is a power
// on reset Trap which sets the processor into the following state.
@ -614,7 +614,8 @@ PowerOnReset::invoke(ThreadContext *tc, StaticInstPtr inst)
}
void
FastInstructionAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
FastInstructionAccessMMUMiss::invoke(ThreadContext *tc,
const StaticInstPtr &inst)
{
if (FullSystem) {
SparcFaultBase::invoke(tc, inst);
@ -634,7 +635,7 @@ FastInstructionAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
}
void
FastDataAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
FastDataAccessMMUMiss::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
if (FullSystem) {
SparcFaultBase::invoke(tc, inst);
@ -658,7 +659,7 @@ FastDataAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
}
void
SpillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
SpillNNormal::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
if (FullSystem) {
SparcFaultBase::invoke(tc, inst);
@ -678,7 +679,7 @@ SpillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
}
void
FillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
FillNNormal::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
if (FullSystem) {
SparcFaultBase::invoke(tc, inst);
@ -698,7 +699,7 @@ FillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
}
void
TrapInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
TrapInstruction::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
if (FullSystem) {
SparcFaultBase::invoke(tc, inst);

28
src/arch/sparc/faults.hh
View file

@ -65,8 +65,8 @@ class SparcFaultBase : public FaultBase
const PrivilegeLevel nextPrivilegeLevel[NumLevels];
FaultStat count;
};
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
virtual TrapType trapType() = 0;
virtual FaultPriority priority() = 0;
virtual FaultStat & countStat() = 0;
@ -93,8 +93,8 @@ class SparcFault : public SparcFaultBase
class PowerOnReset : public SparcFault<PowerOnReset>
{
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
};
class WatchDogReset : public SparcFault<WatchDogReset> {};
@ -206,8 +206,8 @@ class FastInstructionAccessMMUMiss :
{}
FastInstructionAccessMMUMiss() : vaddr(0)
{}
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
};
class FastDataAccessMMUMiss : public SparcFault<FastDataAccessMMUMiss>
@ -219,8 +219,8 @@ class FastDataAccessMMUMiss : public SparcFault<FastDataAccessMMUMiss>
{}
FastDataAccessMMUMiss() : vaddr(0)
{}
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
};
class FastDataAccessProtection : public SparcFault<FastDataAccessProtection> {};
@ -238,8 +238,8 @@ class SpillNNormal : public EnumeratedFault<SpillNNormal>
public:
SpillNNormal(uint32_t n) : EnumeratedFault<SpillNNormal>(n) {;}
// These need to be handled specially to enable spill traps in SE
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
};
class SpillNOther : public EnumeratedFault<SpillNOther>
@ -255,8 +255,8 @@ class FillNNormal : public EnumeratedFault<FillNNormal>
FillNNormal(uint32_t n) : EnumeratedFault<FillNNormal>(n)
{}
// These need to be handled specially to enable fill traps in SE
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
};
class FillNOther : public EnumeratedFault<FillNOther>
@ -272,8 +272,8 @@ class TrapInstruction : public EnumeratedFault<TrapInstruction>
TrapInstruction(uint32_t n) : EnumeratedFault<TrapInstruction>(n)
{}
// In SE, trap instructions are requesting services from the OS.
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
};
void enterREDState(ThreadContext *tc);

2
src/arch/sparc/stacktrace.hh
View file

@ -48,7 +48,7 @@ class StackTrace
public:
bool
trace(ThreadContext *tc, StaticInstPtr inst)
trace(ThreadContext *tc, const StaticInstPtr &inst)
{
panic("StackTrace::trace not implemented for SPARC.\n");
return false;

2
src/arch/sparc/utility.hh
View file

@ -87,7 +87,7 @@ void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
void skipFunction(ThreadContext *tc);
inline void
advancePC(PCState &pc, const StaticInstPtr inst)
advancePC(PCState &pc, const StaticInstPtr &inst)
{
inst->advancePC(pc);
}

14
src/arch/x86/faults.cc
View file

@ -50,7 +50,7 @@
namespace X86ISA
{
void X86FaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
void X86FaultBase::invoke(ThreadContext * tc, const StaticInstPtr &inst)
{
if (!FullSystem) {
FaultBase::invoke(tc, inst);
@ -104,7 +104,7 @@ namespace X86ISA
return ss.str();
}
void X86Trap::invoke(ThreadContext * tc, StaticInstPtr inst)
void X86Trap::invoke(ThreadContext * tc, const StaticInstPtr &inst)
{
X86FaultBase::invoke(tc);
if (!FullSystem)
@ -116,13 +116,13 @@ namespace X86ISA
pc.uEnd();
}
void X86Abort::invoke(ThreadContext * tc, StaticInstPtr inst)
void X86Abort::invoke(ThreadContext * tc, const StaticInstPtr &inst)
{
panic("Abort exception!");
}
void
InvalidOpcode::invoke(ThreadContext * tc, StaticInstPtr inst)
InvalidOpcode::invoke(ThreadContext * tc, const StaticInstPtr &inst)
{
if (FullSystem) {
X86Fault::invoke(tc, inst);
@ -132,7 +132,7 @@ namespace X86ISA
}
}
void PageFault::invoke(ThreadContext * tc, StaticInstPtr inst)
void PageFault::invoke(ThreadContext * tc, const StaticInstPtr &inst)
{
if (FullSystem) {
HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
@ -170,7 +170,7 @@ namespace X86ISA
}
void
InitInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
InitInterrupt::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
DPRINTF(Faults, "Init interrupt.\n");
// The otherwise unmodified integer registers should be set to 0.
@ -288,7 +288,7 @@ namespace X86ISA
}
void
StartupInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
StartupInterrupt::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
DPRINTF(Faults, "Startup interrupt with vector %#x.\n", vector);
HandyM5Reg m5Reg = tc->readMiscReg(MISCREG_M5_REG);

32
src/arch/x86/faults.hh
View file

@ -85,8 +85,8 @@ namespace X86ISA
return false;
}
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
virtual std::string describe() const;
@ -120,8 +120,8 @@ namespace X86ISA
: X86FaultBase(name, mnem, vector, _errorCode)
{}
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
};
// Base class for x86 aborts which seem to be catastrophic failures.
@ -133,8 +133,8 @@ namespace X86ISA
: X86FaultBase(name, mnem, vector, _errorCode)
{}
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
};
// Base class for x86 interrupts.
@ -155,8 +155,8 @@ namespace X86ISA
return "unimplemented_micro";
}
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr)
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr)
{
panic("Unimplemented instruction!");
}
@ -248,8 +248,8 @@ namespace X86ISA
X86Fault("Invalid-Opcode", "#UD", 6)
{}
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
};
class DeviceNotAvailable : public X86Fault
@ -331,8 +331,8 @@ namespace X86ISA
errorCode = code;
}
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
virtual std::string describe() const;
};
@ -400,8 +400,8 @@ namespace X86ISA
X86Interrupt("INIT Interrupt", "#INIT", _vector)
{}
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
};
class StartupInterrupt : public X86Interrupt
@ -411,8 +411,8 @@ namespace X86ISA
X86Interrupt("Startup Interrupt", "#SIPI", _vector)
{}
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
};
class SoftwareInterrupt : public X86Interrupt

2
src/arch/x86/stacktrace.cc
View file

@ -121,7 +121,7 @@ namespace X86ISA
{
}
StackTrace::StackTrace(ThreadContext *_tc, StaticInstPtr inst)
StackTrace::StackTrace(ThreadContext *_tc, const StaticInstPtr &inst)
: tc(0), stack(64)
{
trace(_tc, inst);

6
src/arch/x86/stacktrace.hh
View file

@ -75,7 +75,7 @@ namespace X86ISA
public:
StackTrace();
StackTrace(ThreadContext *tc, StaticInstPtr inst);
StackTrace(ThreadContext *tc, const StaticInstPtr &inst);
~StackTrace();
void clear()
@ -85,7 +85,7 @@ namespace X86ISA
}
bool valid() const { return tc != NULL; }
bool trace(ThreadContext *tc, StaticInstPtr inst);
bool trace(ThreadContext *tc, const StaticInstPtr &inst);
public:
const std::vector<Addr> &getstack() const { return stack; }
@ -107,7 +107,7 @@ namespace X86ISA
};
inline bool
StackTrace::trace(ThreadContext *tc, StaticInstPtr inst)
StackTrace::trace(ThreadContext *tc, const StaticInstPtr &inst)
{
if (!inst->isCall() && !inst->isReturn())
return false;

2
src/arch/x86/utility.hh
View file

@ -94,7 +94,7 @@ namespace X86ISA
void skipFunction(ThreadContext *tc);
inline void
advancePC(PCState &pc, const StaticInstPtr inst)
advancePC(PCState &pc, const StaticInstPtr &inst)
{
inst->advancePC(pc);
}

8
src/cpu/base_dyn_inst.hh
View file

@ -156,7 +156,7 @@ class BaseDynInst : public ExecContext, public RefCounted
InstSeqNum seqNum;
/** The StaticInst used by this BaseDynInst. */
StaticInstPtr staticInst;
const StaticInstPtr staticInst;
/** Pointer to the Impl's CPU object. */
ImplCPU *cpu;
@ -204,7 +204,7 @@ class BaseDynInst : public ExecContext, public RefCounted
TheISA::PCState predPC;
/** The Macroop if one exists */
StaticInstPtr macroop;
const StaticInstPtr macroop;
/** How many source registers are ready. */
uint8_t readyRegs;
@ -427,14 +427,14 @@ class BaseDynInst : public ExecContext, public RefCounted
* @param seq_num The sequence number of the instruction.
* @param cpu Pointer to the instruction's CPU.
*/
BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop,
BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop,
TheISA::PCState pc, TheISA::PCState predPC,
InstSeqNum seq_num, ImplCPU *cpu);
/** BaseDynInst constructor given a StaticInst pointer.
* @param _staticInst The StaticInst for this BaseDynInst.
*/
BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop);
BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop);
/** BaseDynInst destructor. */
~BaseDynInst();

8
src/cpu/base_dyn_inst_impl.hh
View file

@ -59,8 +59,8 @@
#include "sim/faults.hh"
template <class Impl>
BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
StaticInstPtr _macroop,
BaseDynInst<Impl>::BaseDynInst(const StaticInstPtr &_staticInst,
const StaticInstPtr &_macroop,
TheISA::PCState _pc, TheISA::PCState _predPC,
InstSeqNum seq_num, ImplCPU *cpu)
: staticInst(_staticInst), cpu(cpu), traceData(NULL), macroop(_macroop)
@ -74,8 +74,8 @@ BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
}
template <class Impl>
BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
StaticInstPtr _macroop)
BaseDynInst<Impl>::BaseDynInst(const StaticInstPtr &_staticInst,
const StaticInstPtr &_macroop)
: staticInst(_staticInst), traceData(NULL), macroop(_macroop)
{
seqNum = 0;

2
src/cpu/checker/cpu_impl.hh
View file

@ -303,7 +303,7 @@ Checker<Impl>::verify(DynInstPtr &completed_inst)
microcodeRom.fetchMicroop(pcState.microPC(), NULL);
} else if (!curMacroStaticInst) {
//We're not in the middle of a macro instruction
StaticInstPtr instPtr = NULL;
StaticInstPtr instPtr = nullptr;
//Predecode, ie bundle up an ExtMachInst
//If more fetch data is needed, pass it in.

2
src/cpu/exetrace.cc
View file

@ -56,7 +56,7 @@ ExeTracerRecord::dumpTicks(ostream &outs)
}
void
Trace::ExeTracerRecord::traceInst(StaticInstPtr inst, bool ran)
Trace::ExeTracerRecord::traceInst(const StaticInstPtr &inst, bool ran)
{
ostream &outs = Trace::output();

2
src/cpu/exetrace.hh
View file

@ -56,7 +56,7 @@ class ExeTracerRecord : public InstRecord
{
}
void traceInst(StaticInstPtr inst, bool ran);
void traceInst(const StaticInstPtr &inst, bool ran);
void dump();
virtual void dumpTicks(std::ostream &outs);

2
src/cpu/minor/func_unit.cc
View file

@ -199,7 +199,7 @@ FUPipeline::advance()
}
MinorFUTiming *
FUPipeline::findTiming(StaticInstPtr inst)
FUPipeline::findTiming(const StaticInstPtr &inst)
{
#if THE_ISA == ARM_ISA
/* This should work for any ISA with a POD mach_inst */

2
src/cpu/minor/func_unit.hh
View file

@ -257,7 +257,7 @@ class FUPipeline : public FUPipelineBase, public FuncUnit
/** Find the extra timing information for this instruction. Returns
* NULL if no decode info. is found */
MinorFUTiming *findTiming(StaticInstPtr inst);
MinorFUTiming *findTiming(const StaticInstPtr &inst);
/** Step the pipeline. Allow multiple steps? */
void advance();

5
src/cpu/o3/cpu.cc
View file

@ -946,12 +946,13 @@ FullO3CPU<Impl>::processInterrupts(const Fault &interrupt)
this->interrupts->updateIntrInfo(this->threadContexts[0]);
DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
this->trap(interrupt, 0, NULL);
this->trap(interrupt, 0, nullptr);
}
template <class Impl>
void
FullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid, StaticInstPtr inst)
FullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid,
const StaticInstPtr &inst)
{
// Pass the thread's TC into the invoke method.
fault->invoke(this->threadContexts[tid], inst);

2
src/cpu/o3/cpu.hh
View file

@ -376,7 +376,7 @@ class FullO3CPU : public BaseO3CPU
{ return globalSeqNum++; }
/** Traps to handle given fault. */
void trap(const Fault &fault, ThreadID tid, StaticInstPtr inst);
void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst);
/** HW return from error interrupt. */
Fault hwrei(ThreadID tid);

5
src/cpu/o3/dyn_inst.hh
View file

@ -83,12 +83,13 @@ class BaseO3DynInst : public BaseDynInst<Impl>
public:
/** BaseDynInst constructor given a binary instruction. */
BaseO3DynInst(StaticInstPtr staticInst, StaticInstPtr macroop,
BaseO3DynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop,
TheISA::PCState pc, TheISA::PCState predPC,
InstSeqNum seq_num, O3CPU *cpu);
/** BaseDynInst constructor given a static inst pointer. */
BaseO3DynInst(StaticInstPtr _staticInst, StaticInstPtr _macroop);
BaseO3DynInst(const StaticInstPtr &_staticInst,
const StaticInstPtr &_macroop);
~BaseO3DynInst();

8
src/cpu/o3/dyn_inst_impl.hh
View file

@ -49,8 +49,8 @@
#include "debug/O3PipeView.hh"
template <class Impl>
BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst,
StaticInstPtr macroop,
BaseO3DynInst<Impl>::BaseO3DynInst(const StaticInstPtr &staticInst,
const StaticInstPtr &macroop,
TheISA::PCState pc, TheISA::PCState predPC,
InstSeqNum seq_num, O3CPU *cpu)
: BaseDynInst<Impl>(staticInst, macroop, pc, predPC, seq_num, cpu)
@ -59,8 +59,8 @@ BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst,
}
template <class Impl>
BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr _staticInst,
StaticInstPtr _macroop)
BaseO3DynInst<Impl>::BaseO3DynInst(const StaticInstPtr &_staticInst,
const StaticInstPtr &_macroop)
: BaseDynInst<Impl>(_staticInst, _macroop)
{
initVars();

4
src/cpu/pred/bpred_unit.hh
View file

@ -87,9 +87,9 @@ class BPredUnit : public SimObject
* @param tid The thread id.
* @return Returns if the branch is taken or not.
*/
bool predict(StaticInstPtr &inst, const InstSeqNum &seqNum,
bool predict(const StaticInstPtr &inst, const InstSeqNum &seqNum,
TheISA::PCState &pc, ThreadID tid);
bool predictInOrder(StaticInstPtr &inst, const InstSeqNum &seqNum,
bool predictInOrder(const StaticInstPtr &inst, const InstSeqNum &seqNum,
int asid, TheISA::PCState &instPC,
TheISA::PCState &predPC, ThreadID tid);

4
src/cpu/pred/bpred_unit_impl.hh
View file

@ -129,7 +129,7 @@ BPredUnit::drainSanityCheck() const
}
bool
BPredUnit::predict(StaticInstPtr &inst, const InstSeqNum &seqNum,
BPredUnit::predict(const StaticInstPtr &inst, const InstSeqNum &seqNum,
TheISA::PCState &pc, ThreadID tid)
{
// See if branch predictor predicts taken.
@ -244,7 +244,7 @@ BPredUnit::predict(StaticInstPtr &inst, const InstSeqNum &seqNum,
}
bool
BPredUnit::predictInOrder(StaticInstPtr &inst, const InstSeqNum &seqNum,
BPredUnit::predictInOrder(const StaticInstPtr &inst, const InstSeqNum &seqNum,
int asid, TheISA::PCState &instPC,
TheISA::PCState &predPC, ThreadID tid)
{

4
src/cpu/profile.hh
View file

@ -73,7 +73,7 @@ class FunctionProfile
FunctionProfile(const SymbolTable *symtab);
~FunctionProfile();
ProfileNode *consume(ThreadContext *tc, StaticInstPtr inst);
ProfileNode *consume(ThreadContext *tc, const StaticInstPtr &inst);
ProfileNode *consume(const std::vector<Addr> &stack);
void clear();
void dump(ThreadContext *tc, std::ostream &out) const;
@ -81,7 +81,7 @@ class FunctionProfile
};
inline ProfileNode *
FunctionProfile::consume(ThreadContext *tc, StaticInstPtr inst)
FunctionProfile::consume(ThreadContext *tc, const StaticInstPtr &inst)
{
if (!trace.trace(tc, inst))
return NULL;

2
src/cpu/simple/probes/simpoint.cc
View file

@ -77,7 +77,7 @@ void
SimPoint::profile(const std::pair<SimpleThread*, StaticInstPtr>& p)
{
SimpleThread* thread = p.first;
StaticInstPtr inst = p.second;
const StaticInstPtr &inst = p.second;
if (!currentBBVInstCount)
currentBBV.first = thread->pcState().instAddr();

2
src/cpu/timing_expr.cc
View file

@ -40,7 +40,7 @@
#include "base/intmath.hh"
#include "cpu/timing_expr.hh"
TimingExprEvalContext::TimingExprEvalContext (StaticInstPtr inst_,
TimingExprEvalContext::TimingExprEvalContext(const StaticInstPtr &inst_,
ThreadContext *thread_,
TimingExprLet *let_) :
inst(inst_), thread(thread_), let(let_)

4
src/cpu/timing_expr.hh
View file

@ -73,7 +73,7 @@ class TimingExprEvalContext
{
public:
/** Special visible context */
StaticInstPtr inst;
const StaticInstPtr &inst;
ThreadContext *thread;
/** Context visible as sub expressions. results will hold the results
@ -83,7 +83,7 @@ class TimingExprEvalContext
std::vector<uint64_t> results;
std::vector<bool > resultAvailable;
TimingExprEvalContext(StaticInstPtr inst_,
TimingExprEvalContext(const StaticInstPtr &inst_,
ThreadContext *thread_, TimingExprLet *let_);
};

10
src/sim/faults.cc
View file

@ -39,7 +39,7 @@
#include "sim/full_system.hh"
#include "sim/process.hh"
void FaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
void FaultBase::invoke(ThreadContext * tc, const StaticInstPtr &inst)
{
if (FullSystem) {
DPRINTF(Fault, "Fault %s at PC: %s\n", name(), tc->pcState());
@ -49,17 +49,17 @@ void FaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
}
}
void UnimpFault::invoke(ThreadContext * tc, StaticInstPtr inst)
void UnimpFault::invoke(ThreadContext * tc, const StaticInstPtr &inst)
{
panic("Unimpfault: %s\n", panicStr.c_str());
}
void ReExec::invoke(ThreadContext *tc, StaticInstPtr inst)
void ReExec::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
tc->pcState(tc->pcState());
}
void GenericPageTableFault::invoke(ThreadContext *tc, StaticInstPtr inst)
void GenericPageTableFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
bool handled = false;
if (!FullSystem) {
@ -71,7 +71,7 @@ void GenericPageTableFault::invoke(ThreadContext *tc, StaticInstPtr inst)
}
void GenericAlignmentFault::invoke(ThreadContext *tc, StaticInstPtr inst)
void GenericAlignmentFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
panic("Alignment fault when accessing virtual address %#x\n", vaddr);
}

20
src/sim/faults.hh
View file

@ -54,8 +54,8 @@ class FaultBase : public RefCounted
{
public:
virtual FaultName name() const = 0;
virtual void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
virtual void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
};
class UnimpFault : public FaultBase
@ -68,8 +68,8 @@ class UnimpFault : public FaultBase
{ }
FaultName name() const {return "Unimplemented simulator feature";}
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
};
class ReExec : public FaultBase
@ -77,8 +77,8 @@ class ReExec : public FaultBase
public:
virtual FaultName name() const { return "Re-execution fault";}
ReExec() {}
void invoke(ThreadContext *tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
};
class GenericPageTableFault : public FaultBase
@ -88,8 +88,8 @@ class GenericPageTableFault : public FaultBase
public:
FaultName name() const {return "Generic page table fault";}
GenericPageTableFault(Addr va) : vaddr(va) {}
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
};
class GenericAlignmentFault : public FaultBase
@ -99,8 +99,8 @@ class GenericAlignmentFault : public FaultBase
public:
FaultName name() const {return "Generic alignment fault";}
GenericAlignmentFault(Addr va) : vaddr(va) {}
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
};
#endif // __FAULTS_HH__