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gem5/src/arch/x86
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Alexandru 5efbb4442a mem: adding architectural page table support for SE mode 
This patch enables the use of page tables that are stored in system memory
and respect x86 specification, in SE mode. It defines an architectural
page table for x86 as a MultiLevelPageTable class and puts a placeholder
class for other ISAs page tables, giving the possibility for future
implementation.
2014-08-28 10:11:44 -05:00
..
bios base: Replace the internal varargs stuff with C++11 constructs 2014-08-26 10:13:45 -04:00
insts cpu: Add flag name printing to StaticInst 2014-05-09 18:58:47 -04:00
isa arch: teach ISA parser how to split code across files 2014-05-09 18:58:47 -04:00
linux x86: enables lstat and readlink syscalls 2013-10-07 18:05:49 -05:00
regs arch/x86: add support for explicit CC register file 2013-10-15 14:22:44 -04:00
cpuid.cc x86 cpuid: enable clflush 2013-01-15 07:43:21 -06:00
cpuid.hh scons: Add warning for missing declarations 2013-02-19 05:56:07 -05:00
decoder.cc Decoder: Remove the thread context get/set from the decoder. 2013-01-04 19:00:45 -06:00
decoder.hh x86, cpu: corrects 270c9a75e91f, take over decoder on cpu switch 2013-01-22 00:10:10 -06:00
decoder_tables.cc CPU: Merge the predecoder and decoder. 2012-05-26 13:44:46 -07:00
emulenv.cc CPU: Merge the predecoder and decoder. 2012-05-26 13:44:46 -07:00
emulenv.hh gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
faults.cc x86: Setup correct TSL/TR segment attributes on INIT 2014-03-03 14:44:57 +01:00
faults.hh x86: Expose the interrupt vector in faults 2013-09-18 11:28:24 +02:00
interrupts.cc x86: Add support for checking the raw state of an interrupt 2013-09-18 11:28:27 +02:00
interrupts.hh kvm: x86: Add support for x86 INIT and STARTUP handling 2014-03-16 17:28:23 +01:00
intmessage.hh MEM: Remove the Broadcast destination from the packet 2012-04-14 05:45:55 -04:00
isa.cc x86: Changes to decoder, corrects 9376 2013-01-12 22:09:48 -06:00
isa.hh arch: Make all register index flattening const 2014-01-24 15:29:30 -06:00
isa_traits.hh ISA: generic Linux thread info support 2012-11-02 11:32:00 -05:00
kernel_stats.hh copyright: Change HP copyright on x86 code to be more friendly 2010-05-23 22:44:15 -07:00
locked_mem.hh cpu: Add CPU support for generatig wake up events when LLSC adresses are snooped. 2014-01-24 15:29:30 -06:00
memhelpers.hh ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem. 2011-07-02 22:35:04 -07:00
microcode_rom.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
mmapped_ipr.hh arch: Add support for m5ops using mmapped IPRs 2013-09-30 12:20:43 +02:00
nativetrace.cc gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
nativetrace.hh Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
pagetable.cc x86: add tlb checkpointing 2013-08-07 14:51:17 -05:00
pagetable.hh mem: adding architectural page table support for SE mode 2014-08-28 10:11:44 -05:00
pagetable_walker.cc mem: adding architectural page table support for SE mode 2014-08-28 10:11:44 -05:00
pagetable_walker.hh x86: Squash outstanding walks when instructions are squashed. 2013-05-21 11:40:11 -05:00
process.cc syscall emulation: clean up & comment SyscallReturn 2014-05-12 14:23:31 -07:00
process.hh mem: adding architectural page table support for SE mode 2014-08-28 10:11:44 -05:00
registers.hh arch/x86: add support for explicit CC register file 2013-10-15 14:22:44 -04:00
remote_gdb.cc X86: Get rid of more uses of FULL_SYSTEM. 2011-10-30 00:33:02 -07:00
remote_gdb.hh copyright: Change HP copyright on x86 code to be more friendly 2010-05-23 22:44:15 -07:00
SConscript arch: teach ISA parser how to split code across files 2014-05-09 18:58:47 -04:00
SConsopts copyright: This file need not have had the more restrictive copyright. 2009-02-09 20:10:15 -08:00
stacktrace.cc MEM: Make port proxies use references rather than pointers 2012-02-24 11:45:30 -05:00
stacktrace.hh trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
system.cc x86: Make the boot state VMX compliant 2013-06-18 16:27:28 +02:00
system.hh mem: adding architectural page table support for SE mode 2014-08-28 10:11:44 -05:00
tlb.cc mem: Use a flag instead of address bit 63 for generic IPRs 2013-10-15 13:24:35 +02:00
tlb.hh arch, arm: Preserve TLB bootUncacheability when switching CPUs 2014-05-09 18:58:47 -04:00
types.cc X86: Change the copyright holder to AMD. 2010-08-27 15:35:36 -07:00
types.hh CPU: Merge the predecoder and decoder. 2012-05-26 13:44:46 -07:00
utility.cc x86: Fix x87 state transfer bug 2014-02-05 14:08:13 +01:00
utility.hh x86: Add support routines to load and store 80-bit floats 2013-09-30 09:42:30 +02:00
vtophys.cc X86: Use the AddrTrie class to implement the TLB. 2012-04-14 23:24:18 -07:00
vtophys.hh gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
x86_traits.hh arch/x86: add support for explicit CC register file 2013-10-15 14:22:44 -04:00
X86ISA.py arch: Make the ISA class inherit from SimObject 2013-01-07 13:05:35 -05:00
X86LocalApic.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
X86NativeTrace.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
X86System.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
X86TLB.py x86: add tlb checkpointing 2013-08-07 14:51:17 -05:00