scons: Add warning for missing declarations

This patch enables warnings for missing declarations. To avoid issues
with SWIG-generated code, the warning is only applied to non-SWIG
code.

src/SConscript

@@ -899,9 +899,17 @@ def makeEnv(label, objsfx, strip = False, **kwargs):
                                  '-Wno-unused-value'])
         if compareVersions(env['GCC_VERSION'], '4.6') >= 0:
             swig_env.Append(CCFLAGS='-Wno-unused-but-set-variable')
+
+        # Add additional warnings here that should not be applied to
+        # the SWIG generated code
+        new_env.Append(CXXFLAGS='-Wmissing-declarations')
     if env['CLANG']:
         swig_env.Append(CCFLAGS=['-Wno-unused-label', '-Wno-unused-value'])
 
+        # Add additional warnings here that should not be applied to
+        # the SWIG generated code
+        new_env.Append(CXXFLAGS='-Wmissing-declarations')
+
     werror_env = new_env.Clone()
     werror_env.Append(CCFLAGS='-Werror')
 

src/arch/arm/isa/formats/misc.isa

@@ -81,7 +81,7 @@ def format ArmMsrMrs() {{
 let {{
     header_output = '''
     StaticInstPtr
-    decodeMcrMrc15(ExtMachInst machInst);
+    decodeMcrMrc14(ExtMachInst machInst);
     '''
     decoder_output = '''
     StaticInstPtr

src/arch/arm/isa/insts/m5ops.isa

@@ -38,7 +38,9 @@
 
 
 let {{
-    header_output = ""
+    header_output = '''
+    uint64_t join32to64(uint32_t r1, uint32_t r0);
+    '''
     decoder_output = '''
     uint64_t join32to64(uint32_t r1, uint32_t r0)
     {

src/arch/mips/isa/formats/control.isa

@@ -172,6 +172,13 @@ output decoder {{
 
 }};
 
+output header {{
+        bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num);
+
+        bool isMMUTLB(%(CPU_exec_context)s *xc);
+
+}};
+
 output exec {{
         bool
         isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)

src/arch/mips/isa/formats/dsp.isa

@@ -135,6 +135,12 @@ def template DspHiLoExecute {{
         }
 }};
 
+output header {{
+    bool isDspEnabled(%(CPU_exec_context)s *xc);
+
+    bool isDspPresent(%(CPU_exec_context)s *xc);
+}};
+
 //Outputs to decoder.cc
 output decoder {{
 }};

src/arch/mips/isa/formats/fp.isa

@@ -86,6 +86,11 @@ output decoder {{
         }
 }};
 
+output header {{
+        void fpResetCauseBits(%(CPU_exec_context)s *cpu);
+
+}};
+
 output exec {{
         inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
         {

src/arch/mips/isa/formats/mem.isa

@@ -96,6 +96,11 @@ output decoder {{
 
 }};
 
+output header {{
+    uint64_t getMemData(%(CPU_exec_context)s *xc, Packet *packet);
+
+}};
+
 output exec {{
     /** return data in cases where there the size of data is only
         known in the packet

src/arch/mips/isa/formats/mt.isa

@@ -84,6 +84,17 @@ output decoder {{
     }
 }};
 
+output header {{
+   void getThrRegExValues(%(CPU_exec_context)s *xc,
+                          MipsISA::VPEConf0Reg &vpe_conf0,
+                          MipsISA::TCBindReg &tc_bind_mt,
+                          MipsISA::TCBindReg &tc_bind,
+                          MipsISA::VPEControlReg &vpe_control,
+                          MipsISA::MVPConf0Reg &mvp_conf0);
+
+   void getMTExValues(%(CPU_exec_context)s *xc, MipsISA::Config3Reg &config3);
+}};
+
 output exec {{
     void getThrRegExValues(%(CPU_exec_context)s *xc,
             VPEConf0Reg &vpe_conf0, TCBindReg &tc_bind_mt,

src/arch/mips/isa/includes.isa

@@ -39,7 +39,8 @@ output header {{
 #include <sstream>
 
 #include "arch/mips/isa_traits.hh"
-#include "arch/mips/types.hh"
+#include "arch/mips/mt_constants.hh"
+#include "arch/mips/pra_constants.hh"
 #include "cpu/static_inst.hh"
 #include "mem/packet.hh"
 }};

src/arch/sparc/faults.hh

@@ -276,6 +276,19 @@ class TrapInstruction : public EnumeratedFault<TrapInstruction>
             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 
+void enterREDState(ThreadContext *tc);
+
+void doREDFault(ThreadContext *tc, TrapType tt);
+
+void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv);
+
+void getREDVector(MiscReg TT, Addr &PC, Addr &NPC);
+
+void getHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, MiscReg TT);
+
+void getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, MiscReg TT,
+                   MiscReg TL);
+
 } // namespace SparcISA
 
 #endif // __SPARC_FAULTS_HH__

src/arch/x86/bios/intelmp.hh

@@ -73,6 +73,12 @@ struct X86IntelMPAddrSpaceMappingParams;
 struct X86IntelMPBusHierarchyParams;
 struct X86IntelMPCompatAddrSpaceModParams;
 
+template<class T>
+uint8_t writeOutField(PortProxy& proxy, Addr addr, T val);
+
+uint8_t writeOutString(PortProxy& proxy, Addr addr, std::string str,
+                       int length);
+
 namespace X86ISA
 {
 

src/arch/x86/cpuid.hh

@@ -55,6 +55,8 @@ namespace X86ISA
         {}
     };
 
+    uint64_t stringToRegister(const char *str);
+
     bool doCpuid(ThreadContext * tc, uint32_t function,
             uint32_t index, CpuidResult &result);
 } // namespace X86ISA

src/arch/x86/interrupts.hh

@@ -66,8 +66,12 @@
 class ThreadContext;
 class BaseCPU;
 
+int divideFromConf(uint32_t conf);
+
 namespace X86ISA {
 
+ApicRegIndex decodeAddr(Addr paddr);
+
 class Interrupts : public BasicPioDevice, IntDev
 {
   protected:

src/base/debug.cc

@@ -33,8 +33,6 @@
 
 #include <algorithm>
 #include <csignal>
-#include <map>
-#include <vector>
 
 #include "base/cprintf.hh"
 #include "base/debug.hh"
@@ -62,7 +60,6 @@ breakpoint()
 //
 // Flags for debugging purposes.  Primarily for trace.hh
 //
-typedef std::map<string, Flag *> FlagsMap;
 int allFlagsVersion = 0;
 FlagsMap &
 allFlags()

src/base/debug.hh

@@ -32,6 +32,7 @@
 #ifndef __BASE_DEBUG_HH__
 #define __BASE_DEBUG_HH__
 
+#include <map>
 #include <string>
 #include <vector>
 
@@ -110,6 +111,19 @@ class CompoundFlag : public SimpleFlag
     void disable();
 };
 
+typedef std::map<std::string, Flag *> FlagsMap;
+FlagsMap &allFlags();
+
+Flag *findFlag(const std::string &name);
+
+bool changeFlag(const char *s, bool value);
+
 } // namespace Debug
 
+void setDebugFlag(const char *string);
+
+void clearDebugFlag(const char *string);
+
+void dumpDebugFlags();
+
 #endif // __BASE_DEBUG_HH__

src/base/hostinfo.cc

@@ -44,6 +44,7 @@
 #include <cstring>
 #include <string>
 
+#include "base/hostinfo.hh"
 #include "base/misc.hh"
 #include "base/str.hh"
 #include "base/types.hh"

src/base/hostinfo.hh

@@ -35,6 +35,8 @@
 
 #include "base/types.hh"
 
+std::string __get_hostname();
+
 std::string &hostname();
 
 uint64_t procInfo(const char *filename, const char *target);

src/base/inet.hh

@@ -463,6 +463,7 @@ class UdpPtr
     int pstart() const { return off() + get()->size(); }
 };
 
+uint16_t __tu_cksum(const IpPtr &ip);
 uint16_t cksum(const UdpPtr &ptr);
 
 int hsplit(const EthPacketPtr &ptr);

src/base/statistics.cc

@@ -49,7 +49,6 @@ using namespace std;
 namespace Stats {
 
 std::string Info::separatorString = "::";
-typedef map<const void *, Info *> MapType;
 
 // We wrap these in a function to make sure they're built in time.
 list<Info *> &
@@ -114,7 +113,6 @@ StorageParams::~StorageParams()
 {
 }
 
-typedef map<std::string, Info *> NameMapType;
 NameMapType &
 nameMap()
 {

src/base/statistics.hh

@@ -3164,6 +3164,16 @@ void registerDumpCallback(Callback *cb);
 
 std::list<Info *> &statsList();
 
+typedef std::map<const void *, Info *> MapType;
+MapType &statsMap();
+
+typedef std::map<std::string, Info *> NameMapType;
+NameMapType &nameMap();
+
+bool validateStatName(const std::string &name);
+
 } // namespace Stats
 
+void debugDumpStats();
+
 #endif // __BASE_STATISTICS_HH__

src/base/stats/text.hh

@@ -35,6 +35,7 @@
 #include <string>
 
 #include "base/stats/output.hh"
+#include "base/stats/types.hh"
 #include "base/output.hh"
 
 namespace Stats {
@@ -75,6 +76,8 @@ class Text : public Output
     virtual void end();
 };
 
+std::string ValueToString(Result value, int precision);
+
 Output *initText(const std::string &filename, bool desc);
 
 } // namespace Stats

src/base/userinfo.cc

@@ -34,6 +34,8 @@
 
 #include <string>
 
+#include "base/userinfo.hh"
+
 std::string
 username()
 {

src/cpu/legiontrace.hh

@@ -42,6 +42,8 @@ class ThreadContext;
 
 namespace Trace {
 
+void setupSharedData();
+
 class LegionTraceRecord : public InstRecord
 {
   public:

src/cpu/pc_event.hh

@@ -39,6 +39,7 @@
 
 class ThreadContext;
 class PCEventQueue;
+class System;
 
 class PCEvent
 {
@@ -141,4 +142,8 @@ class BreakPCEvent : public PCEvent
     virtual void process(ThreadContext *tc);
 };
 
+void sched_break_pc_sys(System *sys, Addr addr);
+
+void sched_break_pc(Addr addr);
+
 #endif // __PC_EVENT_HH__

src/dev/disk_image.hh

@@ -137,4 +137,20 @@ class CowDiskImage : public DiskImage
     virtual std::streampos write(const uint8_t *data, std::streampos offset);
 };
 
+void SafeRead(std::ifstream &stream, void *data, int count);
+
+template<class T>
+void SafeRead(std::ifstream &stream, T &data);
+
+template<class T>
+void SafeReadSwap(std::ifstream &stream, T &data);
+
+void SafeWrite(std::ofstream &stream, const void *data, int count);
+
+template<class T>
+void SafeWrite(std::ofstream &stream, const T &data);
+
+template<class T>
+void SafeWriteSwap(std::ofstream &stream, const T &data);
+
 #endif // __DISK_IMAGE_HH__

src/kern/tru64/dump_mbuf.cc

@@ -40,6 +40,7 @@
 #include "base/types.hh"
 #include "config/the_isa.hh"
 #include "cpu/thread_context.hh"
+#include "kern/tru64/dump_mbuf.hh"
 #include "kern/tru64/mbuf.hh"
 #include "sim/arguments.hh"
 #include "sim/system.hh"

src/kern/tru64/printf.cc

@@ -36,6 +36,7 @@
 #include "base/cprintf.hh"
 #include "base/trace.hh"
 #include "base/types.hh"
+#include "kern/tru64/printf.hh"
 #include "sim/arguments.hh"
 
 using namespace std;

src/mem/ruby/buffers/MessageBuffer.hh

@@ -216,6 +216,8 @@ class MessageBuffer
     int m_vnet_id;
 };
 
+Cycles random_time();
+
 inline std::ostream&
 operator<<(std::ostream& out, const MessageBuffer& obj)
 {

src/mem/ruby/network/simple/PerfectSwitch.hh

@@ -53,6 +53,8 @@ struct LinkOrder
     int m_value;
 };
 
+bool operator<(const LinkOrder& l1, const LinkOrder& l2);
+
 class PerfectSwitch : public Consumer
 {
   public:

src/mem/ruby/profiler/AddressProfiler.hh

@@ -92,6 +92,14 @@ class AddressProfiler
     int m_num_of_sequencers;
 };
 
+AccessTraceForAddress& lookupTraceForAddress(const Address& addr,
+                                             AddressProfiler::AddressMap&
+                                             record_map);
+
+void printSorted(std::ostream& out, int num_of_sequencers,
+                 const AddressProfiler::AddressMap &record_map,
+                 std::string description);
+
 inline std::ostream&
 operator<<(std::ostream& out, const AddressProfiler& obj)
 {

src/mem/ruby/system/CacheMemory.hh

@@ -170,4 +170,6 @@ class CacheMemory : public SimObject
     bool m_resource_stalls;
 };
 
+std::ostream& operator<<(std::ostream& out, const CacheMemory& obj);
+
 #endif // __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__

src/mem/ruby/system/RubyMemoryControl.hh

@@ -168,4 +168,6 @@ class RubyMemoryControl : public MemoryControl
     MemCntrlProfiler* m_profiler_ptr;
 };
 
+std::ostream& operator<<(std::ostream& out, const RubyMemoryControl& obj);
+
 #endif // __MEM_RUBY_SYSTEM_MEMORY_CONTROL_HH__

src/mem/ruby/system/WireBuffer.hh

@@ -100,4 +100,6 @@ class WireBuffer : public SimObject
 
 };
 
+std::ostream& operator<<(std::ostream& out, const WireBuffer& obj);
+
 #endif // __MEM_RUBY_SYSTEM_WireBuffer_HH__

src/python/swig/pyobject.cc

@@ -35,10 +35,10 @@
 #include "base/inifile.hh"
 #include "base/output.hh"
 #include "dev/etherdevice.hh"
-#include "dev/etherint.hh"
 #include "dev/etherobject.hh"
 #include "mem/mem_object.hh"
 #include "mem/port.hh"
+#include "python/swig/pyobject.hh"
 #include "sim/full_system.hh"
 #include "sim/sim_object.hh"
 

src/python/swig/pyobject.hh

@@ -31,12 +31,15 @@
 #include <Python.h>
 
 #include "base/types.hh"
+#include "dev/etherint.hh"
 #include "sim/serialize.hh"
 #include "sim/sim_object.hh"
 
 extern "C" SimObject *convertSwigSimObjectPtr(PyObject *);
 SimObject *resolveSimObject(const std::string &name);
 
+EtherInt * lookupEthPort(SimObject *so, const std::string &name, int i);
+
 /**
  * Connect the described MemObject ports.  Called from Python via SWIG.
  */

src/sim/debug.hh

@@ -53,6 +53,8 @@ void takeCheckpoint(Tick when);
  */
 void eventqDump();
 
+void py_interact();
+
 int getRemoteGDBPort();
 // Remote gdb base port.  0 disables remote gdb.
 void setRemoteGDBPort(int port);

src/sim/drain.hh

@@ -236,4 +236,7 @@ class Drainable
 
 };
 
+DrainManager *createDrainManager();
+void cleanupDrainManager(DrainManager *drain_manager);
+
 #endif

src/sim/eventq.hh

@@ -418,6 +418,8 @@ class EventQueue : public Serializable
 #endif
 };
 
+void dumpMainQueue();
+
 #ifndef SWIG
 class EventManager
 {

src/sim/init.hh

@@ -31,6 +31,8 @@
 #ifndef __SIM_INIT_HH__
 #define __SIM_INIT_HH__
 
+#include <Python.h>
+
 /*
  * Data structure describing an embedded python file.
  */
@@ -74,8 +76,13 @@ struct EmbeddedSwig
     static void initAll();
 };
 
+void dumpStatsHandler(int sigtype);
+void dumprstStatsHandler(int sigtype);
+void exitNowHandler(int sigtype);
+void abortHandler(int sigtype);
 void initSignals();
 int initM5Python();
 int m5Main(int argc, char **argv);
+PyMODINIT_FUNC initm5(void);
 
 #endif // __SIM_INIT_HH__

src/sim/serialize.hh

@@ -178,6 +178,8 @@ class Serializable
     static void unserializeGlobals(Checkpoint *cp);
 };
 
+void debug_serialize(const std::string &cpt_dir);
+
 //
 // A SerializableBuilder serves as an evaluation context for a set of
 // parameters that describe a specific instance of a Serializable.  This

src/sim/sim_object.hh

@@ -176,4 +176,8 @@ class SimObject : public EventManager, public Serializable, public Drainable
     static SimObject *find(const char *name);
 };
 
+#ifdef DEBUG
+void debugObjectBreak(const char *objs);
+#endif
+
 #endif // __SIM_OBJECT_HH__

src/sim/stat_control.hh

@@ -46,6 +46,12 @@
 
 namespace Stats {
 
+double statElapsedTime();
+
+Tick statElapsedTicks();
+
+Tick statFinalTick();
+
 void initSimStats();
 
 /**

src/sim/system.hh

@@ -472,4 +472,6 @@ class System : public MemObject
 
 };
 
+void printSystems();
+
 #endif // __SYSTEM_HH__