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x86: Setup correct TSL/TR segment attributes on INIT

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The TSL/LDT & TR/TSS segments didn't contain valid attributes. This
caused problems when transfering the state into KVM where invalid
state is a no-go. Fixup the attributes with values from AMD's
architecture programmer's manual.
This commit is contained in:
Andreas Sandberg 2014-03-03 14:44:57 +01:00
parent e7d230ede0
commit be246cef62
1 changed files with 8 additions and 2 deletions
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10
src/arch/x86/faults.cc
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@ -245,15 +245,21 @@ namespace X86ISA
tc->setMiscReg(MISCREG_IDTR_BASE, 0);
tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
SegAttr tslAttr = 0;
tslAttr.present = 1;
tslAttr.type = 2; // LDT
tc->setMiscReg(MISCREG_TSL, 0);
tc->setMiscReg(MISCREG_TSL_BASE, 0);
tc->setMiscReg(MISCREG_TSL_LIMIT, 0xffff);
tc->setMiscReg(MISCREG_TSL_ATTR, 0);
tc->setMiscReg(MISCREG_TSL_ATTR, tslAttr);
SegAttr trAttr = 0;
trAttr.present = 1;
trAttr.type = 3; // Busy 16-bit TSS
tc->setMiscReg(MISCREG_TR, 0);
tc->setMiscReg(MISCREG_TR_BASE, 0);
tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff);
tc->setMiscReg(MISCREG_TR_ATTR, 0);
tc->setMiscReg(MISCREG_TR_ATTR, trAttr);
// This value should be the family/model/stepping of the processor.
// (page 418). It should be consistent with the value from CPUID, but