Commit graph

2681 commits

Author SHA1 Message Date
Kevin Lim
36581a5342 Faults generated at fetch are passed to the backend by creating a dummy nop instruction and giving it the fault. This unifies front end faults and normal instruction faults.
cpu/checker/cpu.cc:
    Fixups for fetch fault being sent with the instruction.
cpu/o3/fetch_impl.hh:
cpu/ozone/front_end_impl.hh:
    Send any faults generated at fetch along with a fake nop instruction to the back end.  This avoids having to use direct communication to check if the entire front end has drained; it is naturally handled through the nop's fault being handled when it reaches the head of commit.
cpu/ozone/front_end.hh:
    Add extra status TrapPending.
cpu/ozone/lw_back_end_impl.hh:
    Fetch fault handled through a dummy nop carrying the fetch fault.

    Avoid putting Nops on the exeList.

--HG--
extra : convert_revision : 8d9899748b34c204763a49c48a9b5113864f5789
2006-05-17 14:25:10 -04:00
Steve Reinhardt
343bff3b7d Backport ISA scanner fix from newmem to work with
scons 0.96.9* versions.

arch/SConscript:
    Backport ISA scanner fix from newmem.

--HG--
extra : convert_revision : 96be75660f85900fd26badef36fb4109b36d8394
2006-05-17 07:05:27 -04:00
Ali Saidi
5da14ec60a Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : efa962c4ea614e22e8964f6979cd7c9dcd4ee866
2006-05-16 23:58:37 -04:00
Ali Saidi
a873cd2ca1 add single fs newmem test
--HG--
extra : convert_revision : 895beeae44a36f585656e33a4a403dbedbe694ea
2006-05-16 23:58:31 -04:00
Steve Reinhardt
309e1d8193 Split SimpleCPU into two different models, AtomicSimpleCPU and
TimingSimpleCPU, which use atomic and timing memory accesses
respectively.  Common code is factored into the BaseSimpleCPU class.
AtomicSimpleCPU includes an option (simulate_stalls) to add delays
based on the estimated latency reported by the atomic accesses.
Plain old "SimpleCPU" is gone; I have not updated all the config
files (just test/test.py).
Also fixes to get timing accesses working in new memory model and
to get split-phase memory instruction definitions working with
new memory model as well.

arch/alpha/isa/main.isa:
    Need to include packet_impl.h for functions that use Packet objects.
arch/alpha/isa/mem.isa:
    Change completeAcc() methods to take Packet object pointers.
    Also split out StoreCond template for completeAcc(), since
    that's the only one that needs write_result and we get an
    unused variable warning if we always have it in there.
build/SConstruct:
    Update list of recognized CPU model names.
configs/test/test.py:
    Change SimpleCPU to AtomicSimpleCPU.
cpu/SConscript:
    Define sources for new CPU models.
    Add split memory access methods to CPU model signatures.
cpu/cpu_models.py:
cpu/static_inst.hh:
    Define new CPU models.
cpu/simple/base.cc:
cpu/simple/base.hh:
    Factor out pieces specific to Atomic or Timing models.
mem/bus.cc:
    Bus needs to be able to route timing packets based on explicit dest
    so responses can get back to requester.  Set dest to Packet::Broadcast
    to indicate that dest should be derived from address.
    Also set packet src field based on port from which packet is sent.
mem/bus.hh:
    Set packet src field based on port from which packet is sent.
mem/packet.hh:
    Define Broadcast destination address to indicate that
    packet should be routed based on address.
mem/physical.cc:
    Set packet dest on response so packet is routed
    back to requester properly.
mem/port.cc:
    Flag blob packets as Broadcast.
python/m5/objects/PhysicalMemory.py:
    Change default latency to be 1 cycle.

--HG--
rename : cpu/simple/cpu.cc => cpu/simple/base.cc
rename : cpu/simple/cpu.hh => cpu/simple/base.hh
extra : convert_revision : e9646af6406a20c8c605087936dc4683375c2132
2006-05-16 17:36:50 -04:00
Kevin Lim
aaf1969c78 Merge ktlim@zamp:/z/ktlim2/clean/m5-o3
into  zamp.eecs.umich.edu:/z/ktlim2/clean/m5-merge

--HG--
extra : convert_revision : 077a04edf0e3e4d735e88c9741d6742666e97de6
2006-05-16 15:30:36 -04:00
Kevin Lim
578777d48e Update configuration files.
--HG--
extra : convert_revision : f733bc68758d95987dfc481d48a4623c23b16ede
2006-05-16 15:25:46 -04:00
Kevin Lim
044f3998d0 Merge ktlim@zizzer:/bk/m5
into  zamp.eecs.umich.edu:/z/ktlim2/clean/m5-merge

--HG--
extra : convert_revision : 182df443376e5561d46f323d36089a2a49dc2024
2006-05-16 15:09:06 -04:00
Kevin Lim
abe14c253b Include checker and trap latency parameters.
--HG--
extra : convert_revision : 148c59f430874e8425952db6960ca4f5e57e2a42
2006-05-16 14:47:09 -04:00
Kevin Lim
52383ca7cc Sampler updates.
cpu/ozone/cpu.hh:
    Updates for sampler.
cpu/ozone/cpu_impl.hh:
    Updates for sampler, checker.
cpu/ozone/inorder_back_end.hh:
    Sampler updates.  Also support old memory system.

--HG--
extra : convert_revision : 33ebe38e4c08d49c6af84032b819533b784b4fe8
2006-05-16 14:09:04 -04:00
Kevin Lim
ef6e2eb3c4 Updates for sampler, checker, and general correctness.
cpu/o3/alpha_cpu.hh:
    Update for sampler to work properly.  Also code cleanup.
cpu/o3/alpha_cpu_builder.cc:
cpu/o3/alpha_dyn_inst.hh:
    Updates to support the checker.
cpu/o3/alpha_cpu_impl.hh:
    Updates to support the checker.  Also general code cleanup.
cpu/o3/alpha_dyn_inst_impl.hh:
    Code cleanup.
cpu/o3/alpha_params.hh:
    Updates to support the checker.  Also supports trap latencies set through the parameters.
cpu/o3/commit.hh:
    Supports sampler, checker.  Code cleanup.
cpu/o3/commit_impl.hh:
    Updates to support the sampler and checker, as well as general code cleanup.
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
    Support sampler and checker.
cpu/o3/decode_impl.hh:
    Supports sampler.
cpu/o3/fetch.hh:
    Supports sampler.  Also update to hold the youngest valid SN fetch has seen to ensure that the entire pipeline has been drained.
cpu/o3/fetch_impl.hh:
    Sampler updates.  Also be sure to not fetches to uncached space (bad path).
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
    Sampler updates.
cpu/o3/lsq_unit_impl.hh:
    Supports checker.
cpu/o3/regfile.hh:
    No need for accessing xcProxies directly.
cpu/o3/rename.hh:
cpu/o3/rename_impl.hh:
    Sampler support.

--HG--
extra : convert_revision : 03881885dd50ebbca13ef31f31492fd4ef59121c
2006-05-16 14:06:35 -04:00
Kevin Lim
c23b23f4e7 Add in checker. Supports dynamically verifying the execution of instructions, as well as limited amount of control path verification. It will verify anything within the program, but anything external (traps, interrupts, XC) it assumes is redirected properly by the CPU. Similarly it assumes the results of store conditionals, uncached loads, and instructions marked as "unverifiable" are correct from the CPU.
base/traceflags.py:
build/SConstruct:
cpu/SConscript:
cpu/cpu_models.py:
    Add in Checker.
cpu/base.cc:
    Add in checker support.  Also XC status starts off as suspended.
cpu/base.hh:
    Add in checker.

--HG--
extra : convert_revision : 091b5cc83e837858adb681ef0137a0beb30bd1b2
2006-05-16 13:59:29 -04:00
Kevin Lim
bd88385034 Sampler updates.
--HG--
extra : convert_revision : 9f88846d3e91ba725e1c2e0107568ba0f21f4638
2006-05-16 13:52:03 -04:00
Kevin Lim
989cc1735e Sampling fixes related to the quiesce event.
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
    Sampling fixes.  The CPU models may switch during a quiesce period, so it needs to be sure to wake up the right XC.
cpu/exec_context.hh:
    Return the EndQuiesceEvent specifically.
sim/pseudo_inst.cc:
    Return the EndQuiesceEvent specifically for sampling.

--HG--
extra : convert_revision : f9aa1fc8d4db8058f05319cb6a3d4605ce93b4c8
2006-05-16 13:51:18 -04:00
Kevin Lim
bfa9cc2c3a Add some flags for the upcoming checker.
arch/alpha/isa/decoder.isa:
    Mark store conditionals as serializing.  This is slightly higher over head than they truly have in the 264, but it's close.  Normally they block any other instructions from entering the IQ until the IQ is empty.  This is higher overhead because it waits until the ROB is empty.

    Also mark RPCC as unverifiable.  The checker will just grab the value from the instruction and assume it's correct.
cpu/static_inst.hh:
    Add unverifiable flag, specifically for the CheckerCPU.

--HG--
extra : convert_revision : cbc34d1f2f5b07105d31d4bd8f19edae2cf8158e
2006-05-16 13:48:05 -04:00
Steve Reinhardt
2db12b3d6c Many files:
Get rid of more unneeded includes.

base/hostinfo.cc:
base/inet.cc:
base/remote_gdb.cc:
cpu/simple/cpu.cc:
dev/alpha_console.cc:
dev/disk_image.cc:
dev/ns_gige.cc:
dev/sinic.cc:
mem/physical.cc:
sim/param.cc:
sim/process.cc:
sim/pseudo_inst.cc:
test/cprintftest.cc:
    Get rid of more unneeded includes.

--HG--
extra : convert_revision : f531ae40db3787f2c55df7d251f251ecae4ab731
2006-05-15 20:30:20 -04:00
Steve Reinhardt
2d9b7846c6 Many files:
Fix sstream includes

arch/alpha/tlb.cc:
base/cprintf.hh:
base/cprintf_formats.hh:
base/crc.cc:
base/statistics.cc:
base/statistics.hh:
base/stats/text.cc:
cpu/memtest/memtest.cc:
cpu/simple/cpu.cc:
dev/pcidev.cc:
sim/eventq.cc:
    Fix sstream includes

--HG--
extra : convert_revision : fd69937ea26b4961e92f1736fa44daa16f54698d
2006-05-15 20:06:42 -04:00
Ali Saidi
7d3eb0fe80 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

base/loader/elf_object.cc:
    removed SPARC32PLUS since it doesn't work.

--HG--
extra : convert_revision : 620a1c75cdeefbeeb97383d92335cf319d9c9444
2006-05-15 17:52:50 -04:00
Ali Saidi
a6266a99e2 Add support for sparc/solaris syscall emulation. Not tested yet because I can't get a static sparc 64 binary
arch/sparc/SConscript:
arch/sparc/process.cc:
base/loader/elf_object.cc:
    Add support for sparc/solaris syscall emulation.

--HG--
extra : convert_revision : e22df8476e5c6ae14db1cab1d94d01c0578ea06c
2006-05-15 17:37:03 -04:00
Ali Saidi
c7b26d015a fix typo, headers protection should be named __DIR_DIR_..._FILE_HH__
--HG--
extra : convert_revision : 18268bfcb8575a33659ae94b821e1f4cc9b7d821
2006-05-15 17:35:51 -04:00
Gabe Black
0a053c7919 Merge m5.eecs.umich.edu:/bk/newmem
into  ewok.(none):/home/gblack/m5/newmem

--HG--
extra : convert_revision : 2db5529a9fbe8c62e57cad05f093c915f9713c67
2006-05-14 23:58:23 -04:00
Gabe Black
149b724b86 Fixed some problems with signed vs. unsigned numbers which were breaking conditional moves and signed divisions. Also did some minor clean ups.
--HG--
extra : convert_revision : 6389ec18387a68ea5b675badfe1fd10cd30c264d
2006-05-14 23:57:21 -04:00
Gabe Black
42313f33ef Made the decoder handle reg_or_imm type arguments with type qualifiers.
--HG--
extra : convert_revision : f0ec58d754401fa6f3d64998355644882c5f5c96
2006-05-14 23:56:16 -04:00
Gabe Black
b91b877e9a Made EM_SPARC32PLUS be recognized as belonging to the SPARC architecture. Programs which have this set will not work because the stack works differently, so this should probably throw an error and quit.
--HG--
extra : convert_revision : b770045cad02d30445de0d7cc4d8c611a0ac931f
2006-05-14 23:55:07 -04:00
Gabe Black
9955ebd03c Moved the UnimpFault to be global
--HG--
extra : convert_revision : a42224c70c475c1559e83b8a2ef71ff3b792a3ab
2006-05-14 23:53:29 -04:00
Gabe Black
8db6dd370c Copied Korey's MIPS tests over to SPARC
--HG--
extra : convert_revision : bcfefd77c35245ce938ecb9bb46e97ad07377db8
2006-05-14 23:52:45 -04:00
Ali Saidi
0be3d001c9 Merge zeep.pool:/z/saidi/work/m5.head
into  zeep.pool:/z/saidi/work/m5.nm_m5_pull

--HG--
extra : convert_revision : fc90e4e8eefd78a3b7554e06fbc666965794753b
2006-05-12 18:51:42 -04:00
Ali Saidi
4644eab6d8 replace /.automount/ with /n/
--HG--
extra : convert_revision : 8b9ad49fa7e2e8863ebaf3f6709fc4fda62f2862
2006-05-12 18:51:23 -04:00
Ali Saidi
03a00e5d32 Merge zeep.pool:/z/saidi/work/m5.head
into  zeep.pool:/z/saidi/work/m5.nm_m5_pull

SConscript:
    dram memory needs to be converted to newmem before we can use it
dev/ide_ctrl.cc:
    don't need this printing in newmem
dev/ide_disk.cc:
    will read stats in next commit
dev/sinic.cc:
    merge sinic from head, still needs work

--HG--
extra : convert_revision : b9aabd8c7814d07d54ce6f971aad3ec349fa24e1
2006-05-12 18:16:07 -04:00
Ali Saidi
7929b9ee19 fix the checkpoint bug
--HG--
extra : convert_revision : 1ccae3282737d70b14ff86c8647e2e662a42c3bc
2006-05-12 17:47:23 -04:00
Korey Sewell
a91ee5abc2 FP programs are back to running... Condition Codes can be read and set...
Special Regs (Hi,Lo,FCSR) are now added to the operands for use in decoder.isa.

Now it's back to just debugging execution of code for the release (those unaligned
memory access instruction pairs are still quite the pain i might add)

arch/mips/isa_traits.hh:
    declare functions for .cc file
arch/mips/isa_traits.cc:
    delete unnecessary overloaded functions

    implement condition code functions

    implement round function
arch/mips/isa/base.isa:
    remove R31 constant... define in the operands.isa file instead
arch/mips/isa/decoder.isa:
    wholesale changes once again to FP.

    Now the FP Condition Codes are implemented and the FP programs can
    run and complete to finish.

    Use isnan() instead of my unorderedFP() function

    Also, we now access special regs such as HI,LO,FCSR,etc. just like we do any other reg. operand
arch/mips/isa/operands.isa:
    add more operands for special control regs in int and FP regfiles
arch/mips/isa/formats/branch.isa:
    use R31 instead of r31
arch/mips/isa/formats/fp.isa:
    use MakeCCVector to set Condition Codes in FCSR
arch/mips/regfile/float_regfile.hh:
    treat control regs like any other reg. Just Index them after the regular architectural registers
arch/mips/regfile/int_regfile.hh:
    treat hi,lo as regular int. regs w/special indexing
arch/mips/regfile/regfile.hh:
    no longer need for special register accesses with their own function.

--HG--
rename : arch/mips/regfile.hh => arch/mips/regfile/regfile.hh
extra : convert_revision : 5d2f8fdb59606de2b2e9db3e0a085240561e479e
2006-05-12 02:57:32 -04:00
Kevin Lim
21df09cf7a Fixes for ozone CPU to successfully boot and run linux.
cpu/base_dyn_inst.hh:
    Remove snoop function (did not mean to commit it).
cpu/ozone/back_end_impl.hh:
    Set instruction as having its result ready, not completed.
cpu/ozone/cpu.hh:
    Fixes for store conditionals.  Use an additional lock addr list to make sure that the access is valid.  I don't know if this is fully necessary, but it gives me a peace of mind (at some performance cost).
    Make sure to schedule for cycles(1) and not just 1 cycle in the future as tick = 1ps.
    Also support the new Checker.
cpu/ozone/cpu_builder.cc:
    Add parameter for maxOutstandingMemOps so it can be set through the config.
    Also add in the checker.  Right now it's a BaseCPU simobject, but that may change in the future.
cpu/ozone/cpu_impl.hh:
    Add support for the checker.  For now there's a dynamic cast to convert the simobject passed back from the builder to the proper Checker type.  It's ugly, but only happens at startup, and is probably a justified use of dynamic cast.

    Support switching out/taking over from other CPUs.

    Correct indexing problem for float registers.
cpu/ozone/dyn_inst.hh:
    Add ability for instructions to wait on memory instructions in addition to source register instructions.  This is needed for memory dependence predictors and memory barriers.
cpu/ozone/dyn_inst_impl.hh:
    Support waiting on memory operations.
    Use "resultReady" to differentiate an instruction having its registers produced vs being totally completed.
cpu/ozone/front_end.hh:
    Support switching out.
    Also record if an interrupt is pending.
cpu/ozone/front_end_impl.hh:
    Support switching out.  Also support stalling the front end if an interrupt is pending.
cpu/ozone/lw_back_end.hh:
    Add checker in.
    Support switching out.
    Support memory barriers.
cpu/ozone/lw_back_end_impl.hh:
    Lots of changes to get things to work right.
    Faults, traps, interrupts all wait until all stores have written back (important).
    Memory barriers are supported, as is the general ability for instructions to be dependent on other memory instructions.
cpu/ozone/lw_lsq.hh:
    Support switching out.
    Also use store writeback events in all cases, not just dcache misses.
cpu/ozone/lw_lsq_impl.hh:
    Support switching out.
    Also use store writeback events in all cases, not just dcache misses.
    Support the checker CPU.  Marks instructions as completed once the functional access is done (which has to be done for the checker to be able to verify results).
cpu/ozone/simple_params.hh:
    Add max outstanding mem ops parameter.
python/m5/objects/OzoneCPU.py:
    Add max outstanding mem ops, checker.

--HG--
extra : convert_revision : f4d408e1bb1f25836a097b6abe3856111e950c59
2006-05-11 19:18:36 -04:00
Ron Dreslinski
e5064e470c Initialize the count on the number of devices drained properly.
--HG--
extra : convert_revision : 80833647202985d1c1c7d23c6896831fcd27ff40
2006-05-11 17:26:11 -04:00
Ron Dreslinski
5cfff7d5bb First pass at a serializer object, may need to work on naming of object and functions:
Intended Use:
A SimObject will call the serializer when it needs the state to be serializable (i.e. switchCPUs, checkpoint, switch memory access model).  It will call the requestSeialization() function.
The Serializer will signal all the objects in its list to drain their state via the SimObject method drain().  Drain() has a default implementation to just signal done.
When each object is drained it will signal the Serializer that it has drained via the signalDrained() function.
The Serializer will collect these signals, when all have drained it will signal the initial requestor via serializationComplete() method in the SimObject.
Once that object is done, it will signal the Serializer to resumeExecution().
The Serializer will signal all the objects in its list to resume via the resume() method on the SimObject.

SConscript:
    Add serializer object to build list
sim/sim_object.cc:
    Add default behavior for drain (just signal finished, must be overided if you really must drain something)
sim/sim_object.hh:
    Add functions for serializer

--HG--
extra : convert_revision : 15aa2d1b42010c2d703bef9114c11d079c216170
2006-05-11 17:24:15 -04:00
Ali Saidi
d1e6f48203 make the dma buffer equal to the max dma size
--HG--
extra : convert_revision : 87adee6c2239f67976675c9291dc4fbaa4f67507
2006-05-11 17:19:17 -04:00
Ali Saidi
9892bdb342 ide printing to match newmem
--HG--
extra : convert_revision : ca6665bd93d257a8cf9d43600828ac22998c5810
2006-05-11 17:18:19 -04:00
Ali Saidi
1c5aa3f8cd make m5 panic a little more verbose
--HG--
extra : convert_revision : 32f52d829040c06c8a62cab1a7af1ed3b453b6f9
2006-05-11 17:17:47 -04:00
Kevin Lim
8a9416ef8d Small fixes to O3 model.
cpu/o3/alpha_dyn_inst.hh:
    Set the instResult using a function on the base dyn inst.
cpu/o3/bpred_unit_impl.hh:
    Don't need to reset the state.
cpu/o3/commit_impl.hh:
    Mark instructions as completed.

    Wait until all stores are written back to handle a fault.
cpu/o3/cpu.cc:
    Clear instruction lists when switching out.
cpu/o3/lsq_unit.hh:
    Allow wbEvent to be set externally.
cpu/o3/lsq_unit_impl.hh:
    Mark instructions as completed properly.  Also use events for writing back stores even if there is a hit in the dcache.

--HG--
extra : convert_revision : 172ad088b75ac31e848a5040633152b5c051444c
2006-05-11 15:39:02 -04:00
Kevin Lim
92838fd35e Set memory properly.
--HG--
extra : convert_revision : 4e6c61d31bf052bb4aabf4bb7a4f0e870b44b771
2006-05-11 15:19:48 -04:00
Kevin Lim
9a96ebf368 Separate out result being ready and the instruction being complete.
--HG--
extra : convert_revision : 9f17af114bf639f8fb61896e49fa714932c081d7
2006-05-11 14:12:34 -04:00
Korey Sewell
80dee53b04 Fixes for Paired-Single FP Compare Operations...
Now all the variations of FP should be implemented correctly in the decoder.
The new formats and functions supporting these functions need to be implemented for
some of the FP stuff but for the most part things are looking like their "supposed to"...

arch/mips/isa/decoder.isa:
    Fixes for Paired-Single FP Compare Operations...
    Now all the variations of FP should be implemented correctly in the decoder.
arch/mips/isa/formats/fp.isa:
    Add new PS formats
arch/mips/isa_traits.cc:
    Add skeleton overloaded round & truncate functions
arch/mips/isa_traits.hh:
    declare overloaded functions

--HG--
extra : convert_revision : 15d5cf7b08ac2dc9ebcd6b268e92d4abffdd8597
2006-05-11 03:26:19 -04:00
Korey Sewell
c552b06a8c Support for FP Paired Single Operations
Auxiliary Functions and Formats for FP in general

arch/mips/isa/decoder.isa:
    ISA Parser doesnt accept operands of different types in one instruction so fix this for unorderedFP functions...
    Add basic support for Paired Singled (PS) FP ops which happen to be part of the MIPS 32-ASE but turned out to
    be included in the MIPS32ISA manual... The PS instructions allow SIMD in a pipeline...
arch/mips/isa/formats/fp.isa:
    Add some more Formats for FP operation. I will add some auxiliary code through these formats
    to alleviate code redundancy in the decoder.isa
arch/mips/isa/operands.isa:
    Add operands for Paired Singles Ops
arch/mips/isa_traits.cc:
    removed convert&round function and replace with fpConvert.
    The whole "rounding mode" stuff is something that should be considered for full-system mode...

    Also added skeletons for the unorderedFP,truncFP,and condition code funcs.
arch/mips/isa_traits.hh:
    declare some Functions
arch/mips/types.hh:
    add new conversion types

--HG--
extra : convert_revision : 79251d590a27b74a3d6a62a2fbb937df3e59963f
2006-05-10 20:54:03 -04:00
Korey Sewell
45524e8f2d Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem

--HG--
extra : convert_revision : 0a146eed200abd2c18f135b112987c5cf91a649b
2006-05-10 18:34:26 -04:00
Korey Sewell
6375b7aca9 revamping code to appropriately handle FP condition code and conversion ops.
There still needs to be a work around to handle the paired singles operations ...

arch/mips/isa/decoder.isa:
    More revamping of the floating point ops in decoder.isa. Change all of the
    "convert and round" functions to fpConvert. Also, the utility functions
    roundFP, truncFP, and unorderedFP are in place everywhere. Things
    have been set up to appropriately use the FP condition codes in the decoder.isa
    The fp.isa format file and the isa_traits.cc file now needed to be updated
    to implement the appropriate "backend" operations/functionality...
arch/mips/isa_traits.hh:
    Remove convert & round functions
    Add roundFP, truncFP,unorderedFP, and the get/setFPconditionCode
    functions
arch/mips/isa_traits.cc:
    Add utility functions

--HG--
extra : convert_revision : 3d6708388abae5b432467f528d52e6343afecd9c
2006-05-10 16:52:27 -04:00
Korey Sewell
5aa47cdbd9 decoder.isa:
Now handles instructions for FP compares in single or double recision

arch/mips/isa/decoder.isa:
    Now handles instructions for FP compares in single or double recision

--HG--
extra : convert_revision : eb3a13616e6736bf2d1ead0b816dda8c6099b20f
2006-05-10 08:33:52 -04:00
Korey Sewell
01304f8935 decoder.isa:
Basic Code for Floating Point Compare with Single Precision Floats
Added.

arch/mips/isa/decoder.isa:
    Basic Code for Floating Point Compare with Single Precision Floats
    Added.

--HG--
extra : convert_revision : 56b14da1e9d987c2d2090fd2f79af8b12fe8d2ec
2006-05-09 15:18:36 -04:00
Korey Sewell
c01a43d302 decoder.isa:
Added support for FP compare instructions. Somehow these flew beneath
my radar. Also, I start to use special FP utility functions in FP code.
Right now, they are defined in isa_traits.hh but may be moved in the
future

arch/mips/isa/decoder.isa:
    Added support for FP compare instructions. Somehow these flew beneath
    my radar. Also, I start to use special FP utility functions in FP code.
    Right now, they are defined in isa_traits.hh but may be moved in the
    future

--HG--
extra : convert_revision : 84a3b66882f3977ce9c1356cf466d62a7fd8bf19
2006-05-09 14:39:45 -04:00
Steve Reinhardt
4758eb151f Print M5 build options for 'scons -h'.
--HG--
extra : convert_revision : 14ef62e513987b89e913e2bf9b8771ee086ed0a0
2006-05-09 12:43:01 -04:00
Korey Sewell
a4ed65d0fa Start working on more complex FP tests
Debug FP instructions to handle these FP insts

arch/mips/isa/bitfields.isa:
    add Bitfield for Floating Point Condition Codes
arch/mips/isa/decoder.isa:
    Follow instruction naming style with FP single insts
    Send the float value to the convert&round functions in single FP
    add ll inst support
    add 'token' sc support
arch/mips/isa_traits.cc:
    Add SINGLE->WORD, WORD->SINGLE, & WORD->DOUBLE conversions
arch/mips/regfile.hh:
    update header files
arch/mips/regfile/float_regfile.hh:
    Add more FP registers

--HG--
rename : arch/mips/int_regfile.hh => arch/mips/regfile/int_regfile.hh
rename : arch/mips/misc_regfile.hh => arch/mips/regfile/misc_regfile.hh
extra : convert_revision : 92faf0bfd8542ade762ac569ec158d198f6a9c7e
2006-05-08 03:59:40 -04:00
Korey Sewell
1047215ee5 First Steps in cleaning up MIPS code - This changeset rearranges the files in the MIPS directory by moving where constants/types/classes are defined
arch/mips/SConscript:
arch/mips/isa_traits.cc:
arch/mips/isa_traits.hh:
arch/mips/process.cc:
arch/mips/linux/linux.cc:
arch/mips/utility.hh:
arch/mips/linux/process.cc:
arch/mips/int_regfile.hh:
arch/mips/misc_regfile.hh:
arch/mips/regfile.hh:
arch/mips/types.hh:
    MIPS directory rearranging

--HG--
rename : arch/mips/mips_linux.cc => arch/mips/linux/linux.cc
rename : arch/mips/mips_linux.hh => arch/mips/linux/linux.hh
rename : arch/mips/linux_process.cc => arch/mips/linux/process.cc
rename : arch/mips/linux_process.hh => arch/mips/linux/process.hh
extra : convert_revision : 138eee48c8ed75efcf38572f335a556aaec38fc7
2006-05-07 18:50:41 -04:00