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First Steps in cleaning up MIPS code - This changeset rearranges the files in the MIPS directory by moving where constants/types/classes are defined

Browse source 
arch/mips/SConscript:
arch/mips/isa_traits.cc:
arch/mips/isa_traits.hh:
arch/mips/process.cc:
arch/mips/linux/linux.cc:
arch/mips/utility.hh:
arch/mips/linux/process.cc:
arch/mips/int_regfile.hh:
arch/mips/misc_regfile.hh:
arch/mips/regfile.hh:
arch/mips/types.hh:
    MIPS directory rearranging

--HG--
rename : arch/mips/mips_linux.cc => arch/mips/linux/linux.cc
rename : arch/mips/mips_linux.hh => arch/mips/linux/linux.hh
rename : arch/mips/linux_process.cc => arch/mips/linux/process.cc
rename : arch/mips/linux_process.hh => arch/mips/linux/process.hh
extra : convert_revision : 138eee48c8ed75efcf38572f335a556aaec38fc7
This commit is contained in:
Korey Sewell 2006-05-07 18:50:41 -04:00
parent 0930024b88
commit 1047215ee5
13 changed files with 607 additions and 948 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
arch/mips/SConscript
View file

@ -57,8 +57,8 @@ full_system_sources = Split('''
# Syscall emulation (non-full-system) sources
syscall_emulation_sources = Split('''
mips_linux.cc
linux_process.cc
linux/linux.cc
linux/process.cc
process.cc
''')

90
arch/mips/int_regfile.hh Normal file
View file

@ -0,0 +1,90 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARCH_MIPS_INT_REGFILE_HH__
#define __ARCH_MIPS_INT_REGFILE_HH__
#include "arch/mips/types.hh"
#include "arch/mips/constants.hh"
#include "sim/faults.hh"
class Checkpoint;
class ExecContext;
class Regfile;
namespace MipsISA
{
class IntRegFile
{
protected:
IntReg regs[NumIntRegs];
IntReg hi;
IntReg lo;
public:
IntReg readReg(int intReg)
{
return regs[intReg];
}
Fault setReg(int intReg, const IntReg &val)
{
regs[intReg] = val;
return NoFault;
}
IntReg readHi()
{
return hi;
}
Fault setHi(const IntReg &val)
{
hi = val;
return NoFault;
}
IntReg readLo()
{
return lo;
}
Fault setLo(const IntReg &val)
{
lo = val;
return NoFault;
}
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
};
} // namespace MipsISA
#endif

254
arch/mips/isa_traits.cc
View file

@ -35,6 +35,31 @@
using namespace MipsISA;
using namespace std;
void
MipsISA::copyRegs(ExecContext *src, ExecContext *dest)
{
/*fpcr = xc->readMiscReg(MipsISA::Fpcr_DepTag);
uniq = xc->readMiscReg(MipsISA::Uniq_DepTag);
lock_flag = xc->readMiscReg(MipsISA::Lock_Flag_DepTag);
lock_addr = xc->readMiscReg(MipsISA::Lock_Addr_DepTag);
#if FULL_SYSTEM
copyIprs(xc);
#endif*/
}
void
MipsISA::MiscRegFile::copyMiscRegs(ExecContext *xc)
{
/*fpcr = xc->readMiscReg(MipsISA::Fpcr_DepTag);
uniq = xc->readMiscReg(MipsISA::Uniq_DepTag);
lock_flag = xc->readMiscReg(MipsISA::Lock_Flag_DepTag);
lock_addr = xc->readMiscReg(MipsISA::Lock_Addr_DepTag);
#endif*/
}
uint64_t
MipsISA::convert_and_round(uint32_t fp_val, ConvertType cvt_type, int rnd_mode)
{
@ -111,236 +136,8 @@ MipsISA::convert_and_round(double fp_val, ConvertType cvt_type, int rnd_mode)
}
}
void
MipsISA::copyRegs(ExecContext *src, ExecContext *dest)
{
/*fpcr = xc->readMiscReg(MipsISA::Fpcr_DepTag);
uniq = xc->readMiscReg(MipsISA::Uniq_DepTag);
lock_flag = xc->readMiscReg(MipsISA::Lock_Flag_DepTag);
lock_addr = xc->readMiscReg(MipsISA::Lock_Addr_DepTag);
#if FULL_SYSTEM
copyIprs(xc);
#endif*/
}
void
MipsISA::MiscRegFile::copyMiscRegs(ExecContext *xc)
{
/*fpcr = xc->readMiscReg(MipsISA::Fpcr_DepTag);
uniq = xc->readMiscReg(MipsISA::Uniq_DepTag);
lock_flag = xc->readMiscReg(MipsISA::Lock_Flag_DepTag);
lock_addr = xc->readMiscReg(MipsISA::Lock_Addr_DepTag);
#if FULL_SYSTEM
copyIprs(xc);
#endif*/
}
void MipsISA::RegFile::coldReset()
{
//CP0 Random Reg:
//Randomly generated index into the TLB array
/*miscRegs[Random] = 0x0000003f;
//CP0 Wired Reg.
miscRegs[Wired] = 0x0000000;
//CP0 HWRENA
miscRegs[HWRena] = 0x0000000;
//CP0 Status Reg.
miscRegs[Status] = 0x0400004;
//CP0 INTCNTL
miscRegs[IntCtl] = 0xfc00000;
//CP0 SRSCNTL
miscRegs[SRSCtl] = 0x0c00000;
//CP0 SRSMAP
miscRegs[SRSMap] = 0x0000000;
//CP0 Cause
miscRegs[Cause] = 0x0000000;
//CP0 Processor ID
miscRegs[PrId] = 0x0019300;
//CP0 EBASE
miscRegs[EBase] = 0x8000000;
//CP0 Config Reg.
miscRegs[Config] = 0x80040482;
//CP0 Config 1 Reg.
miscRegs[Config1] = 0xfee3719e;
//CP0 Config 2 Reg.
miscRegs[Config2] = 0x8000000;
//CP0 Config 3 Reg.
miscRegs[Config3] = 0x0000020;
//CP0 Config 7 Reg.
miscRegs[Config7] = 0x0000000;
//CP0 Debug
miscRegs[Debug] = 0x0201800;
//CP0 PERFCNTL1
miscRegs[PerfCnt0] = 0x0000000;
//CP0 PERFCNTL2
miscRegs[PerfCnt1] = 0x0000000;*/
}
void RegFile::createCP0Regs()
{
//Resize Coprocessor Register Banks to
// the number specified in MIPS32K VOL.III
// Chapter 8
/*
//Cop-0 Regs. Bank 0: Index,
miscRegs[0].resize(4);
//Cop-0 Regs. Bank 1:
miscRegs[1].resize(8);
//Cop-0 Regs. Bank 2:
miscRegs[2].resize(8);
//Cop-0 Regs. Bank 3:
miscRegs[3].resize(1);
//Cop-0 Regs. Bank 4:
miscRegs[4].resize(2);
//Cop-0 Regs. Bank 5:
miscRegs[5].resize(2);
//Cop-0 Regs. Bank 6:
miscRegs[6].resize(6);
//Cop-0 Regs. Bank 7:
miscRegs[7].resize(1);
//Cop-0 Regs. Bank 8:
miscRegs[8].resize(1);
//Cop-0 Regs. Bank 9:
miscRegs[9].resize(1);
//Cop-0 Regs. Bank 10:
miscRegs[10].resize(1);
//Cop-0 Regs. Bank 11:
miscRegs[11].resize(1);
//Cop-0 Regs. Bank 12:
miscRegs[12].resize(4);
//Cop-0 Regs. Bank 13:
miscRegs[13].resize(1);
//Cop-0 Regs. Bank 14:
miscRegs[14].resize(1);
//Cop-0 Regs. Bank 15:
miscRegs[15].resize(2);
//Cop-0 Regs. Bank 16:
miscRegs[16].resize(4);
//Cop-0 Regs. Bank 17:
miscRegs[17].resize(1);
//Cop-0 Regs. Bank 18:
miscRegs[18].resize(8);
//Cop-0 Regs. Bank 19:
miscRegs[19].resize(8);
//Cop-0 Regs. Bank 20:
miscRegs[20].resize(1);
case PerfCnt0: panic("Accessing Unimplemented CP0 Register"); break;
case PerfCnt1: panic("Accessing Unimplemented CP0 Register"); break;
case PerfCnt2: panic("Accessing Unimplemented CP0 Register"); break;
case PerfCnt3: panic("Accessing Unimplemented CP0 Register"); break;
//Cop-0 Regs. Bank 21:
//miscRegs[21].resize(1);
//Reserved for future extensions
//Cop-0 Regs. Bank 22:
//miscRegs[22].resize(4);
//Available for implementation dependent use
//Cop-0 Regs. Bank 23:
miscRegs[23].resize(5);
//Cop-0 Regs. Bank 24:
miscRegs[24].resize(1);
//Cop-0 Regs. Bank 25:
miscRegs[25].resize(8);
//Cop-0 Regs. Bank 26:
miscRegs[26].resize(1);
//Cop-0 Regs. Bank 27:
miscRegs[27].resize(4);
//Cop-0 Regs. Bank 28:
miscRegs[28].resize(8);
//Cop-0 Regs. Bank 29:
miscRegs[29].resize(8);
//Cop-0 Regs. Bank 30:
miscRegs[30].resize(1);
//Cop-0 Regs. Bank 31:
miscRegs[31].resize(1);*/
}
const Addr MipsISA::PageShift = 13;
const Addr MipsISA::PageBytes = ULL(1) << PageShift;
const Addr MipsISA::PageMask = ~(PageBytes - 1);
const Addr MipsISA::PageOffset = PageBytes - 1;
#if FULL_SYSTEM
////////////////////////////////////////////////////////////////////////
//
// Translation stuff
//
const Addr MipsISA::PteShift = 3;
const Addr MipsISA::NPtePageShift = PageShift - PteShift;
const Addr MipsISA::NPtePage = ULL(1) << NPtePageShift;
const Addr MipsISA::PteMask = NPtePage - 1;
// User Virtual
const Addr MipsISA::USegBase = ULL(0x0);
const Addr MipsISA::USegEnd = ULL(0x000003ffffffffff);
// Kernel Direct Mapped
const Addr MipsISA::K0SegBase = ULL(0xfffffc0000000000);
const Addr MipsISA::K0SegEnd = ULL(0xfffffdffffffffff);
// Kernel Virtual
const Addr MipsISA::K1SegBase = ULL(0xfffffe0000000000);
const Addr MipsISA::K1SegEnd = ULL(0xffffffffffffffff);
#endif
// Mips UNOP (sll r0,r0,r0)
const MachInst MipsISA::NoopMachInst = 0x00000000;
static inline Addr
TruncPage(Addr addr)
@ -349,6 +146,7 @@ TruncPage(Addr addr)
static inline Addr
RoundPage(Addr addr)
{ return (addr + MipsISA::PageBytes - 1) & ~(MipsISA::PageBytes - 1); }
#endif
void
IntRegFile::serialize(std::ostream &os)

757
arch/mips/isa_traits.hh
View file

@ -29,8 +29,11 @@
#ifndef __ARCH_MIPS_ISA_TRAITS_HH__
#define __ARCH_MIPS_ISA_TRAITS_HH__
//#include "arch/mips/misc_regfile.hh"
#include "arch/mips/constants.hh"
#include "arch/mips/types.hh"
#include "arch/mips/regfile.hh"
#include "arch/mips/faults.hh"
#include "arch/mips/utility.hh"
#include "base/misc.hh"
#include "config/full_system.hh"
#include "sim/byteswap.hh"
@ -95,665 +98,21 @@ namespace MipsISA
{
using namespace LittleEndianGuest;
typedef uint32_t MachInst;
typedef uint32_t MachInst;
typedef uint64_t ExtMachInst;
typedef uint8_t RegIndex;
// typedef uint64_t Addr;
// Constants Related to the number of registers
const int NumIntArchRegs = 32;
const int NumPALShadowRegs = 8;
const int NumFloatArchRegs = 32;
// @todo: Figure out what this number really should be.
const int NumMiscArchRegs = 265;
const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
const int NumFloatRegs = NumFloatArchRegs;
const int NumMiscRegs = NumMiscArchRegs;
const int TotalNumRegs = NumIntRegs + NumFloatRegs +
NumMiscRegs + 0/*NumInternalProcRegs*/;
const int TotalDataRegs = NumIntRegs + NumFloatRegs;
// Static instruction parameters
const int MaxInstSrcRegs = 3;
const int MaxInstDestRegs = 2;
// semantically meaningful register indices
const int ZeroReg = 0;
const int AssemblerReg = 1;
const int ReturnValueReg1 = 2;
const int ReturnValueReg2 = 3;
const int ArgumentReg0 = 4;
const int ArgumentReg1 = 5;
const int ArgumentReg2 = 6;
const int ArgumentReg3 = 7;
const int KernelReg0 = 26;
const int KernelReg1 = 27;
const int GlobalPointerReg = 28;
const int StackPointerReg = 29;
const int FramePointerReg = 30;
const int ReturnAddressReg = 31;
const int SyscallNumReg = ReturnValueReg1;
const int SyscallPseudoReturnReg = ReturnValueReg1;
const int SyscallSuccessReg = ArgumentReg3;
const int LogVMPageSize = 13; // 8K bytes
const int VMPageSize = (1 << LogVMPageSize);
const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
const int MachineBytes = 4;
const int WordBytes = 4;
const int HalfwordBytes = 2;
const int ByteBytes = 1;
// These enumerate all the registers for dependence tracking.
enum DependenceTags {
// 0..31 are the integer regs 0..31
// 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
FP_Base_DepTag = 32,
Ctrl_Base_DepTag = 64,
Fpcr_DepTag = 64, // floating point control register
Uniq_DepTag = 65,
IPR_Base_DepTag = 66,
MiscReg_DepTag = 67
};
typedef uint64_t IntReg;
class IntRegFile
static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs)
{
protected:
IntReg regs[NumIntRegs];
public:
IntReg readReg(int intReg)
{
return regs[intReg];
if (return_value.successful()) {
// no error
regs->setIntReg(SyscallSuccessReg, 0);
regs->setIntReg(ReturnValueReg1, return_value.value());
} else {
// got an error, return details
regs->setIntReg(SyscallSuccessReg, (IntReg) -1);
regs->setIntReg(ReturnValueReg1, -return_value.value());
}
Fault setReg(int intReg, const IntReg &val)
{
regs[intReg] = val;
return NoFault;
}
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
};
typedef float FloatReg;
typedef double FPVal;
typedef uint32_t FloatReg32;
typedef uint64_t FloatReg64;
typedef uint64_t FloatRegBits;
// const uint64_t hi_mask64 = 0xFFFFFFFF00000000;
//const uint64_t lo_mask64 = 0x00000000FFFFFFFF;
const int SingleWidth = 32;
const int SingleBytes = 4;
const int DoubleWidth = 64;
const int DoubleBytes = 8;
const int QuadWidth = 128;
const int QuadBytes = QuadWidth / 4;
class FloatRegFile
{
protected:
FloatReg32 regs[NumFloatRegs];
public:
void clear()
{
bzero(regs, sizeof(regs));
}
double readReg(int floatReg, int width)
{
using namespace std;
switch(width)
{
case SingleWidth:
void *float_ptr = &regs[floatReg];
return *(float *) float_ptr;
case DoubleWidth:
uint64_t double_val = (FloatReg64)regs[floatReg + 1] << 32 | regs[floatReg];
void *double_ptr = &double_val;
return *(double *) double_ptr;
default:
panic("Attempted to read a %d bit floating point register!", width);
}
}
FloatRegBits readRegBits(int floatReg, int width)
{
using namespace std;
switch(width)
{
case SingleWidth:
return regs[floatReg];
case DoubleWidth:
return (FloatReg64)regs[floatReg + 1] << 32 | regs[floatReg];
default:
panic("Attempted to read a %d bit floating point register!", width);
}
}
Fault setReg(int floatReg, const FPVal &val, int width)
{
switch(width)
{
case SingleWidth:
float temp = val;
void *float_ptr = &temp;
regs[floatReg] = *(FloatReg32 *) float_ptr;
break;
case DoubleWidth:
const void *double_ptr = &val;
FloatReg64 temp_double = *(FloatReg64 *) double_ptr;
regs[floatReg + 1] = temp_double >> 32;
regs[floatReg] = temp_double;
break;
default:
panic("Attempted to read a %d bit floating point register!", width);
}
return NoFault;
}
Fault setRegBits(int floatReg, const FloatRegBits &val, int width)
{
using namespace std;
switch(width)
{
case SingleWidth:
regs[floatReg] = val;
break;
case DoubleWidth:
regs[floatReg + 1] = val >> 32;
regs[floatReg] = val;
break;
default:
panic("Attempted to read a %d bit floating point register!", width);
}
return NoFault;
}
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
};
enum ConvertType{
SINGLE_TO_DOUBLE,
SINGLE_TO_WORD,
SINGLE_TO_LONG,
DOUBLE_TO_SINGLE,
DOUBLE_TO_WORD,
DOUBLE_TO_LONG,
LONG_TO_SINGLE,
LONG_TO_DOUBLE,
LONG_TO_WORD,
WORD_TO_SINGLE,
WORD_TO_DOUBLE,
WORD_TO_LONG,
PLOWER_TO_SINGLE,
PUPPER_TO_SINGLE
};
enum RoundMode{
RND_ZERO,
RND_DOWN,
RND_UP,
RND_NEAREST
};
uint64_t convert_and_round(uint32_t fp_val,ConvertType cvt_type, int rnd_mode = 0);
uint64_t convert_and_round(uint64_t fp_val,ConvertType cvt_type, int rnd_mode = 0);
uint64_t convert_and_round(double fp_val,ConvertType cvt_type, int rnd_mode = 0);
void copyRegs(ExecContext *src, ExecContext *dest);
// cop-0/cop-1 system control register file
typedef uint64_t MiscReg;
//typedef MiscReg MiscRegFile[NumMiscRegs];
class MiscRegFile {
protected:
uint64_t fpcr; // floating point condition codes
uint64_t uniq; // process-unique register
bool lock_flag; // lock flag for LL/SC
Addr lock_addr; // lock address for LL/SC
MiscReg miscRegFile[NumMiscRegs];
public:
//These functions should be removed once the simplescalar cpu model
//has been replaced.
int getInstAsid();
int getDataAsid();
void copyMiscRegs(ExecContext *xc);
MiscReg readReg(int misc_reg)
{ return miscRegFile[misc_reg]; }
MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc)
{ return miscRegFile[misc_reg];}
Fault setReg(int misc_reg, const MiscReg &val)
{ miscRegFile[misc_reg] = val; return NoFault; }
Fault setRegWithEffect(int misc_reg, const MiscReg &val,
ExecContext *xc)
{ miscRegFile[misc_reg] = val; return NoFault; }
#if FULL_SYSTEM
void clearIprs() { }
protected:
InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
private:
MiscReg readIpr(int idx, Fault &fault, ExecContext *xc) { }
Fault setIpr(int idx, uint64_t val, ExecContext *xc) { }
#endif
friend class RegFile;
};
enum MiscRegTags {
//Coprocessor 0 Registers
//Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
//(Register Number-Register Select) Summary of Register
//------------------------------------------------------
Index = 0, //0-0 Index into the TLB array
MVPControl = 1, //0-1 Per-processor register containing global
//MIPS® MT configuration data
MVPConf0 = 2, //0-2 Per-processor register containing global
//MIPS® MT configuration data
MVPConf1 = 3, //0-3 Per-processor register containing global
//MIPS® MT configuration data
Random = 8, //1-0 Randomly generated index into the TLB array
VPEControl = 9, //1-1 Per-VPE register containing relatively volatile
//thread configuration data
VPEConf0 = 10, //1-2 Per-VPE multi-thread configuration
//information
VPEConf1 = 11, //1-2 Per-VPE multi-thread configuration
//information
YQMask = 12, //Per-VPE register defining which YIELD
//qualifier bits may be used without generating
//an exception
VPESchedule = 13,
VPEScheFBack = 14,
VPEOpt = 15,
EntryLo0 = 16, // Bank 3: 16 - 23
TCStatus = 17,
TCBind = 18,
TCRestart = 19,
TCHalt = 20,
TCContext = 21,
TCSchedule = 22,
TCScheFBack = 23,
EntryLo1 = 24,// Bank 4: 24 - 31
Context = 32, // Bank 5: 32 - 39
ContextConfig = 33,
//PageMask = 40, //Bank 6: 40 - 47
PageGrain = 41,
Wired = 48, //Bank 7:48 - 55
SRSConf0 = 49,
SRSConf1 = 50,
SRSConf2 = 51,
SRSConf3 = 52,
SRSConf4 = 53,
BadVAddr = 54,
HWRena = 56,//Bank 8:56 - 63
Count = 64, //Bank 9:64 - 71
EntryHi = 72,//Bank 10:72 - 79
Compare = 80,//Bank 11:80 - 87
Status = 88,//Bank 12:88 - 96 //12-0 Processor status and control
IntCtl = 89, //12-1 Interrupt system status and control
SRSCtl = 90, //12-2 Shadow register set status and control
SRSMap = 91, //12-3 Shadow set IPL mapping
Cause = 97,//97-104 //13-0 Cause of last general exception
EPC = 105,//105-112 //14-0 Program counter at last exception
PRId = 113,//113-120, //15-0 Processor identification and revision
EBase = 114, //15-1 Exception vector base register
Config = 121,//Bank 16: 121-128
Config1 = 122,
Config2 = 123,
Config3 = 124,
Config6 = 127,
Config7 = 128,
LLAddr = 129,//Bank 17: 129-136
WatchLo0 = 137,//Bank 18: 137-144
WatchLo1 = 138,
WatchLo2 = 139,
WatchLo3 = 140,
WatchLo4 = 141,
WatchLo5 = 142,
WatchLo6 = 143,
WatchLo7 = 144,
WatchHi0 = 145,//Bank 19: 145-152
WatchHi1 = 146,
WatchHi2 = 147,
WatchHi3 = 148,
WatchHi4 = 149,
WatchHi5 = 150,
WatchHi6 = 151,
WatchHi7 = 152,
XCContext64 = 153,//Bank 20: 153-160
//Bank 21: 161-168
//Bank 22: 169-176
Debug = 177, //Bank 23: 177-184
TraceControl1 = 178,
TraceControl2 = 179,
UserTraceData = 180,
TraceBPC = 181,
DEPC = 185,//Bank 24: 185-192
PerfCnt0 = 193,//Bank 25: 193 - 200
PerfCnt1 = 194,
PerfCnt2 = 195,
PerfCnt3 = 196,
PerfCnt4 = 197,
PerfCnt5 = 198,
PerfCnt6 = 199,
PerfCnt7 = 200,
ErrCtl = 201, //Bank 26: 201 - 208
CacheErr0 = 209, //Bank 27: 209 - 216
CacheErr1 = 210,
CacheErr2 = 211,
CacheErr3 = 212,
TagLo0 = 217,//Bank 28: 217 - 224
DataLo1 = 218,
TagLo2 = 219,
DataLo3 = 220,
TagLo4 = 221,
DataLo5 = 222,
TagLo6 = 223,
DataLo7 = 234,
TagHi0 = 233,//Bank 29: 233 - 240
DataHi1 = 234,
TagHi2 = 235,
DataHi3 = 236,
TagHi4 = 237,
DataHi5 = 238,
TagHi6 = 239,
DataHi7 = 240,
ErrorEPC = 249,//Bank 30: 241 - 248
DESAVE = 257,//Bank 31: 249-256
//More Misc. Regs
Hi,
Lo,
FIR,
FCSR,
FPCR,
//Alpha Regs, but here now, for
//compiling sake
UNIQ,
LockAddr,
LockFlag
};
extern const Addr PageShift;
extern const Addr PageBytes;
extern const Addr PageMask;
extern const Addr PageOffset;
#if FULL_SYSTEM
typedef uint64_t InternalProcReg;
#include "arch/mips/isa_fullsys_traits.hh"
#else
enum {
NumInternalProcRegs = 0
};
#endif
typedef union {
IntReg intreg;
FloatReg fpreg;
MiscReg ctrlreg;
} AnyReg;
class RegFile {
protected:
IntRegFile intRegFile; // (signed) integer register file
FloatRegFile floatRegFile; // floating point register file
MiscRegFile miscRegFile; // control register file
public:
void clear()
{
bzero(&intRegFile, sizeof(intRegFile));
bzero(&floatRegFile, sizeof(floatRegFile));
bzero(&miscRegFile, sizeof(miscRegFile));
}
MiscReg readMiscReg(int miscReg)
{
return miscRegFile.readReg(miscReg);
}
MiscReg readMiscRegWithEffect(int miscReg,
Fault &fault, ExecContext *xc)
{
fault = NoFault;
return miscRegFile.readRegWithEffect(miscReg, fault, xc);
}
Fault setMiscReg(int miscReg, const MiscReg &val)
{
return miscRegFile.setReg(miscReg, val);
}
Fault setMiscRegWithEffect(int miscReg, const MiscReg &val,
ExecContext * xc)
{
return miscRegFile.setRegWithEffect(miscReg, val, xc);
}
FloatReg readFloatReg(int floatReg)
{
return floatRegFile.readReg(floatReg,SingleWidth);
}
FloatReg readFloatReg(int floatReg, int width)
{
return floatRegFile.readReg(floatReg,width);
}
FloatRegBits readFloatRegBits(int floatReg)
{
return floatRegFile.readRegBits(floatReg,SingleWidth);
}
FloatRegBits readFloatRegBits(int floatReg, int width)
{
return floatRegFile.readRegBits(floatReg,width);
}
Fault setFloatReg(int floatReg, const FloatReg &val)
{
return floatRegFile.setReg(floatReg, val, SingleWidth);
}
Fault setFloatReg(int floatReg, const FloatReg &val, int width)
{
return floatRegFile.setReg(floatReg, val, width);
}
Fault setFloatRegBits(int floatReg, const FloatRegBits &val)
{
return floatRegFile.setRegBits(floatReg, val, SingleWidth);
}
Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
{
return floatRegFile.setRegBits(floatReg, val, width);
}
IntReg readIntReg(int intReg)
{
return intRegFile.readReg(intReg);
}
Fault setIntReg(int intReg, const IntReg &val)
{
return intRegFile.setReg(intReg, val);
}
protected:
Addr pc; // program counter
Addr npc; // next-cycle program counter
Addr nnpc; // next-next-cycle program counter
// used to implement branch delay slot
// not real register
public:
Addr readPC()
{
return pc;
}
void setPC(Addr val)
{
pc = val;
}
Addr readNextPC()
{
return npc;
}
void setNextPC(Addr val)
{
npc = val;
}
Addr readNextNPC()
{
return nnpc;
}
void setNextNPC(Addr val)
{
nnpc = val;
}
MiscReg hi; // MIPS HI Register
MiscReg lo; // MIPS LO Register
#if FULL_SYSTEM
IntReg palregs[NumIntRegs]; // PAL shadow registers
InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
int intrflag; // interrupt flag
bool pal_shadow; // using pal_shadow registers
inline int instAsid() { return MIPS34K::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); }
inline int dataAsid() { return MIPS34K::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); }
#endif // FULL_SYSTEM
//void initCP0Regs();
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
void createCP0Regs();
void coldReset();
typedef int ContextParam;
typedef int ContextVal;
void changeContext(ContextParam param, ContextVal val)
{
}
};
}
StaticInstPtr decodeInst(ExtMachInst);
// return a no-op instruction... used for instruction fetch faults
extern const MachInst NoopMachInst;
enum annotes {
ANNOTE_NONE = 0,
// An impossible number for instruction annotations
ITOUCH_ANNOTE = 0xffffffff,
};
//void getMiscRegIdx(int reg_name,int &idx, int &sel);
static inline ExtMachInst
makeExtMI(MachInst inst, const uint64_t &pc) {
#if FULL_SYSTEM
@ -767,25 +126,38 @@ extern const Addr PageOffset;
#endif
}
static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
panic("register classification not implemented");
return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
}
/**
* Function to insure ISA semantics about 0 registers.
* @param xc The execution context.
*/
template <class XC>
void zeroRegisters(XC *xc);
static inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
panic("register classification not implemented");
return (reg >= 9 && reg <= 15);
}
const Addr MaxAddr = (Addr)-1;
static inline bool isCallerSaveFloatRegister(unsigned int reg) {
panic("register classification not implemented");
return false;
}
void copyRegs(ExecContext *src, ExecContext *dest);
static inline bool isCalleeSaveFloatRegister(unsigned int reg) {
panic("register classification not implemented");
return false;
}
uint64_t convert_and_round(uint32_t fp_val, ConvertType cvt_type, int rnd_mode = 0);
uint64_t convert_and_round(uint64_t fp_val, ConvertType cvt_type, int rnd_mode = 0);
uint64_t convert_and_round(double fp_val, ConvertType cvt_type, int rnd_mode = 0);
// Machine operations
void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
int regnum);
void restoreMachineReg(RegFile &regs, const AnyReg &reg,
int regnum);
#if 0
static void serializeSpecialRegs(const Serializable::Proxy &proxy,
const RegFile &regs);
static void unserializeSpecialRegs(const IniFile *db,
const std::string &category,
ConfigNode *node,
RegFile &regs);
#endif
static inline Addr alignAddress(const Addr &addr,
unsigned int nbytes) {
@ -812,53 +184,12 @@ extern const Addr PageOffset;
return 0;
}
static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs)
{
if (return_value.successful()) {
// no error
regs->setIntReg(SyscallSuccessReg, 0);
regs->setIntReg(ReturnValueReg1, return_value.value());
} else {
// got an error, return details
regs->setIntReg(SyscallSuccessReg, (IntReg) -1);
regs->setIntReg(ReturnValueReg1, -return_value.value());
}
}
// Machine operations
void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
int regnum);
void restoreMachineReg(RegFile &regs, const AnyReg &reg,
int regnum);
#if 0
static void serializeSpecialRegs(const Serializable::Proxy &proxy,
const RegFile &regs);
static void unserializeSpecialRegs(const IniFile *db,
const std::string &category,
ConfigNode *node,
RegFile &regs);
#endif
/**
* Function to insure ISA semantics about 0 registers.
* @param xc The execution context.
*/
template <class XC>
void zeroRegisters(XC *xc);
const Addr MaxAddr = (Addr)-1;
};
#if FULL_SYSTEM
//typedef TheISA::InternalProcReg InternalProcReg;
//const int NumInternalProcRegs = TheISA::NumInternalProcRegs;
//const int NumInterruptLevels = TheISA::NumInterruptLevels;
#include "arch/mips/mips34k.hh"
#endif
using namespace MipsISA;

2
arch/mips/mips_linux.cc → arch/mips/linux/linux.cc
View file

@ -26,7 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "arch/mips/mips_linux.hh"
#include "arch/mips/linux/linux.hh"
// open(2) flags translation table
OpenFlagTransTable MipsLinux::openFlagTable[] = {

0
arch/mips/mips_linux.hh → arch/mips/linux/linux.hh
View file

4
arch/mips/linux_process.cc → arch/mips/linux/process.cc
View file

@ -26,8 +26,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "arch/mips/mips_linux.hh"
#include "arch/mips/linux_process.hh"
#include "arch/mips/linux/linux.hh"
#include "arch/mips/linux/process.hh"
#include "arch/mips/isa_traits.hh"
#include "base/trace.hh"

0
arch/mips/linux_process.hh → arch/mips/linux/process.hh
View file

96
arch/mips/misc_regfile.hh Normal file
View file

@ -0,0 +1,96 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARCH_MIPS_MISC_REGFILE_HH__
#define __ARCH_MIPS_MISC_REGFILE_HH__
#include "arch/mips/types.hh"
#include "arch/mips/constants.hh"
#include "sim/faults.hh"
class Checkpoint;
class ExecContext;
class Regfile;
namespace MipsISA
{
class MiscRegFile {
protected:
uint64_t fpcr; // floating point condition codes
uint64_t uniq; // process-unique register
bool lock_flag; // lock flag for LL/SC
Addr lock_addr; // lock address for LL/SC
MiscReg miscRegFile[NumMiscRegs];
public:
//These functions should be removed once the simplescalar cpu model
//has been replaced.
int getInstAsid();
int getDataAsid();
void copyMiscRegs(ExecContext *xc);
MiscReg readReg(int misc_reg)
{
return miscRegFile[misc_reg];
}
MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc)
{
return miscRegFile[misc_reg];
}
Fault setReg(int misc_reg, const MiscReg &val)
{
miscRegFile[misc_reg] = val; return NoFault;
}
Fault setRegWithEffect(int misc_reg, const MiscReg &val,
ExecContext *xc)
{
miscRegFile[misc_reg] = val; return NoFault;
}
#if FULL_SYSTEM
void clearIprs() { }
protected:
InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
private:
MiscReg readIpr(int idx, Fault &fault, ExecContext *xc) { }
Fault setIpr(int idx, uint64_t val, ExecContext *xc) { }
#endif
friend class RegFile;
};
} // namespace MipsISA
#endif

2
arch/mips/process.cc
View file

@ -28,7 +28,7 @@
#include "arch/mips/isa_traits.hh"
#include "arch/mips/process.hh"
#include "arch/mips/linux_process.hh"
#include "arch/mips/linux/process.hh"
#include "base/loader/object_file.hh"
#include "base/misc.hh"
#include "cpu/exec_context.hh"

247
arch/mips/regfile.hh Normal file
View file

@ -0,0 +1,247 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARCH_MIPS_REGFILE_HH__
#define __ARCH_MIPS_REGFILE_HH__
#include "arch/mips/types.hh"
#include "arch/mips/constants.hh"
#include "arch/mips/int_regfile.hh"
#include "arch/mips/float_regfile.hh"
#include "arch/mips/misc_regfile.hh"
#include "sim/faults.hh"
class Checkpoint;
class ExecContext;
namespace MipsISA
{
class RegFile {
protected:
IntRegFile intRegFile; // (signed) integer register file
FloatRegFile floatRegFile; // floating point register file
MiscRegFile miscRegFile; // control register file
public:
void clear()
{
bzero(&intRegFile, sizeof(intRegFile));
bzero(&floatRegFile, sizeof(floatRegFile));
bzero(&miscRegFile, sizeof(miscRegFile));
}
MiscReg readMiscReg(int miscReg)
{
if (miscReg < CtrlReg_DepTag)
return miscRegFile.readReg(miscReg);
else {
switch (miscReg)
{
case Hi:
return intRegFile.readHi();
case Lo:
return intRegFile.readLo();
case FIR:
return floatRegFile.readFIR();
case FCSR:
return floatRegFile.readFCSR();
case FPCR:
return floatRegFile.readFPCR();
default:
panic("Invalid Misc. Reg. Access\n");
return 0;
}
}
}
MiscReg readMiscRegWithEffect(int miscReg,
Fault &fault, ExecContext *xc)
{
fault = NoFault;
return miscRegFile.readRegWithEffect(miscReg, fault, xc);
}
Fault setMiscReg(int miscReg, const MiscReg &val)
{
if (miscReg < CtrlReg_DepTag)
return miscRegFile.setReg(miscReg, val);
else {
switch (miscReg)
{
case Hi:
return intRegFile.setHi(val);
case Lo:
return intRegFile.setLo(val);
case FIR:
return floatRegFile.setFIR(val);
case FCSR:
return floatRegFile.setFCSR(val);
case FPCR:
return floatRegFile.setFPCR(val);
default:
panic("Invalid Misc. Reg. Access\n");
return 0;
}
}
}
Fault setMiscRegWithEffect(int miscReg, const MiscReg &val,
ExecContext * xc)
{
return miscRegFile.setRegWithEffect(miscReg, val, xc);
}
FloatReg readFloatReg(int floatReg)
{
return floatRegFile.readReg(floatReg,SingleWidth);
}
FloatReg readFloatReg(int floatReg, int width)
{
return floatRegFile.readReg(floatReg,width);
}
FloatRegBits readFloatRegBits(int floatReg)
{
return floatRegFile.readRegBits(floatReg,SingleWidth);
}
FloatRegBits readFloatRegBits(int floatReg, int width)
{
return floatRegFile.readRegBits(floatReg,width);
}
Fault setFloatReg(int floatReg, const FloatReg &val)
{
return floatRegFile.setReg(floatReg, val, SingleWidth);
}
Fault setFloatReg(int floatReg, const FloatReg &val, int width)
{
return floatRegFile.setReg(floatReg, val, width);
}
Fault setFloatRegBits(int floatReg, const FloatRegBits &val)
{
return floatRegFile.setRegBits(floatReg, val, SingleWidth);
}
Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
{
return floatRegFile.setRegBits(floatReg, val, width);
}
IntReg readIntReg(int intReg)
{
return intRegFile.readReg(intReg);
}
Fault setIntReg(int intReg, const IntReg &val)
{
return intRegFile.setReg(intReg, val);
}
protected:
Addr pc; // program counter
Addr npc; // next-cycle program counter
Addr nnpc; // next-next-cycle program counter
// used to implement branch delay slot
// not real register
public:
Addr readPC()
{
return pc;
}
void setPC(Addr val)
{
pc = val;
}
Addr readNextPC()
{
return npc;
}
void setNextPC(Addr val)
{
npc = val;
}
Addr readNextNPC()
{
return nnpc;
}
void setNextNPC(Addr val)
{
nnpc = val;
}
#if FULL_SYSTEM
IntReg palregs[NumIntRegs]; // PAL shadow registers
InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
int intrflag; // interrupt flag
bool pal_shadow; // using pal_shadow registers
inline int instAsid() { return MIPS34K::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); }
inline int dataAsid() { return MIPS34K::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); }
#endif // FULL_SYSTEM
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
typedef int ContextParam;
typedef int ContextVal;
void changeContext(ContextParam param, ContextVal val)
{
}
};
void copyRegs(ExecContext *src, ExecContext *dest);
void copyMiscRegs(ExecContext *src, ExecContext *dest);
#if FULL_SYSTEM
void copyIprs(ExecContext *src, ExecContext *dest);
#endif
} // namespace MipsISA
#endif

90
arch/mips/types.hh Normal file
View file

@ -0,0 +1,90 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARCH_MIPS_TYPES_HH__
#define __ARCH_MIPS_TYPES_HH__
#include "sim/host.hh"
namespace MipsISA
{
typedef uint32_t MachInst;
typedef uint64_t ExtMachInst;
typedef uint8_t RegIndex;
typedef uint32_t IntReg;
// floating point register file entry type
typedef double FloatReg;
typedef uint32_t FloatReg32;
typedef uint64_t FloatReg64;
typedef uint64_t FloatRegBits;
// cop-0/cop-1 system control register
typedef uint64_t MiscReg;
typedef uint64_t InternalProcReg;
typedef union {
IntReg intreg;
FloatReg fpreg;
MiscReg ctrlreg;
} AnyReg;
//used in FP convert & round function
enum ConvertType{
SINGLE_TO_DOUBLE,
SINGLE_TO_WORD,
SINGLE_TO_LONG,
DOUBLE_TO_SINGLE,
DOUBLE_TO_WORD,
DOUBLE_TO_LONG,
LONG_TO_SINGLE,
LONG_TO_DOUBLE,
LONG_TO_WORD,
WORD_TO_SINGLE,
WORD_TO_DOUBLE,
WORD_TO_LONG,
PLOWER_TO_SINGLE,
PUPPER_TO_SINGLE
};
//used in FP convert & round function
enum RoundMode{
RND_ZERO,
RND_DOWN,
RND_UP,
RND_NEAREST
};
} // namespace MipsISA
#endif

9
arch/mips/utility.hh
View file

@ -29,6 +29,13 @@
#ifndef __ARCH_MIPS_UTILITY_HH__
#define __ARCH_MIPS_UTILITY_HH__
//Placeholder file for now
#include "arch/mips/types.hh"
#include "arch/mips/constants.hh"
#include "base/misc.hh"
#include "sim/host.hh"
namespace MipsISA {
};
#endif