Faults generated at fetch are passed to the backend by creating a dummy nop instruction and giving it the fault. This unifies front end faults and normal instruction faults.
cpu/checker/cpu.cc: Fixups for fetch fault being sent with the instruction. cpu/o3/fetch_impl.hh: cpu/ozone/front_end_impl.hh: Send any faults generated at fetch along with a fake nop instruction to the back end. This avoids having to use direct communication to check if the entire front end has drained; it is naturally handled through the nop's fault being handled when it reaches the head of commit. cpu/ozone/front_end.hh: Add extra status TrapPending. cpu/ozone/lw_back_end_impl.hh: Fetch fault handled through a dummy nop carrying the fetch fault. Avoid putting Nops on the exeList. --HG-- extra : convert_revision : 8d9899748b34c204763a49c48a9b5113864f5789
This commit is contained in:
parent
343bff3b7d
commit
36581a5342
5 changed files with 99 additions and 100 deletions
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@ -607,41 +607,46 @@ Checker<DynInstPtr>::tick(DynInstPtr &completed_inst)
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bool succeeded = translateInstReq(memReq);
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if (!succeeded) {
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warn("Instruction PC %#x was not found in the ITB!",
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cpuXC->readPC());
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handleError();
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if (inst->getFault() == NoFault) {
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warn("Instruction PC %#x was not found in the ITB!",
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cpuXC->readPC());
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handleError();
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// go to the next instruction
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cpuXC->setPC(cpuXC->readNextPC());
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cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst));
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// go to the next instruction
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cpuXC->setPC(cpuXC->readNextPC());
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cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst));
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return;
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return;
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} else {
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fault = inst->getFault();
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}
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}
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// if (fault == NoFault)
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if (fault == NoFault) {
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// fault = cpuXC->mem->read(memReq, machInst);
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cpuXC->mem->read(memReq, machInst);
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cpuXC->mem->read(memReq, machInst);
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// If we've got a valid instruction (i.e., no fault on instruction
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// fetch), then execute it.
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// If we've got a valid instruction (i.e., no fault on instruction
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// fetch), then execute it.
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// keep an instruction count
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numInst++;
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numInst++;
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// numInsts++;
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// decode the instruction
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machInst = gtoh(machInst);
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// Checks that the instruction matches what we expected it to be.
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// Checks both the machine instruction and the PC.
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validateInst(inst);
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// decode the instruction
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machInst = gtoh(machInst);
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// Checks that the instruction matches what we expected it to be.
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// Checks both the machine instruction and the PC.
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validateInst(inst);
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curStaticInst = StaticInst::decode(makeExtMI(machInst, cpuXC->readPC()));
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curStaticInst = StaticInst::decode(makeExtMI(machInst, cpuXC->readPC()));
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#if FULL_SYSTEM
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cpuXC->setInst(machInst);
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cpuXC->setInst(machInst);
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#endif // FULL_SYSTEM
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fault = inst->getFault();
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fault = inst->getFault();
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}
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// Either the instruction was a fault and we should process the fault,
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// or we should just go ahead execute the instruction. This assumes
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -27,22 +27,21 @@
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*/
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#include "arch/isa_traits.hh"
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#include "sim/byteswap.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/o3/fetch.hh"
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#include "mem/base_mem.hh"
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#include "mem/mem_interface.hh"
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#include "mem/mem_req.hh"
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#include "sim/byteswap.hh"
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#include "sim/root.hh"
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#if FULL_SYSTEM
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#include "arch/tlb.hh"
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#include "arch/vtophys.hh"
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#include "base/remote_gdb.hh"
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#include "mem/functional/memory_control.hh"
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#include "mem/functional/physical.hh"
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#include "sim/system.hh"
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#include "arch/tlb.hh"
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#include "arch/vtophys.hh"
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#else // !FULL_SYSTEM
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#include "mem/functional/functional.hh"
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#endif // FULL_SYSTEM
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@ -136,14 +135,7 @@ DefaultFetch<Impl>::DefaultFetch(Params *params)
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// Create a new memory request.
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memReq[tid] = NULL;
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// memReq[tid] = new MemReq();
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/*
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// Need a way of setting this correctly for parallel programs
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// @todo: Figure out how to properly set asid vs thread_num.
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memReq[tid]->asid = tid;
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memReq[tid]->thread_num = tid;
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memReq[tid]->data = new uint8_t[64];
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*/
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// Create space to store a cache line.
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cacheData[tid] = new uint8_t[cacheBlkSize];
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@ -261,10 +253,6 @@ DefaultFetch<Impl>::setCPU(FullCPU *cpu_ptr)
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DPRINTF(Fetch, "Setting the CPU pointer.\n");
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cpu = cpu_ptr;
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// Set ExecContexts for Memory Requests
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// for (int tid=0; tid < numThreads; tid++)
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// memReq[tid]->xc = cpu->xcBase(tid);
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// Fetch needs to start fetching instructions at the very beginning,
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// so it must start up in active state.
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switchToActive();
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@ -362,9 +350,8 @@ DefaultFetch<Impl>::processCacheCompletion(MemReqPtr &req)
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// memcpy(cacheData[tid], memReq[tid]->data, memReq[tid]->size);
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// Reset the completion event to NULL.
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// Reset the mem req to NULL.
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memReq[tid] = NULL;
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// memReq[tid]->completionEvent = NULL;
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}
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template <class Impl>
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@ -468,10 +455,6 @@ template <class Impl>
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bool
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DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid)
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{
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// Check if the instruction exists within the cache.
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// If it does, then proceed on to read the instruction and the rest
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// of the instructions in the cache line until either the end of the
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// cache line or a predicted taken branch is encountered.
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Fault fault = NoFault;
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#if FULL_SYSTEM
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@ -509,7 +492,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
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//#endif
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// In the case of faults, the fetch stage may need to stall and wait
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// on what caused the fetch (ITB or Icache miss).
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// for the ITB miss to be handled.
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// If translation was successful, attempt to read the first
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// instruction.
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@ -518,7 +501,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
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if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) ||
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memReq[tid]->flags & UNCACHEABLE) {
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DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a "
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"misspeculating path!",
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"misspeculating path)!",
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memReq[tid]->paddr);
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ret_fault = TheISA::genMachineCheckFault();
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return false;
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@ -587,44 +570,9 @@ DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid)
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if (fetchStatus[tid] == IcacheMissStall && icacheInterface) {
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DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
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tid);
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// icacheInterface->squash(tid);
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/*
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if (memReq[tid]->completionEvent) {
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if (memReq[tid]->completionEvent->scheduled()) {
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memReq[tid]->completionEvent->squash();
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} else {
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delete memReq[tid]->completionEvent;
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memReq[tid]->completionEvent = NULL;
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}
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}
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*/
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memReq[tid] = NULL;
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}
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if (fetchStatus[tid] == TrapPending) {
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// @todo: Hardcoded number here
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// This is only effective if communication to and from commit
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// is identical. If it's faster to commit than it is from
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// commit to here, then it causes problems.
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bool found_fault = false;
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for (int i = 0; i > -5; --i) {
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if (fetchQueue->access(i)->fetchFault) {
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DPRINTF(Fetch, "[tid:%i]: Fetch used to be in a trap, "
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"clearing it.\n",
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tid);
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fetchQueue->access(i)->fetchFault = NoFault;
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found_fault = true;
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}
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}
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if (!found_fault) {
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warn("%lli Fault from fetch not found in time buffer!",
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curTick);
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}
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toDecode->clearFetchFault = true;
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}
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fetchStatus[tid] = Squashing;
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++fetchSquashCycles;
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@ -643,7 +591,6 @@ DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC,
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// Tell the CPU to remove any instructions that are in flight between
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// fetch and decode.
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cpu->removeInstsUntil(seq_num, tid);
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youngestSN = seq_num;
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}
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template<class Impl>
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// In any case, squash.
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squash(fromCommit->commitInfo[tid].nextPC,tid);
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youngestSN = fromCommit->commitInfo[tid].doneSeqNum;
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// Also check if there's a mispredict that happened.
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if (fromCommit->commitInfo[tid].branchMispredict) {
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@ -1009,8 +955,6 @@ DefaultFetch<Impl>::fetch(bool &status_change)
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// Get a sequence number.
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inst_seq = cpu->getAndIncrementInstSeq();
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youngestSN = inst_seq;
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// Make sure this is a valid index.
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assert(offset <= cacheBlkSize - instSize);
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// This stage will not be able to continue until all the ROB
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// slots are empty, at which point the fault can be handled.
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// The only other way it can wake up is if a squash comes along
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// and changes the PC. Not sure how to handle that case...perhaps
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// have it handled by the upper level CPU class which peeks into the
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// time buffer and sees if a squash comes along, in which case it
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// changes the status.
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// and changes the PC.
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#if FULL_SYSTEM
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assert(numInst != fetchWidth);
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// Get a sequence number.
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inst_seq = cpu->getAndIncrementInstSeq();
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// We will use a nop in order to carry the fault.
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ext_inst = TheISA::NoopMachInst;
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// Create a new DynInst from the dummy nop.
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DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
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next_PC,
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inst_seq, cpu);
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instruction->setPredTarg(next_PC + instSize);
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instruction->setThread(tid);
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instruction->setASID(tid);
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instruction->setState(cpu->thread[tid]);
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instruction->traceData = NULL;
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instruction->setInstListIt(cpu->addInst(instruction));
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instruction->fault = fault;
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toDecode->insts[numInst] = instruction;
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toDecode->size++;
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// Tell the commit stage the fault we had.
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toDecode->fetchFault = fault;
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toDecode->fetchFaultSN = cpu->globalSeqNum;
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// toDecode->fetchFault = fault;
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// toDecode->fetchFaultSN = cpu->globalSeqNum;
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DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
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@ -120,6 +120,7 @@ class FrontEnd
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SerializeComplete,
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RenameBlocked,
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QuiescePending,
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TrapPending,
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BEBlocked
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};
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@ -268,11 +268,9 @@ FrontEnd<Impl>::tick()
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}
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if (status == RenameBlocked || status == SerializeBlocked ||
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status == BEBlocked) {
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// This might cause the front end to run even though it
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// shouldn't, but this should only be a problem for one cycle.
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// Also will cause a one cycle bubble between changing state
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// and restarting.
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status == TrapPending || status == BEBlocked) {
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// Will cause a one cycle bubble between changing state and
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// restarting.
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DPRINTF(FE, "In blocked status.\n");
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fetchBlockedCycles++;
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FrontEnd<Impl>::handleFault(Fault &fault)
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{
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DPRINTF(FE, "Fault at fetch, telling commit\n");
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backEnd->fetchFault(fault);
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// backEnd->fetchFault(fault);
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// We're blocked on the back end until it handles this fault.
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status = BEBlocked;
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status = TrapPending;
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// Get a sequence number.
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InstSeqNum inst_seq = getAndIncrementInstSeq();
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// We will use a nop in order to carry the fault.
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ExtMachInst ext_inst = TheISA::NoopMachInst;
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// Create a new DynInst from the dummy nop.
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DynInstPtr instruction = new DynInst(ext_inst, PC,
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PC+sizeof(MachInst),
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inst_seq, cpu);
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instruction->setPredTarg(instruction->readNextPC());
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// instruction->setThread(tid);
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// instruction->setASID(tid);
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instruction->setState(thread);
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instruction->traceData = NULL;
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instruction->fault = fault;
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instruction->setCanIssue();
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instBuffer.push_back(instruction);
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++instBufferSize;
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}
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template <class Impl>
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(*buff_it)->isSquashed());
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buff_it++;
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}
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}
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template <class Impl>
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@ -652,7 +652,7 @@ LWBackEnd<Impl>::tick()
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squashFromTrap();
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} else if (xcSquash) {
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squashFromXC();
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} else if (fetchHasFault && robEmpty() && frontEnd->isEmpty() && !LSQ.hasStoresToWB()) {
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} /*else if (fetchHasFault && robEmpty() && frontEnd->isEmpty() && !LSQ.hasStoresToWB()) {
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DPRINTF(BE, "ROB and front end empty, handling fetch fault\n");
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Fault fetch_fault = frontEnd->getFault();
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if (fetch_fault == NoFault) {
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@ -662,7 +662,7 @@ LWBackEnd<Impl>::tick()
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handleFault(fetch_fault);
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fetchHasFault = false;
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}
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}
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}*/
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#endif
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if (dispatchStatus != Blocked) {
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@ -777,6 +777,12 @@ LWBackEnd<Impl>::dispatchInsts()
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inst->seqNum);
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exeList.push(inst);
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}
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} else if (inst->isNop()) {
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DPRINTF(BE, "Nop encountered [sn:%lli], skipping exeList.\n",
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inst->seqNum);
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inst->setIssued();
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inst->setExecuted();
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inst->setCanCommit();
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} else {
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DPRINTF(BE, "Instruction [sn:%lli] ready, addding to exeList.\n",
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inst->seqNum);
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Reference in a new issue