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Include checker and trap latency parameters.

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--HG--
extra : convert_revision : 148c59f430874e8425952db6960ca4f5e57e2a42
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Kevin Lim 2006-05-16 14:47:09 -04:00
parent 52383ca7cc
commit abe14c253b
1 changed files with 4 additions and 0 deletions
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4
python/m5/objects/AlphaFullCPU.py
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@ -9,6 +9,8 @@ class DerivAlphaFullCPU(BaseCPU):
if not build_env['FULL_SYSTEM']:
mem = Param.FunctionalMemory(NULL, "memory")
checker = Param.BaseCPU(NULL, "checker")
cachePorts = Param.Unsigned("Cache Ports")
decodeToFetchDelay = Param.Unsigned("Decode to fetch delay")
@ -50,6 +52,8 @@ class DerivAlphaFullCPU(BaseCPU):
renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay")
commitWidth = Param.Unsigned("Commit width")
squashWidth = Param.Unsigned("Squash width")
trapLatency = Param.Tick("Trap latency")
fetchTrapLatency = Param.Tick("Fetch trap latency")
localPredictorSize = Param.Unsigned("Size of local predictor")
localCtrBits = Param.Unsigned("Bits per counter")