Separate out result being ready and the instruction being complete.
--HG-- extra : convert_revision : 9f17af114bf639f8fb61896e49fa714932c081d7
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@ -101,6 +101,7 @@ BaseDynInst<Impl>::initVars()
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readyRegs = 0;
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completed = false;
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resultReady = false;
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canIssue = false;
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issued = false;
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executed = false;
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@ -117,6 +117,11 @@ class BaseDynInst : public FastAlloc, public RefCounted
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Fault write(T data, Addr addr, unsigned flags,
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uint64_t *res);
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// @todo: Probably should not have this function in the DynInst.
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template <class T>
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bool snoop(MemReqPtr &req, T &data)
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{ return cpu->snoop(req, data); }
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void prefetch(Addr addr, unsigned flags);
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void writeHint(Addr addr, int size, unsigned flags);
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Fault copySrcTranslate(Addr src);
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@ -139,6 +144,9 @@ class BaseDynInst : public FastAlloc, public RefCounted
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/** Is the instruction completed. */
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bool completed;
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/** Is the instruction's result ready. */
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bool resultReady;
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/** Can this instruction issue. */
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bool canIssue;
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@ -187,7 +195,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
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/** Pointer to the FullCPU object. */
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FullCPU *cpu;
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/** Pointer to the exec context. Will not exist in the final version. */
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/** Pointer to the exec context. */
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ImplState *thread;
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/** The kind of fault this instruction has generated. */
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@ -353,6 +361,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
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bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
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bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
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bool isQuiesce() const { return staticInst->isQuiesce(); }
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bool isUnverifiable() const { return staticInst->isUnverifiable(); }
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/** Temporarily sets this instruction as a serialize before instruction. */
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void setSerializeBefore() { serializeBefore = true; }
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@ -423,6 +432,26 @@ class BaseDynInst : public FastAlloc, public RefCounted
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/** Returns the result of a floating point (double) instruction. */
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double readDoubleResult() { return instResult.dbl; }
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void setIntReg(const StaticInst *si, int idx, uint64_t val)
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{
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instResult.integer = val;
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}
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void setFloatRegSingle(const StaticInst *si, int idx, float val)
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{
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instResult.fp = val;
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}
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void setFloatRegDouble(const StaticInst *si, int idx, double val)
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{
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instResult.dbl = val;
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}
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void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
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{
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instResult.integer = val;
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}
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//Push to .cc file.
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/** Records that one of the source registers is ready. */
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void markSrcRegReady();
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@ -444,6 +473,10 @@ class BaseDynInst : public FastAlloc, public RefCounted
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/** Returns whether or not this instruction is completed. */
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bool isCompleted() const { return completed; }
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void setResultReady() { resultReady = true; }
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bool isResultReady() const { return resultReady; }
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/** Sets this instruction as ready to issue. */
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void setCanIssue() { canIssue = true; }
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@ -540,7 +573,11 @@ class BaseDynInst : public FastAlloc, public RefCounted
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const Addr readPC() const { return PC; }
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/** Set the next PC of this instruction (its actual target). */
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void setNextPC(uint64_t val) { nextPC = val; }
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void setNextPC(uint64_t val)
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{
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nextPC = val;
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// instResult.integer = val;
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}
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void setASID(short addr_space_id) { asid = addr_space_id; }
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