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Steve Reinhardt 309e1d8193 Split SimpleCPU into two different models, AtomicSimpleCPU and 
TimingSimpleCPU, which use atomic and timing memory accesses
respectively.  Common code is factored into the BaseSimpleCPU class.
AtomicSimpleCPU includes an option (simulate_stalls) to add delays
based on the estimated latency reported by the atomic accesses.
Plain old "SimpleCPU" is gone; I have not updated all the config
files (just test/test.py).
Also fixes to get timing accesses working in new memory model and
to get split-phase memory instruction definitions working with
new memory model as well.

arch/alpha/isa/main.isa:
    Need to include packet_impl.h for functions that use Packet objects.
arch/alpha/isa/mem.isa:
    Change completeAcc() methods to take Packet object pointers.
    Also split out StoreCond template for completeAcc(), since
    that's the only one that needs write_result and we get an
    unused variable warning if we always have it in there.
build/SConstruct:
    Update list of recognized CPU model names.
configs/test/test.py:
    Change SimpleCPU to AtomicSimpleCPU.
cpu/SConscript:
    Define sources for new CPU models.
    Add split memory access methods to CPU model signatures.
cpu/cpu_models.py:
cpu/static_inst.hh:
    Define new CPU models.
cpu/simple/base.cc:
cpu/simple/base.hh:
    Factor out pieces specific to Atomic or Timing models.
mem/bus.cc:
    Bus needs to be able to route timing packets based on explicit dest
    so responses can get back to requester.  Set dest to Packet::Broadcast
    to indicate that dest should be derived from address.
    Also set packet src field based on port from which packet is sent.
mem/bus.hh:
    Set packet src field based on port from which packet is sent.
mem/packet.hh:
    Define Broadcast destination address to indicate that
    packet should be routed based on address.
mem/physical.cc:
    Set packet dest on response so packet is routed
    back to requester properly.
mem/port.cc:
    Flag blob packets as Broadcast.
python/m5/objects/PhysicalMemory.py:
    Change default latency to be 1 cycle.

--HG--
rename : cpu/simple/cpu.cc => cpu/simple/base.cc
rename : cpu/simple/cpu.hh => cpu/simple/base.hh
extra : convert_revision : e9646af6406a20c8c605087936dc4683375c2132
2006-05-16 17:36:50 -04:00
arch Split SimpleCPU into two different models, AtomicSimpleCPU and 2006-05-16 17:36:50 -04:00
base Many files: 2006-05-15 20:30:20 -04:00
build Split SimpleCPU into two different models, AtomicSimpleCPU and 2006-05-16 17:36:50 -04:00
configs Split SimpleCPU into two different models, AtomicSimpleCPU and 2006-05-16 17:36:50 -04:00
cpu Split SimpleCPU into two different models, AtomicSimpleCPU and 2006-05-16 17:36:50 -04:00
dev Many files: 2006-05-15 20:30:20 -04:00
docs Many files: 2005-06-05 05:16:00 -04:00
kern Add support for sparc/solaris syscall emulation. Not tested yet because I can't get a static sparc 64 binary 2006-05-15 17:37:03 -04:00
mem Split SimpleCPU into two different models, AtomicSimpleCPU and 2006-05-16 17:36:50 -04:00
python Split SimpleCPU into two different models, AtomicSimpleCPU and 2006-05-16 17:36:50 -04:00
sim Many files: 2006-05-15 20:30:20 -04:00
test Many files: 2006-05-15 20:30:20 -04:00
util Merge zeep.pool:/z/saidi/work/m5.head 2006-05-12 18:16:07 -04:00
Doxyfile Fix minor doxygen issues. 2005-06-05 08:08:29 -04:00
LICENSE Fix a few broken or inconsistently formatted copyrights 2005-06-05 05:08:37 -04:00
README More documentation for 1.1 release. 2005-10-06 13:59:05 -04:00
RELEASE_NOTES More documentation for 1.1 release. 2005-10-06 13:59:05 -04:00
SConscript First pass at a serializer object, may need to work on naming of object and functions: 2006-05-11 17:24:15 -04:00

README 

This is release m5_1.1 of the M5 simulator.

This file contains brief "getting started" instructions.  For more
information, see http://m5.eecs.umich.edu.  If you have questions,
please send mail to m5sim-users@lists.sourceforge.net.

WHAT'S INCLUDED (AND NOT)
-------------------------

The basic source release includes these subdirectories:
 - m5: the simulator itself
 - m5-test: regression tests
 - ext: less-common external packages needed to build m5
 - alpha-system: source for Alpha console and PALcode

To run full-system simulations, you will need compiled console,
PALcode, and kernel binaries and one or more disk images.  These files
are collected in a separate archive, m5_system_1.1.tar.bz2.  This file
is included on the CD release, or you can download it separately from
Sourceforge.

M5 supports Linux 2.4/2.6, FreeBSD, and the proprietary Compaq/HP
Tru64 version of Unix. We are able to distribute Linux and FreeBSD
bootdisks, but we are unable to distribute bootable disk images of
Tru64 Unix. If you have a Tru64 license and are interested in
obtaining disk images, contact us at m5-dev@eecs.umich.edu.

The CD release includes a few extra goodies, such as a tar file
containing doxygen-generated HTML documentation (html-docs.tar.gz), a
set of Linux source patches (linux_m5-2.6.8.1.diff), and the scons
program needed to build M5.  If you do not have the CD, the same HTML
documentation is available online at http://m5.eecs.umich.edu/docs,
the Linux source patches are available at
http://m5.eecs.umich.edu/dist/linux_m5-2.6.8.1.diff, and the scons
program is available from http://www.scons.org.

WHAT'S NEEDED
-------------
- GCC version 3.3 or newer
- Python 2.3 or newer
- SCons 0.96.1 or newer (see http://www.scons.org)

WHAT'S RECOMMENDED
------------------
- MySQL (for statistics complex statistics storage/retrieval)
- Python-MysqlDB (for statistics analysis) 

GETTING STARTED
---------------

There are two different build targets and three optimizations levels:

Target:
-------
ALPHA_SE - Syscall emulation simulation
ALPHA_FS - Full system simulation

Optimization:
-------------
m5.debug - debug version of the code with tracing and without optimization
m5.opt   - optimized version of code with tracing
m5.fast  - optimized version of the code without tracing and asserts

Different targets are built in different subdirectories of m5/build.
Binaries with the same target but different optimization levels share
the same directory.  Note that you can build m5 in any directory you
choose;p just configure the target directory using the 'mkbuilddir'
script in m5/build.

The following steps will build and test the simulator.  The variable
"$top" refers to the top directory where you've unpacked the files,
i.e., the one containing the m5, m5-test, and ext directories.  If you
have a multiprocessor system, you should give scons a "-j N" argument (like
make) to run N jobs in parallel.

To build and test the syscall-emulation simulator:

	cd $top/m5/build
	scons ALPHA_SE/test/opt/quick

This process takes under 10 minutes on a dual 3GHz Xeon system (using
the '-j 4' option).

To build and test the full-system simulator:

1. Unpack the full-system binaries from m5_system_1.1.tar.bz2.  (See
   above for directions on obtaining this file if you don't have it.)
   This package includes disk images and kernel, palcode, and console
   binaries for Linux and FreeBSD.
2. Edit the SYSTEMDIR search path in $top/m5-test/SysPaths.py to
   include the path to your local copy of the binaries.
3. In $top/m5/build, run "scons ALPHA_FS/test/opt/quick".

This process also takes under 10 minutes on a dual 3GHz Xeon system
(again using the '-j 4' option).