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FP programs are back to running... Condition Codes can be read and set...

Browse source 
Special Regs (Hi,Lo,FCSR) are now added to the operands for use in decoder.isa.

Now it's back to just debugging execution of code for the release (those unaligned
memory access instruction pairs are still quite the pain i might add)

arch/mips/isa_traits.hh:
    declare functions for .cc file
arch/mips/isa_traits.cc:
    delete unnecessary overloaded functions

    implement condition code functions

    implement round function
arch/mips/isa/base.isa:
    remove R31 constant... define in the operands.isa file instead
arch/mips/isa/decoder.isa:
    wholesale changes once again to FP.

    Now the FP Condition Codes are implemented and the FP programs can
    run and complete to finish.

    Use isnan() instead of my unorderedFP() function

    Also, we now access special regs such as HI,LO,FCSR,etc. just like we do any other reg. operand
arch/mips/isa/operands.isa:
    add more operands for special control regs in int and FP regfiles
arch/mips/isa/formats/branch.isa:
    use R31 instead of r31
arch/mips/isa/formats/fp.isa:
    use MakeCCVector to set Condition Codes in FCSR
arch/mips/regfile/float_regfile.hh:
    treat control regs like any other reg. Just Index them after the regular architectural registers
arch/mips/regfile/int_regfile.hh:
    treat hi,lo as regular int. regs w/special indexing
arch/mips/regfile/regfile.hh:
    no longer need for special register accesses with their own function.

--HG--
rename : arch/mips/regfile.hh => arch/mips/regfile/regfile.hh
extra : convert_revision : 5d2f8fdb59606de2b2e9db3e0a085240561e479e
This commit is contained in:
Korey Sewell 2006-05-12 02:57:32 -04:00
parent e5064e470c
commit a91ee5abc2
10 changed files with 221 additions and 341 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
arch/mips/isa/base.isa
View file

@ -8,8 +8,6 @@
//Outputs to decoder.hh
output header {{
#define R31 31
using namespace MipsISA;

286
arch/mips/isa/decoder.isa
View file

@ -20,8 +20,8 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: decode FUNCTION_LO {
0x1: decode MOVCI {
format BasicOp {
0: movf({{ if (getFPConditionCode(CC) == 0) Rd = Rs}});
1: movt({{ if (getFPConditionCode(CC) == 1) Rd = Rs}});
0: movf({{ if (getFPConditionCode(FCSR, CC) == 0) Rd = Rs}});
1: movt({{ if (getFPConditionCode(FCSR, CC) == 1) Rd = Rs}});
}
}
@ -127,10 +127,10 @@ decode OPCODE_HI default Unknown::unknown() {
0x2: decode FUNCTION_LO {
format BasicOp {
0x0: mfhi({{ Rd = xc->readMiscReg(Hi); }});
0x1: mthi({{ xc->setMiscReg(Hi,Rs); }});
0x2: mflo({{ Rd = xc->readMiscReg(Lo); }});
0x3: mtlo({{ xc->setMiscReg(Lo,Rs); }});
0x0: mfhi({{ Rd = HI; }});
0x1: mthi({{ HI = Rs; }});
0x2: mflo({{ Rd = LO; }});
0x3: mtlo({{ LO = Rs; }});
}
}
@ -138,24 +138,24 @@ decode OPCODE_HI default Unknown::unknown() {
format IntOp {
0x0: mult({{
int64_t temp1 = Rs.sd * Rt.sd;
xc->setMiscReg(Hi,temp1<63:32>);
xc->setMiscReg(Lo,temp1<31:0>);
HI = temp1<63:32>;
LO = temp1<31:0>;
}});
0x1: multu({{
uint64_t temp1 = Rs.ud * Rt.ud;
xc->setMiscReg(Hi,temp1<63:32>);
xc->setMiscReg(Lo,temp1<31:0>);
HI = temp1<63:32>;
LO = temp1<31:0>;
}});
0x2: div({{
xc->setMiscReg(Hi,Rs.sd % Rt.sd);
xc->setMiscReg(Lo,Rs.sd / Rt.sd);
HI = Rs.sd % Rt.sd;
LO = Rs.sd / Rt.sd;
}});
0x3: divu({{
xc->setMiscReg(Hi,Rs.ud % Rt.ud);
xc->setMiscReg(Lo,Rs.ud / Rt.ud);
HI = Rs.ud % Rt.ud;
LO = Rs.ud / Rt.ud;
}});
}
}
@ -163,9 +163,9 @@ decode OPCODE_HI default Unknown::unknown() {
0x4: decode HINT {
0x0: decode FUNCTION_LO {
format IntOp {
0x0: add({{ Rd.sw = Rs.sw + Rt.sw;/*Trap on Overflow*/}});
0x0: add({{ Rd.sw = Rs.sw + Rt.sw; /*Trap on Overflow*/}});
0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}});
0x2: sub({{ Rd.sw = Rs.sw - Rt.sw; /*Trap on Overflow*/}});
0x2: sub({{ Rd.sw = Rs.sw - Rt.sw; /*Trap on Overflow*/}});
0x3: subu({{ Rd.sw = Rs.sw - Rt.sw;}});
0x4: and({{ Rd = Rs & Rt;}});
0x5: or({{ Rd = Rs | Rt;}});
@ -299,6 +299,7 @@ decode OPCODE_HI default Unknown::unknown() {
//sel field. In those instances, the sel field must be zero.
//MT Code Needed Here
}});
0xC: mttr({{
@ -397,78 +398,71 @@ decode OPCODE_HI default Unknown::unknown() {
0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}});
0x4: mtc1 ({{ Fs.uw = Rt.uw; }});
0x7: mthc1({{
uint64_t fs_hi = Rt.ud << 32;
uint64_t fs_hi = Rt.uw;
uint64_t fs_lo = Fs.ud & 0x0000FFFF;
Fs.ud = fs_hi & fs_lo;
Fs.ud = fs_hi << 32 | fs_lo;
}});
}
format System {
0x2: cfc1({{
uint32_t fcsr_reg = xc->readMiscReg(FCSR);
switch (FS)
{
case 0:
Rt = xc->readMiscReg(FIR);
Rt = FIR;
break;
case 25:
Rt = 0 | (fcsr_reg & 0xFE000000) >> 24 | (fcsr_reg & 0x00800000) >> 23;
Rt = 0 | (FCSR & 0xFE000000) >> 24 | (FCSR & 0x00800000) >> 23;
break;
case 26:
Rt = 0 | (fcsr_reg & 0x0003F07C);
Rt = 0 | (FCSR & 0x0003F07C);
break;
case 28:
Rt = 0 | (fcsr_reg);
Rt = 0 | (FCSR & 0x00000F80) | (FCSR & 0x01000000) >> 21 | (FCSR & 0x00000003);
break;
case 31:
Rt = fcsr_reg;
Rt = FCSR;
break;
default:
panic("FP Control Value (%d) Not Available. Ignoring Access to"
"Floating Control Status Register",fcsr_reg);
"Floating Control Status Register",FS);
}
}});
0x6: ctc1({{
uint32_t fcsr_reg = xc->readMiscReg(FCSR);
uint32_t temp;
switch (FS)
{
case 25:
temp = 0 | (Rt.uw<7:1> << 25) // move 31...25
| (fcsr_reg & 0x01000000) // bit 24
| (fcsr_reg & 0x004FFFFF);// bit 22...0
FCSR = 0 | (Rt.uw<7:1> << 25) // move 31...25
| (FCSR & 0x01000000) // bit 24
| (FCSR & 0x004FFFFF);// bit 22...0
break;
case 26:
temp = 0 | (fcsr_reg & 0xFFFC0000) // move 31...18
FCSR = 0 | (FCSR & 0xFFFC0000) // move 31...18
| Rt.uw<17:12> << 12 // bit 17...12
| (fcsr_reg & 0x00000F80) << 7// bit 11...7
| (FCSR & 0x00000F80) << 7// bit 11...7
| Rt.uw<6:2> << 2 // bit 6...2
| (fcsr_reg & 0x00000002); // bit 1...0
| (FCSR & 0x00000002); // bit 1...0
break;
case 28:
temp = 0 | (fcsr_reg & 0xFE000000) // move 31...25
FCSR = 0 | (FCSR & 0xFE000000) // move 31...25
| Rt.uw<2:2> << 24 // bit 24
| (fcsr_reg & 0x00FFF000) << 23// bit 23...12
| (FCSR & 0x00FFF000) << 23// bit 23...12
| Rt.uw<11:7> << 7 // bit 24
| (fcsr_reg & 0x000007E)
| (FCSR & 0x000007E)
| Rt.uw<1:0>;// bit 22...0
break;
case 31:
temp = Rt.uw;
FCSR = Rt.uw;
break;
default:
panic("FP Control Value (%d) Not Available. Ignoring Access to"
"Floating Control Status Register",fcsr_reg);
"Floating Control Status Register", FS);
}
xc->setMiscReg(FCSR,temp);
}});
}
}
@ -476,15 +470,15 @@ decode OPCODE_HI default Unknown::unknown() {
0x1: decode ND {
0x0: decode TF {
format Branch {
0x0: bc1f({{ cond = (getFPConditionCode(CC) == 0); }});
0x1: bc1t({{ cond = (getFPConditionCode(CC) == 1); }});
0x0: bc1f({{ cond = (getFPConditionCode(FCSR,CC) == 0); }});
0x1: bc1t({{ cond = (getFPConditionCode(FCSR,CC) == 1); }});
}
}
0x1: decode TF {
format BranchLikely {
0x0: bc1fl({{ cond = (getFPConditionCode(CC) == 0); }});
0x1: bc1tl({{ cond = (getFPConditionCode(CC) == 1); }});
0x0: bc1fl({{ cond = (getFPConditionCode(FCSR,CC) == 0); }});
0x1: bc1tl({{ cond = (getFPConditionCode(FCSR,CC) == 1); }});
}
}
}
@ -512,7 +506,7 @@ decode OPCODE_HI default Unknown::unknown() {
0x1: decode FUNCTION_LO {
format Float64Op {
0x0: round_l_s({{
Fd.ud = fpConvert(roundFP(Fs.sf), SINGLE_TO_LONG);
Fd.ud = fpConvert(roundFP(Fs.sf,0), SINGLE_TO_LONG);
}});
0x1: trunc_l_s({{
@ -530,7 +524,7 @@ decode OPCODE_HI default Unknown::unknown() {
format FloatOp {
0x4: round_w_s({{
Fd.uw = fpConvert(roundFP(Fs.sf), SINGLE_TO_WORD);
Fd.uw = fpConvert(roundFP(Fs.sf,0), SINGLE_TO_WORD);
}});
0x5: trunc_w_s({{
@ -550,8 +544,8 @@ decode OPCODE_HI default Unknown::unknown() {
0x2: decode FUNCTION_LO {
0x1: decode MOVCF {
format FloatOp {
0x0: movf_s({{if (getFPConditionCode(CC) == 0) Fd = Fs;}});
0x1: movt_s({{if (getFPConditionCode(CC) == 1) Fd = Fs;}});
0x0: movf_s({{if (getFPConditionCode(FCSR,CC) == 0) Fd = Fs;}});
0x1: movt_s({{if (getFPConditionCode(FCSR,CC) == 1) Fd = Fs;}});
}
}
@ -591,49 +585,49 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: c_f_s({{ cond = 0; }});
0x1: c_un_s({{
if (unorderedFP(Fs.sf) || unorderedFP(Ft.sf))
if (isnan(Fs.sf) || isnan(Ft.sf))
cond = 1;
else
cond = 0;
}});
0x2: c_eq_s({{
if (unorderedFP(Fs.sf) || unorderedFP(Ft.sf))
if (isnan(Fs.sf) || isnan(Ft.sf))
cond = 0;
else
cond = (Fs.sf == Ft.sf);
}});
0x3: c_ueq_s({{
if (unorderedFP(Fs.sf) || unorderedFP(Ft.sf))
if (isnan(Fs.sf) || isnan(Ft.sf))
cond = 1;
else
cond = (Fs.sf == Ft.sf);
}});
0x4: c_olt_s({{
if (unorderedFP(Fs.sf) || unorderedFP(Ft.sf))
if (isnan(Fs.sf) || isnan(Ft.sf))
cond = 0;
else
cond = (Fs.sf < Ft.sf);
}});
0x5: c_ult_s({{
if (unorderedFP(Fs.sf) || unorderedFP(Ft.sf))
if (isnan(Fs.sf) || isnan(Ft.sf))
cond = 1;
else
cond = (Fs.sf < Ft.sf);
}});
0x6: c_ole_s({{
if (unorderedFP(Fs.sf) || unorderedFP(Ft.sf))
if (isnan(Fs.sf) || isnan(Ft.sf))
cond = 0;
else
cond = (Fs.sf <= Ft.sf);
}});
0x7: c_ule_s({{
if (unorderedFP(Fs.sf) || unorderedFP(Ft.sf))
if (isnan(Fs.sf) || isnan(Ft.sf))
cond = 1;
else
cond = (Fs.sf <= Ft.sf);
@ -646,49 +640,49 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: c_sf_s({{ cond = 0; }});
0x1: c_ngle_s({{
if (unorderedFP(Fs.sf) || unorderedFP(Ft.sf))
if (isnan(Fs.sf) || isnan(Ft.sf))
cond = 1;
else
cond = 0;
}});
0x2: c_seq_s({{
if (unorderedFP(Fs.sf) || unorderedFP(Ft.sf))
if (isnan(Fs.sf) || isnan(Ft.sf))
cond = 0;
else
cond = (Fs.sf == Ft.sf);
}});
0x3: c_ngl_s({{
if (unorderedFP(Fs.sf) || unorderedFP(Ft.sf))
if (isnan(Fs.sf) || isnan(Ft.sf))
cond = 1;
else
cond = (Fs.sf == Ft.sf);
}});
0x4: c_lt_s({{
if (unorderedFP(Fs.sf) || unorderedFP(Ft.sf))
if (isnan(Fs.sf) || isnan(Ft.sf))
cond = 0;
else
cond = (Fs.sf < Ft.sf);
}});
0x5: c_nge_s({{
if (unorderedFP(Fs.sf) || unorderedFP(Ft.sf))
if (isnan(Fs.sf) || isnan(Ft.sf))
cond = 1;
else
cond = (Fs.sf < Ft.sf);
}});
0x6: c_le_s({{
if (unorderedFP(Fs.sf) || unorderedFP(Ft.sf))
if (isnan(Fs.sf) || isnan(Ft.sf))
cond = 0;
else
cond = (Fs.sf <= Ft.sf);
}});
0x7: c_ngt_s({{
if (unorderedFP(Fs.sf) || unorderedFP(Ft.sf))
if (isnan(Fs.sf) || isnan(Ft.sf))
cond = 1;
else
cond = (Fs.sf <= Ft.sf);
@ -715,37 +709,37 @@ decode OPCODE_HI default Unknown::unknown() {
0x1: decode FUNCTION_LO {
format FloatOp {
0x0: round_l_d({{
Fd.ud = fpConvert(roundFP(Fs.ud), DOUBLE_TO_LONG);
Fd.ud = fpConvert(roundFP(Fs.df,0), DOUBLE_TO_LONG);
}});
0x1: trunc_l_d({{
Fd.ud = fpConvert(truncFP(Fs.ud), DOUBLE_TO_LONG);
Fd.ud = fpConvert(truncFP(Fs.df), DOUBLE_TO_LONG);
}});
0x2: ceil_l_d({{
Fd.ud = fpConvert(ceil(Fs.ud), DOUBLE_TO_LONG);
Fd.ud = fpConvert(ceil(Fs.df), DOUBLE_TO_LONG);
}});
0x3: floor_l_d({{
Fd.ud = fpConvert(floor(Fs.ud), DOUBLE_TO_LONG);
Fd.ud = fpConvert(floor(Fs.df), DOUBLE_TO_LONG);
}});
}
format FloatOp {
0x4: round_w_d({{
Fd.uw = fpConvert(roundFP(Fs.ud), DOUBLE_TO_WORD);
Fd.uw = fpConvert(roundFP(Fs.df,0), DOUBLE_TO_WORD);
}});
0x5: trunc_w_d({{
Fd.uw = fpConvert(truncFP(Fs.ud), DOUBLE_TO_WORD);
Fd.uw = fpConvert(truncFP(Fs.df), DOUBLE_TO_WORD);
}});
0x6: ceil_w_d({{
Fd.uw = fpConvert(ceil(Fs.ud), DOUBLE_TO_WORD);
Fd.uw = fpConvert(ceil(Fs.df), DOUBLE_TO_WORD);
}});
0x7: floor_w_d({{
Fd.uw = fpConvert(floor(Fs.ud), DOUBLE_TO_WORD);
Fd.uw = fpConvert(floor(Fs.df), DOUBLE_TO_WORD);
}});
}
}
@ -753,8 +747,8 @@ decode OPCODE_HI default Unknown::unknown() {
0x2: decode FUNCTION_LO {
0x1: decode MOVCF {
format FloatOp {
0x0: movf_d({{if (getFPConditionCode(CC) == 0) Fd.df = Fs.df; }});
0x1: movt_d({{if (getFPConditionCode(CC) == 1) Fd.df = Fs.df; }});
0x0: movf_d({{if (getFPConditionCode(FCSR,CC) == 0) Fd.df = Fs.df; }});
0x1: movt_d({{if (getFPConditionCode(FCSR,CC) == 1) Fd.df = Fs.df; }});
}
}
@ -772,15 +766,15 @@ decode OPCODE_HI default Unknown::unknown() {
0x4: decode FUNCTION_LO {
format FloatOp {
0x0: cvt_s_d({{
Fd.uw = fpConvert(Fs.ud, DOUBLE_TO_SINGLE);
Fd.uw = fpConvert(Fs.df, DOUBLE_TO_SINGLE);
}});
0x4: cvt_w_d({{
Fd.uw = fpConvert(Fs.ud, DOUBLE_TO_WORD);
Fd.uw = fpConvert(Fs.df, DOUBLE_TO_WORD);
}});
0x5: cvt_l_d({{
Fd.ud = fpConvert(Fs.ud, DOUBLE_TO_LONG);
Fd.ud = fpConvert(Fs.df, DOUBLE_TO_LONG);
}});
}
}
@ -790,49 +784,49 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: c_f_d({{ cond = 0; }});
0x1: c_un_d({{
if (unorderedFP(Fs.df) || unorderedFP(Ft.df))
if (isnan(Fs.df) || isnan(Ft.df))
cond = 1;
else
cond = 0;
}});
0x2: c_eq_d({{
if (unorderedFP(Fs.df) || unorderedFP(Ft.df))
if (isnan(Fs.df) || isnan(Ft.df))
cond = 0;
else
cond = (Fs.df == Ft.df);
}});
0x3: c_ueq_d({{
if (unorderedFP(Fs.df) || unorderedFP(Ft.df))
if (isnan(Fs.df) || isnan(Ft.df))
cond = 1;
else
cond = (Fs.df == Ft.df);
}});
0x4: c_olt_d({{
if (unorderedFP(Fs.df) || unorderedFP(Ft.df))
if (isnan(Fs.df) || isnan(Ft.df))
cond = 0;
else
cond = (Fs.df < Ft.df);
}});
0x5: c_ult_d({{
if (unorderedFP(Fs.df) || unorderedFP(Ft.df))
if (isnan(Fs.df) || isnan(Ft.df))
cond = 1;
else
cond = (Fs.df < Ft.df);
}});
0x6: c_ole_d({{
if (unorderedFP(Fs.df) || unorderedFP(Ft.df))
if (isnan(Fs.df) || isnan(Ft.df))
cond = 0;
else
cond = (Fs.df <= Ft.df);
}});
0x7: c_ule_d({{
if (unorderedFP(Fs.df) || unorderedFP(Ft.df))
if (isnan(Fs.df) || isnan(Ft.df))
cond = 1;
else
cond = (Fs.df <= Ft.df);
@ -845,49 +839,49 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: c_sf_d({{ cond = 0; }});
0x1: c_ngle_d({{
if (unorderedFP(Fs.df) || unorderedFP(Ft.df))
if (isnan(Fs.df) || isnan(Ft.df))
cond = 1;
else
cond = 0;
}});
0x2: c_seq_d({{
if (unorderedFP(Fs.df) || unorderedFP(Ft.df))
if (isnan(Fs.df) || isnan(Ft.df))
cond = 0;
else
cond = (Fs.df == Ft.df);
}});
0x3: c_ngl_d({{
if (unorderedFP(Fs.df) || unorderedFP(Ft.df))
if (isnan(Fs.df) || isnan(Ft.df))
cond = 1;
else
cond = (Fs.df == Ft.df);
}});
0x4: c_lt_d({{
if (unorderedFP(Fs.df) || unorderedFP(Ft.df))
if (isnan(Fs.df) || isnan(Ft.df))
cond = 0;
else
cond = (Fs.df < Ft.df);
}});
0x5: c_nge_d({{
if (unorderedFP(Fs.df) || unorderedFP(Ft.df))
if (isnan(Fs.df) || isnan(Ft.df))
cond = 1;
else
cond = (Fs.df < Ft.df);
}});
0x6: c_le_d({{
if (unorderedFP(Fs.df) || unorderedFP(Ft.df))
if (isnan(Fs.df) || isnan(Ft.df))
cond = 0;
else
cond = (Fs.df <= Ft.df);
}});
0x7: c_ngt_d({{
if (unorderedFP(Fs.df) || unorderedFP(Ft.df))
if (isnan(Fs.df) || isnan(Ft.df))
cond = 1;
else
cond = (Fs.df <= Ft.df);
@ -976,16 +970,16 @@ decode OPCODE_HI default Unknown::unknown() {
0x1: decode MOVCF {
format Float64Op {
0x0: movf_ps({{
if (getFPConditionCode(CC) == 0)
if (getFPConditionCode(FCSR, CC) == 0)
Fd1 = Fs1;
if (getFPConditionCode(CC+1) == 0)
if (getFPConditionCode(FCSR, CC+1) == 0)
Fd2 = Fs2;
}});
0x1: movt_ps({{
if (getFPConditionCode(CC) == 1)
if (getFPConditionCode(FCSR, CC) == 1)
Fd1 = Fs1;
if (getFPConditionCode(CC+1) == 1)
if (getFPConditionCode(FCSR, CC+1) == 1)
Fd2 = Fs2;
}});
}
@ -993,16 +987,16 @@ decode OPCODE_HI default Unknown::unknown() {
format Float64Op {
0x2: movz_ps({{
if (getFPConditionCode(CC) == 0)
if (getFPConditionCode(FCSR, CC) == 0)
Fd1 = Fs1;
if (getFPConditionCode(CC) == 0)
if (getFPConditionCode(FCSR, CC) == 0)
Fd2 = Fs2;
}});
0x3: movn_ps({{
if (getFPConditionCode(CC) == 1)
if (getFPConditionCode(FCSR, CC) == 1)
Fd1 = Fs1;
if (getFPConditionCode(CC) == 1)
if (getFPConditionCode(FCSR, CC) == 1)
Fd2 = Fs2;
}});
}
@ -1033,12 +1027,12 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: c_f_ps({{ cond1 = 0; cond2 = 0; }});
0x1: c_un_ps({{
if (unorderedFP(Fs1.sf) || unorderedFP(Ft1.sf))
if (isnan(Fs1.sf) || isnan(Ft1.sf))
cond1 = 1;
else
cond1 = 0;
if (unorderedFP(Fs2.sf) || unorderedFP(Ft2.sf))
if (isnan(Fs2.sf) || isnan(Ft2.sf))
cond2 = 1;
else
cond2 = 0;
@ -1046,72 +1040,72 @@ decode OPCODE_HI default Unknown::unknown() {
}});
0x2: c_eq_ps({{
if (unorderedFP(Fs1.sf) || unorderedFP(Ft1.sf))
if (isnan(Fs1.sf) || isnan(Ft1.sf))
cond1 = 0;
else
cond1 = (Fs1.sf == Ft1.sf);
if (unorderedFP(Fs2.sf) || unorderedFP(Ft2.sf))
if (isnan(Fs2.sf) || isnan(Ft2.sf))
cond2 = 0;
else
cond2 = (Fs2.sf == Ft2.sf);
}});
0x3: c_ueq_ps({{
if (unorderedFP(Fs1.sf) || unorderedFP(Ft1.sf))
if (isnan(Fs1.sf) || isnan(Ft1.sf))
cond1 = 1;
else
cond1 = (Fs1.sf == Ft1.sf);
if (unorderedFP(Fs2.sf) || unorderedFP(Ft2.sf))
if (isnan(Fs2.sf) || isnan(Ft2.sf))
cond2 = 1;
else
cond2 = (Fs2.sf == Ft2.sf);
}});
0x4: c_olt_ps({{
if (unorderedFP(Fs1.sf) || unorderedFP(Ft1.sf))
if (isnan(Fs1.sf) || isnan(Ft1.sf))
cond1 = 0;
else
cond1 = (Fs1.sf < Ft1.sf);
if (unorderedFP(Fs2.sf) || unorderedFP(Ft2.sf))
if (isnan(Fs2.sf) || isnan(Ft2.sf))
cond2 = 0;
else
cond2 = (Fs2.sf < Ft2.sf);
}});
0x5: c_ult_ps({{
if (unorderedFP(Fs1.sf) || unorderedFP(Ft1.sf))
if (isnan(Fs1.sf) || isnan(Ft1.sf))
cond1 = 1;
else
cond1 = (Fs.sf < Ft.sf);
if (unorderedFP(Fs2.sf) || unorderedFP(Ft2.sf))
if (isnan(Fs2.sf) || isnan(Ft2.sf))
cond2 = 1;
else
cond2 = (Fs2.sf < Ft2.sf);
}});
0x6: c_ole_ps({{
if (unorderedFP(Fs.sf) || unorderedFP(Ft.sf))
if (isnan(Fs.sf) || isnan(Ft.sf))
cond1 = 0;
else
cond1 = (Fs.sf <= Ft.sf);
if (unorderedFP(Fs2.sf) || unorderedFP(Ft2.sf))
if (isnan(Fs2.sf) || isnan(Ft2.sf))
cond2 = 0;
else
cond2 = (Fs2.sf <= Ft2.sf);
}});
0x7: c_ule_ps({{
if (unorderedFP(Fs1.sf) || unorderedFP(Ft1.sf))
if (isnan(Fs1.sf) || isnan(Ft1.sf))
cond1 = 1;
else
cond1 = (Fs1.sf <= Ft1.sf);
if (unorderedFP(Fs2.sf) || unorderedFP(Ft2.sf))
if (isnan(Fs2.sf) || isnan(Ft2.sf))
cond2 = 1;
else
cond2 = (Fs2.sf <= Ft2.sf);
@ -1124,84 +1118,84 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: c_sf_ps({{ cond1 = 0; cond2 = 0; }});
0x1: c_ngle_ps({{
if (unorderedFP(Fs1.sf) || unorderedFP(Ft1.sf))
if (isnan(Fs1.sf) || isnan(Ft1.sf))
cond1 = 1;
else
cond1 = 0;
if (unorderedFP(Fs2.sf) || unorderedFP(Ft2.sf))
if (isnan(Fs2.sf) || isnan(Ft2.sf))
cond2 = 1;
else
cond2 = 0;
}});
0x2: c_seq_ps({{
if (unorderedFP(Fs1.sf) || unorderedFP(Ft1.sf))
if (isnan(Fs1.sf) || isnan(Ft1.sf))
cond1 = 0;
else
cond1 = (Fs1.sf == Ft1.sf);
if (unorderedFP(Fs2.sf) || unorderedFP(Ft2.sf))
if (isnan(Fs2.sf) || isnan(Ft2.sf))
cond2 = 0;
else
cond2 = (Fs2.sf == Ft2.sf);
}});
0x3: c_ngl_ps({{
if (unorderedFP(Fs1.sf) || unorderedFP(Ft1.sf))
if (isnan(Fs1.sf) || isnan(Ft1.sf))
cond1 = 1;
else
cond1 = (Fs1.sf == Ft1.sf);
if (unorderedFP(Fs2.sf) || unorderedFP(Ft2.sf))
if (isnan(Fs2.sf) || isnan(Ft2.sf))
cond2 = 1;
else
cond2 = (Fs2.sf == Ft2.sf);
}});
0x4: c_lt_ps({{
if (unorderedFP(Fs1.sf) || unorderedFP(Ft1.sf))
if (isnan(Fs1.sf) || isnan(Ft1.sf))
cond1 = 0;
else
cond1 = (Fs1.sf < Ft1.sf);
if (unorderedFP(Fs2.sf) || unorderedFP(Ft2.sf))
if (isnan(Fs2.sf) || isnan(Ft2.sf))
cond2 = 0;
else
cond2 = (Fs2.sf < Ft2.sf);
}});
0x5: c_nge_ps({{
if (unorderedFP(Fs1.sf) || unorderedFP(Ft1.sf))
if (isnan(Fs1.sf) || isnan(Ft1.sf))
cond1 = 1;
else
cond1 = (Fs1.sf < Ft1.sf);
if (unorderedFP(Fs2.sf) || unorderedFP(Ft2.sf))
if (isnan(Fs2.sf) || isnan(Ft2.sf))
cond2 = 1;
else
cond2 = (Fs2.sf < Ft2.sf);
}});
0x6: c_le_ps({{
if (unorderedFP(Fs1.sf) || unorderedFP(Ft1.sf))
if (isnan(Fs1.sf) || isnan(Ft1.sf))
cond1 = 0;
else
cond1 = (Fs1.sf <= Ft1.sf);
if (unorderedFP(Fs2.sf) || unorderedFP(Ft2.sf))
if (isnan(Fs2.sf) || isnan(Ft2.sf))
cond2 = 0;
else
cond2 = (Fs2.sf <= Ft2.sf);
}});
0x7: c_ngt_ps({{
if (unorderedFP(Fs1.sf) || unorderedFP(Ft1.sf))
if (isnan(Fs1.sf) || isnan(Ft1.sf))
cond1 = 1;
else
cond1 = (Fs1.sf <= Ft1.sf);
if (unorderedFP(Fs2.sf) || unorderedFP(Ft2.sf))
if (isnan(Fs2.sf) || isnan(Ft2.sf))
cond2 = 1;
else
cond2 = (Fs2.sf <= Ft2.sf);
@ -1326,34 +1320,34 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: decode FUNCTION_LO {
format IntOp {
0x0: madd({{
int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32;
int64_t temp1 = (int64_t) HI << 32 | LO;
temp1 = temp1 + (Rs.sw * Rt.sw);
xc->setMiscReg(Hi,temp1<63:32>);
xc->setMiscReg(Lo,temp1<31:0>);
}});
HI = temp1<63:32>;
LO = temp1<31:0>;
}});
0x1: maddu({{
int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32;
int64_t temp1 = (int64_t) HI << 32 | LO;
temp1 = temp1 + (Rs.uw * Rt.uw);
xc->setMiscReg(Hi,temp1<63:32>);
xc->setMiscReg(Lo,temp1<31:0>);
}});
HI = temp1<63:32>;
LO = temp1<31:0>;
}});
0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }});
0x4: msub({{
int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32;
int64_t temp1 = (int64_t) HI << 32 | LO;
temp1 = temp1 - (Rs.sw * Rt.sw);
xc->setMiscReg(Hi,temp1<63:32>);
xc->setMiscReg(Lo,temp1<31:0>);
}});
HI = temp1<63:32>;
LO = temp1<31:0>;
}});
0x5: msubu({{
int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32;
int64_t temp1 = (int64_t) HI << 32 | LO;
temp1 = temp1 - (Rs.uw * Rt.uw);
xc->setMiscReg(Hi,temp1<63:32>);
xc->setMiscReg(Lo,temp1<31:0>);
}});
HI = temp1<63:32>;
LO = temp1<31:0>;
}});
}
}
@ -1416,8 +1410,8 @@ decode OPCODE_HI default Unknown::unknown() {
0x02: FailUnimpl::wsbh();
format BasicOp {
0x10: seb({{ Rd.sw = Rt<7:0>}});
0x18: seh({{ Rd.sw = Rt<15:0>}});
0x10: seb({{ Rd.sw = Rt.sw<7:0>}});
0x18: seh({{ Rd.sw = Rt.sw<15:0>}});
}
}
@ -1519,8 +1513,6 @@ decode OPCODE_HI default Unknown::unknown() {
}},
{{ EA = (Rs + disp) & ~3; }});
}
0x7: FailUnimpl::reserved();
}
0x5: decode OPCODE_LO default FailUnimpl::reserved() {

6
arch/mips/isa/formats/branch.isa
View file

@ -261,7 +261,7 @@ def format Branch(code,*flags) {{
#Add Link Code if Link instruction
strlen = len(name)
if name[strlen-2:] == 'al':
code += 'r31 = NNPC;\n'
code += 'R31 = NNPC;\n'
#Condition code
code = 'bool cond;\n' + code
@ -285,7 +285,7 @@ def format BranchLikely(code,*flags) {{
#Add Link Code if Link instruction
strlen = len(name)
if name[strlen-3:] == 'all':
code += 'r31 = NNPC;\n'
code += 'R31 = NNPC;\n'
#Condition code
code = 'bool cond;\n' + code
@ -307,7 +307,7 @@ def format Jump(code,*flags) {{
#Add Link Code if Link instruction
strlen = len(name)
if strlen > 1 and name[1:] == 'al':
code = 'r31 = NNPC;\n' + code
code = 'R31 = NNPC;\n' + code
iop = InstObjParams(name, Name, 'Jump', CodeBlock(code),\

8
arch/mips/isa/formats/fp.isa
View file

@ -41,6 +41,7 @@ def format FloatOp(code, *flags) {{
def format FloatCompareOp(code, *flags) {{
code = 'bool cond;\n' + code
code += 'FCSR = makeCCVector(FCSR, CC,cond);\n'
iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
@ -50,6 +51,7 @@ def format FloatCompareOp(code, *flags) {{
def format FloatCompareWithXcptOp(code, *flags) {{
code = 'bool cond;\n' + code
code += 'FCSR = makeCCVector(FCSR, CC,cond);\n'
iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
@ -75,6 +77,8 @@ def format Float64Op(code, *flags) {{
}};
def format Float64ConvertOp(code, *flags) {{
code = 'bool cond;\n' + code
code += 'FCSR = makeCCVector(FCSR, CC,cond);\n'
iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
@ -84,6 +88,8 @@ def format Float64ConvertOp(code, *flags) {{
def format FloatPSCompareOp(code, *flags) {{
code = 'bool cond1;\nbool cond2;\n' + code
code += 'FCSR = makeCCVector(FCSR, CC+1, cond1);\n'
code += 'FCSR = makeCCVector(FCSR, CC, cond2);\n'
iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
@ -93,6 +99,8 @@ def format FloatPSCompareOp(code, *flags) {{
def format FloatPSCompareWithXcptOp(code, *flags) {{
code = 'bool cond1;\nbool cond2;\n' + code
code += 'FCSR = makeCCVector(FCSR, CC+1, cond1);\n'
code += 'FCSR = makeCCVector(FCSR, CC, cond2);\n'
iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)

22
arch/mips/isa/operands.isa
View file

@ -13,20 +13,35 @@ def operand_types {{
}};
def operands {{
#General Purpose Integer Reg Operands
'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2),
'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3),
'r31': ('IntReg', 'uw','R31','IsInteger', 4),
'R0': ('IntReg', 'uw','R0', 'IsInteger', 5),
#Operands used for Link or Syscall Insts
'R31': ('IntReg', 'uw','31','IsInteger', 4),
'R2': ('IntReg', 'uw','2', 'IsInteger', 5),
#Special Integer Reg operands
'HI': ('IntReg', 'uw','32', 'IsInteger', 6),
'LO': ('IntReg', 'uw','33', 'IsInteger', 7),
#Immediate Value operand
'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
#Floating Point Reg Operands
'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1),
'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2),
'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3),
#Special Floating Point Control Reg Operands
'FIR': ('FloatReg', 'uw', '32', 'IsFloating', 1),
'FCCR': ('FloatReg', 'uw', '33', 'IsFloating', 2),
'FEXR': ('FloatReg', 'uw', '34', 'IsFloating', 3),
'FENR': ('FloatReg', 'uw', '35', 'IsFloating', 3),
'FCSR': ('FloatReg', 'uw', '36', 'IsFloating', 3),
#Operands For Paired Singles FP Operations
'Fd1': ('FloatReg', 'sf', 'FD', 'IsFloating', 4),
'Fd2': ('FloatReg', 'sf', 'FD+1', 'IsFloating', 4),
@ -37,9 +52,10 @@ def operands {{
'Fr1': ('FloatReg', 'sf', 'FR', 'IsFloating', 7),
'Fr2': ('FloatReg', 'sf', 'FR+1', 'IsFloating', 7),
#Memory Operand
'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
#Program Counter Operands
'NPC': ('NPC', 'uw', None, ( None, None, 'IsControl' ), 4),
'NNPC':('NNPC', 'uw', None, ( None, None, 'IsControl' ), 4)
}};

62
arch/mips/isa_traits.cc
View file

@ -96,41 +96,15 @@ MipsISA::fpConvert(double fp_val, ConvertType cvt_type)
}
}
float
MipsISA::roundFP(float val)
{
return 1.5;
}
float
MipsISA::roundFP(uint64_t val)
{
return 1.5;
}
double
MipsISA::roundFP(double val)
MipsISA::roundFP(double val, int digits)
{
double trunc_val = trunc(val);
double fraction = val - trunc_val;
if (fraction < 0.5)
return val;
else
return val + 1;
}
float
MipsISA::truncFP(float val)
{
return 1.0;
}
double
MipsISA::truncFP(uint64_t val)
{
int trunc_val = (int) val;
return (double) trunc_val;
double digit_offset = pow(10.0,digits);
val = val * digit_offset;
val = val + 0.5;
val = floor(val);
val = val / digit_offset;
return val;
}
double
@ -141,26 +115,20 @@ MipsISA::truncFP(double val)
}
bool
MipsISA::unorderedFP(float val)
MipsISA::getFPConditionCode(uint32_t fcsr_reg, int cc)
{
return false;
//uint32_t cc_bits = xc->readFloatReg(35);
return false;//regFile.floatRegfile.getConditionCode(cc);
}
bool
MipsISA::unorderedFP(double val)
uint32_t
MipsISA::makeCCVector(uint32_t fcsr, int num, bool val)
{
return false;
}
int shift = (num == 0) ? 22 : num + 23;
bool
MipsISA::getFPConditionCode(int cc)
{
return false;
}
fcsr = fcsr | (val << shift);
void
MipsISA::setFPConditionCode(int num, bool val)
{
return fcsr;
}
#if FULL_SYSTEM

17
arch/mips/isa_traits.hh
View file

@ -31,7 +31,7 @@
#include "arch/mips/constants.hh"
#include "arch/mips/types.hh"
#include "arch/mips/regfile.hh"
#include "arch/mips/regfile/regfile.hh"
#include "arch/mips/faults.hh"
#include "arch/mips/utility.hh"
#include "base/misc.hh"
@ -138,19 +138,10 @@ namespace MipsISA
void copyRegs(ExecContext *src, ExecContext *dest);
uint64_t fpConvert(double fp_val, ConvertType cvt_type);
float roundFP(float val);
double roundFP(double val);
float roundFP(uint64_t val);
float truncFP(float val);
double truncFP(uint64_t val);
double roundFP(double val, int digits);
double truncFP(double val);
bool unorderedFP(float val);
bool unorderedFP(double val);
bool getFPConditionCode(int cc);
void setFPConditionCode(int num, bool val);
bool getFPConditionCode(uint32_t fcsr_reg, int cc);
uint32_t makeCCVector(uint32_t fcsr, int num, bool val);
// Machine operations

76
arch/mips/regfile/float_regfile.hh
View file

@ -47,14 +47,6 @@ namespace MipsISA
{
protected:
FloatReg32 regs[NumFloatRegs];
FloatReg32 fir;
FloatReg32 fcsr;
FloatReg32 fpcr;
FloatReg32 fccr;
FloatReg32 fexr;
FloatReg32 fenr;
public:
@ -65,8 +57,6 @@ namespace MipsISA
double readReg(int floatReg, int width)
{
using namespace std;
switch(width)
{
case SingleWidth:
@ -85,16 +75,23 @@ namespace MipsISA
FloatRegBits readRegBits(int floatReg, int width)
{
switch(width)
{
case SingleWidth:
if (floatReg < NumFloatArchRegs - 1) {
switch(width)
{
case SingleWidth:
return regs[floatReg];
case DoubleWidth:
return (FloatReg64)regs[floatReg + 1] << 32 | regs[floatReg];
default:
panic("Attempted to read a %d bit floating point register!", width);
}
} else {
if (width > SingleWidth)
assert("Control Regs are only 32 bits wide");
return regs[floatReg];
case DoubleWidth:
return (FloatReg64)regs[floatReg + 1] << 32 | regs[floatReg];
default:
panic("Attempted to read a %d bit floating point register!", width);
}
}
@ -144,44 +141,19 @@ namespace MipsISA
return NoFault;
}
MiscReg readFIR()
{
return fir;
}
Fault setFIR(const MiscReg &val)
{
fir = val;
return NoFault;
}
MiscReg readFCSR()
{
return fcsr;
}
Fault setFCSR(const MiscReg &val)
{
fcsr = val;
return NoFault;
}
MiscReg readFPCR()
{
return fpcr;
}
Fault setFPCR(const MiscReg &val)
{
fpcr = val;
return NoFault;
}
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
};
enum MiscFloatRegNums {
FIR = NumFloatArchRegs,
FCCR,
FEXR,
FENR,
FCSR
};
} // namespace MipsISA
#endif

31
arch/mips/regfile/int_regfile.hh
View file

@ -31,6 +31,7 @@
#include "arch/mips/types.hh"
#include "arch/mips/constants.hh"
#include "base/misc.hh"
#include "sim/faults.hh"
class Checkpoint;
@ -43,8 +44,6 @@ namespace MipsISA
{
protected:
IntReg regs[NumIntRegs];
IntReg hi;
IntReg lo;
public:
IntReg readReg(int intReg)
@ -58,33 +57,17 @@ namespace MipsISA
return NoFault;
}
IntReg readHi()
{
return hi;
}
Fault setHi(const IntReg &val)
{
hi = val;
return NoFault;
}
IntReg readLo()
{
return lo;
}
Fault setLo(const IntReg &val)
{
lo = val;
return NoFault;
}
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
};
enum MiscIntRegNums {
HI = NumIntArchRegs,
LO
};
} // namespace MipsISA
#endif

52
arch/mips/regfile.hh → arch/mips/regfile/regfile.hh
View file

@ -58,31 +58,7 @@ namespace MipsISA
MiscReg readMiscReg(int miscReg)
{
if (miscReg < CtrlReg_DepTag)
return miscRegFile.readReg(miscReg);
else {
switch (miscReg)
{
case Hi:
return intRegFile.readHi();
case Lo:
return intRegFile.readLo();
case FIR:
return floatRegFile.readFIR();
case FCSR:
return floatRegFile.readFCSR();
case FPCR:
return floatRegFile.readFPCR();
default:
panic("Invalid Misc. Reg. Access\n");
return 0;
}
}
return miscRegFile.readReg(miscReg);
}
MiscReg readMiscRegWithEffect(int miscReg,
@ -94,31 +70,7 @@ namespace MipsISA
Fault setMiscReg(int miscReg, const MiscReg &val)
{
if (miscReg < CtrlReg_DepTag)
return miscRegFile.setReg(miscReg, val);
else {
switch (miscReg)
{
case Hi:
return intRegFile.setHi(val);
case Lo:
return intRegFile.setLo(val);
case FIR:
return floatRegFile.setFIR(val);
case FCSR:
return floatRegFile.setFCSR(val);
case FPCR:
return floatRegFile.setFPCR(val);
default:
panic("Invalid Misc. Reg. Access\n");
return 0;
}
}
return miscRegFile.setReg(miscReg, val);
}
Fault setMiscRegWithEffect(int miscReg, const MiscReg &val,