a91ee5abc2
Special Regs (Hi,Lo,FCSR) are now added to the operands for use in decoder.isa.
Now it's back to just debugging execution of code for the release (those unaligned
memory access instruction pairs are still quite the pain i might add)
arch/mips/isa_traits.hh:
declare functions for .cc file
arch/mips/isa_traits.cc:
delete unnecessary overloaded functions
implement condition code functions
implement round function
arch/mips/isa/base.isa:
remove R31 constant... define in the operands.isa file instead
arch/mips/isa/decoder.isa:
wholesale changes once again to FP.
Now the FP Condition Codes are implemented and the FP programs can
run and complete to finish.
Use isnan() instead of my unorderedFP() function
Also, we now access special regs such as HI,LO,FCSR,etc. just like we do any other reg. operand
arch/mips/isa/operands.isa:
add more operands for special control regs in int and FP regfiles
arch/mips/isa/formats/branch.isa:
use R31 instead of r31
arch/mips/isa/formats/fp.isa:
use MakeCCVector to set Condition Codes in FCSR
arch/mips/regfile/float_regfile.hh:
treat control regs like any other reg. Just Index them after the regular architectural registers
arch/mips/regfile/int_regfile.hh:
treat hi,lo as regular int. regs w/special indexing
arch/mips/regfile/regfile.hh:
no longer need for special register accesses with their own function.
--HG--
rename : arch/mips/regfile.hh => arch/mips/regfile/regfile.hh
extra : convert_revision : 5d2f8fdb59606de2b2e9db3e0a085240561e479e
61 lines
2.2 KiB
Text
61 lines
2.2 KiB
Text
def operand_types {{
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'sb' : ('signed int', 8),
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'ub' : ('unsigned int', 8),
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'sh' : ('signed int', 16),
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'uh' : ('unsigned int', 16),
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'sw' : ('signed int', 32),
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'uw' : ('unsigned int', 32),
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'sd' : ('signed int', 64),
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'ud' : ('unsigned int', 64),
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'sf' : ('float', 32),
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'df' : ('float', 64),
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'qf' : ('float', 128)
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}};
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def operands {{
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#General Purpose Integer Reg Operands
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'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
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'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2),
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'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3),
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#Operands used for Link or Syscall Insts
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'R31': ('IntReg', 'uw','31','IsInteger', 4),
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'R2': ('IntReg', 'uw','2', 'IsInteger', 5),
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#Special Integer Reg operands
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'HI': ('IntReg', 'uw','32', 'IsInteger', 6),
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'LO': ('IntReg', 'uw','33', 'IsInteger', 7),
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#Immediate Value operand
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'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
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#Floating Point Reg Operands
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'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1),
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'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2),
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'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
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'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3),
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#Special Floating Point Control Reg Operands
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'FIR': ('FloatReg', 'uw', '32', 'IsFloating', 1),
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'FCCR': ('FloatReg', 'uw', '33', 'IsFloating', 2),
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'FEXR': ('FloatReg', 'uw', '34', 'IsFloating', 3),
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'FENR': ('FloatReg', 'uw', '35', 'IsFloating', 3),
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'FCSR': ('FloatReg', 'uw', '36', 'IsFloating', 3),
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#Operands For Paired Singles FP Operations
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'Fd1': ('FloatReg', 'sf', 'FD', 'IsFloating', 4),
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'Fd2': ('FloatReg', 'sf', 'FD+1', 'IsFloating', 4),
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'Fs1': ('FloatReg', 'sf', 'FS', 'IsFloating', 5),
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'Fs2': ('FloatReg', 'sf', 'FS+1', 'IsFloating', 5),
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'Ft1': ('FloatReg', 'sf', 'FT', 'IsFloating', 6),
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'Ft2': ('FloatReg', 'sf', 'FT+1', 'IsFloating', 6),
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'Fr1': ('FloatReg', 'sf', 'FR', 'IsFloating', 7),
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'Fr2': ('FloatReg', 'sf', 'FR+1', 'IsFloating', 7),
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#Memory Operand
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'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
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#Program Counter Operands
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'NPC': ('NPC', 'uw', None, ( None, None, 'IsControl' ), 4),
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'NNPC':('NNPC', 'uw', None, ( None, None, 'IsControl' ), 4)
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}};
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