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Small fixes to O3 model.

Browse source 
cpu/o3/alpha_dyn_inst.hh:
    Set the instResult using a function on the base dyn inst.
cpu/o3/bpred_unit_impl.hh:
    Don't need to reset the state.
cpu/o3/commit_impl.hh:
    Mark instructions as completed.

    Wait until all stores are written back to handle a fault.
cpu/o3/cpu.cc:
    Clear instruction lists when switching out.
cpu/o3/lsq_unit.hh:
    Allow wbEvent to be set externally.
cpu/o3/lsq_unit_impl.hh:
    Mark instructions as completed properly.  Also use events for writing back stores even if there is a hit in the dcache.

--HG--
extra : convert_revision : 172ad088b75ac31e848a5040633152b5c051444c
This commit is contained in:
Kevin Lim 2006-05-11 15:39:02 -04:00
parent 92838fd35e
commit 8a9416ef8d
6 changed files with 38 additions and 28 deletions
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8
cpu/o3/alpha_dyn_inst.hh
View file

@ -183,25 +183,25 @@ class AlphaDynInst : public BaseDynInst<Impl>
void setIntReg(const StaticInst *si, int idx, uint64_t val)
{
this->cpu->setIntReg(_destRegIdx[idx], val);
this->instResult.integer = val;
BaseDynInst<Impl>::setIntReg(si, idx, val);
}
void setFloatRegSingle(const StaticInst *si, int idx, float val)
{
this->cpu->setFloatRegSingle(_destRegIdx[idx], val);
this->instResult.fp = val;
BaseDynInst<Impl>::setFloatRegSingle(si, idx, val);
}
void setFloatRegDouble(const StaticInst *si, int idx, double val)
{
this->cpu->setFloatRegDouble(_destRegIdx[idx], val);
this->instResult.dbl = val;
BaseDynInst<Impl>::setFloatRegDouble(si, idx, val);
}
void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
{
this->cpu->setFloatRegInt(_destRegIdx[idx], val);
this->instResult.integer = val;
BaseDynInst<Impl>::setFloatRegInt(si, idx, val);
}
/** Returns the physical register index of the i'th destination

2
cpu/o3/bpred_unit_impl.hh
View file

@ -107,11 +107,13 @@ template <class Impl>
void
TwobitBPredUnit<Impl>::takeOverFrom()
{
/*
for (int i = 0; i < Impl::MaxThreads; ++i)
RAS[i].reset();
BP.reset();
BTB.reset();
*/
}
template <class Impl>

9
cpu/o3/commit_impl.hh
View file

@ -1117,6 +1117,10 @@ head_inst->isWriteBarrier())*/
panic("Barrier instructions are not handled yet.\n");
}
if (!head_inst->isStore()) {
head_inst->setCompleted();
}
// Check if the instruction caused a fault. If so, trap.
Fault inst_fault = head_inst->getFault();
@ -1126,6 +1130,11 @@ head_inst->isWriteBarrier())*/
DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
head_inst->seqNum, head_inst->readPC());
if (iewStage->hasStoresToWB()) {
DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
return false;
}
assert(!thread[tid]->inSyscall);
thread[tid]->inSyscall = true;

6
cpu/o3/cpu.cc
View file

@ -666,6 +666,12 @@ FullO3CPU<Impl>::switchOut(Sampler *sampler)
rename.switchOut();
iew.switchOut();
commit.switchOut();
instList.clear();
while (!removeList.empty()) {
removeList.pop();
}
if (tickEvent.scheduled())
tickEvent.squash();
sampler->signalSwitched();

2
cpu/o3/lsq_unit.hh
View file

@ -82,7 +82,9 @@ class LSQUnit {
/** The writeback event for the store. Needed for store
* conditionals.
*/
public:
Event *wbEvent;
private:
/** The pointer to the LSQ unit that issued the store. */
LSQUnit<Impl> *lsqPtr;
};

39
cpu/o3/lsq_unit_impl.hh
View file

@ -672,11 +672,6 @@ LSQUnit<Impl>::writebackStores()
req->paddr, *(req->data),
storeQueue[storeWBIdx].inst->seqNum);
// if (fault != NoFault) {
//What should we do if there is a fault???
//for now panic
// panic("Page Table Fault!!!!!\n");
// }
switch(storeQueue[storeWBIdx].size) {
case 1:
cpu->write(req, (uint8_t &)storeQueue[storeWBIdx].data);
@ -693,8 +688,16 @@ LSQUnit<Impl>::writebackStores()
default:
panic("Unexpected store size!\n");
}
if (!(req->flags & LOCKED)) {
storeQueue[storeWBIdx].inst->setCompleted();
}
if (dcacheInterface) {
assert(!req->completionEvent);
StoreCompletionEvent *store_event = new
StoreCompletionEvent(storeWBIdx, NULL, this);
req->completionEvent = store_event;
MemAccessResult result = dcacheInterface->access(req);
if (isStalled() &&
@ -710,16 +713,12 @@ LSQUnit<Impl>::writebackStores()
if (result != MA_HIT && dcacheInterface->doEvents()) {
typename IEW::LdWritebackEvent *wb = NULL;
if (req->flags & LOCKED) {
// Stx_C does not generate a system port transaction.
/*
if (cpu->lockFlag && cpu->lockAddr == req->paddr) {
req->result=1;
} else {
req->result = 0;
}
*/
wb = new typename IEW::LdWritebackEvent(storeQueue[storeWBIdx].inst,
iewStage);
// Stx_C should not generate a system port transaction,
// but that might be hard to accomplish.
wb = new typename
IEW::LdWritebackEvent(storeQueue[storeWBIdx].inst,
iewStage);
store_event->wbEvent = wb;
}
DPRINTF(LSQUnit,"D-Cache Write Miss!\n");
@ -727,12 +726,6 @@ LSQUnit<Impl>::writebackStores()
DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
storeQueue[storeWBIdx].inst->seqNum);
// Will stores need their own kind of writeback events?
// Do stores even need writeback events?
assert(!req->completionEvent);
req->completionEvent = new
StoreCompletionEvent(storeWBIdx, wb, this);
lastDcacheStall = curTick;
// _status = DcacheMissStall;
@ -766,10 +759,8 @@ LSQUnit<Impl>::writebackStores()
typename IEW::LdWritebackEvent *wb =
new typename IEW::LdWritebackEvent(storeQueue[storeWBIdx].inst,
iewStage);
wb->schedule(curTick);
store_event->wbEvent = wb;
}
completeStore(storeWBIdx);
}
incrStIdx(storeWBIdx);