Dependecy graph code moved into its own class.
This requires the changes to the functional units, which is in the next check in.
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
IEW and IQ code cleanup and reorganization.
cpu/o3/inst_queue.cc:
Dependency graph code moved into its own class now.
cpu/o3/inst_queue.hh:
IEW/IQ code cleanup and reorganization.
Dependecy graph code moved into its own class.
cpu/o3/inst_queue_impl.hh:
IEW/IQ code cleanup and reorganization.
Dependecy graph code moved into its own class.
Issue loop cleaned up, with completion events for functional units now used more correctly (before they weren't used for multi-cycle ops with pipelined FU's).
--HG--
extra : convert_revision : 35e50192df6f71dc81d46a73fdd65f7ec07c10e4
SConscript:
Split off activity/idling code into its own class to do the processing separately.
cpu/o3/alpha_cpu_builder.cc:
cpu/o3/alpha_params.hh:
Activity stuff. This is mostly for debugging and may be removed later on (or changed to enable/disable activity idling).
cpu/o3/cpu.cc:
Move activity idling stuff mostly into its own class, so it no longer clutters this file.
cpu/o3/cpu.hh:
Move activity idling stuff into its own class.
python/m5/objects/AlphaFullCPU.py:
Add parameter for initial activity value.
--HG--
extra : convert_revision : f32f7cc03895dc07ab57ddba78c5402a1a8b0f1a
TimingSimpleCPU. Not there yet.
cpu/simple/atomic.cc:
Only read SC result if store was an SC.
Don't fake SC here; fake it in PhysicalMemory so
all CPU models can share in the joy.
cpu/simple/timing.cc:
Don't forget to checkForInterrupts().
Only fetch subsequent instruction if we're still running
(i.e. not quiesced).
dev/io_device.hh:
Initialize port pointer in SendEvent object.
mem/physical.cc:
Move fake SC "implementation" here from AtomicSimpleCPU.
mem/request.hh:
Initialize flags to all clear, not uninitialized.
Otherwise we can't reliably look at flags w/o explicitly
setting them every time we create a request.
--HG--
extra : convert_revision : ae7601ce6fb54c54e19848aa5391327f9a6e61a6
add sinic back to sconscript file
SConscript:
add sinic back to sconscript file
dev/ide_disk.hh:
add regStats() back to ide_disk
--HG--
extra : convert_revision : a25083993190ceadde977283fbd1fb64e8e7ef86
SConscript:
Comment out sinic for now... needs to be fixed to compile under newmem.
configs/test/SysPaths.py:
Fix paths.
configs/test/fs.py:
SimpleCPU -> AtomicSimpleCPU
Fix vmlinux path
cpu/simple/atomic.cc:
Fix suspendContext() so quiesce works.
Don't forget to checkForInterrupts().
cpu/simple/base.cc:
Minor fix to interrupt check code.
dev/ide_disk.hh:
Don't declare regStats() in header since it's not in
.cc file anymore (will need to add it back in when
stats are added back).
dev/io_device.cc:
Set packet dest to Packet::Broadcast.
dev/pciconfigall.cc:
Set PCI config packet result to Success.
python/m5/objects/Root.py:
Add debug object to Root so things like break_cycles
can be set from command line.
--HG--
extra : convert_revision : aa1c652fe589784e753e13ad9acb0cd5f3b6eafb
cpu/checker/cpu.cc:
Fixups for fetch fault being sent with the instruction.
cpu/o3/fetch_impl.hh:
cpu/ozone/front_end_impl.hh:
Send any faults generated at fetch along with a fake nop instruction to the back end. This avoids having to use direct communication to check if the entire front end has drained; it is naturally handled through the nop's fault being handled when it reaches the head of commit.
cpu/ozone/front_end.hh:
Add extra status TrapPending.
cpu/ozone/lw_back_end_impl.hh:
Fetch fault handled through a dummy nop carrying the fetch fault.
Avoid putting Nops on the exeList.
--HG--
extra : convert_revision : 8d9899748b34c204763a49c48a9b5113864f5789
TimingSimpleCPU, which use atomic and timing memory accesses
respectively. Common code is factored into the BaseSimpleCPU class.
AtomicSimpleCPU includes an option (simulate_stalls) to add delays
based on the estimated latency reported by the atomic accesses.
Plain old "SimpleCPU" is gone; I have not updated all the config
files (just test/test.py).
Also fixes to get timing accesses working in new memory model and
to get split-phase memory instruction definitions working with
new memory model as well.
arch/alpha/isa/main.isa:
Need to include packet_impl.h for functions that use Packet objects.
arch/alpha/isa/mem.isa:
Change completeAcc() methods to take Packet object pointers.
Also split out StoreCond template for completeAcc(), since
that's the only one that needs write_result and we get an
unused variable warning if we always have it in there.
build/SConstruct:
Update list of recognized CPU model names.
configs/test/test.py:
Change SimpleCPU to AtomicSimpleCPU.
cpu/SConscript:
Define sources for new CPU models.
Add split memory access methods to CPU model signatures.
cpu/cpu_models.py:
cpu/static_inst.hh:
Define new CPU models.
cpu/simple/base.cc:
cpu/simple/base.hh:
Factor out pieces specific to Atomic or Timing models.
mem/bus.cc:
Bus needs to be able to route timing packets based on explicit dest
so responses can get back to requester. Set dest to Packet::Broadcast
to indicate that dest should be derived from address.
Also set packet src field based on port from which packet is sent.
mem/bus.hh:
Set packet src field based on port from which packet is sent.
mem/packet.hh:
Define Broadcast destination address to indicate that
packet should be routed based on address.
mem/physical.cc:
Set packet dest on response so packet is routed
back to requester properly.
mem/port.cc:
Flag blob packets as Broadcast.
python/m5/objects/PhysicalMemory.py:
Change default latency to be 1 cycle.
--HG--
rename : cpu/simple/cpu.cc => cpu/simple/base.cc
rename : cpu/simple/cpu.hh => cpu/simple/base.hh
extra : convert_revision : e9646af6406a20c8c605087936dc4683375c2132
cpu/ozone/cpu.hh:
Updates for sampler.
cpu/ozone/cpu_impl.hh:
Updates for sampler, checker.
cpu/ozone/inorder_back_end.hh:
Sampler updates. Also support old memory system.
--HG--
extra : convert_revision : 33ebe38e4c08d49c6af84032b819533b784b4fe8
cpu/o3/alpha_cpu.hh:
Update for sampler to work properly. Also code cleanup.
cpu/o3/alpha_cpu_builder.cc:
cpu/o3/alpha_dyn_inst.hh:
Updates to support the checker.
cpu/o3/alpha_cpu_impl.hh:
Updates to support the checker. Also general code cleanup.
cpu/o3/alpha_dyn_inst_impl.hh:
Code cleanup.
cpu/o3/alpha_params.hh:
Updates to support the checker. Also supports trap latencies set through the parameters.
cpu/o3/commit.hh:
Supports sampler, checker. Code cleanup.
cpu/o3/commit_impl.hh:
Updates to support the sampler and checker, as well as general code cleanup.
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
Support sampler and checker.
cpu/o3/decode_impl.hh:
Supports sampler.
cpu/o3/fetch.hh:
Supports sampler. Also update to hold the youngest valid SN fetch has seen to ensure that the entire pipeline has been drained.
cpu/o3/fetch_impl.hh:
Sampler updates. Also be sure to not fetches to uncached space (bad path).
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
Sampler updates.
cpu/o3/lsq_unit_impl.hh:
Supports checker.
cpu/o3/regfile.hh:
No need for accessing xcProxies directly.
cpu/o3/rename.hh:
cpu/o3/rename_impl.hh:
Sampler support.
--HG--
extra : convert_revision : 03881885dd50ebbca13ef31f31492fd4ef59121c
base/traceflags.py:
build/SConstruct:
cpu/SConscript:
cpu/cpu_models.py:
Add in Checker.
cpu/base.cc:
Add in checker support. Also XC status starts off as suspended.
cpu/base.hh:
Add in checker.
--HG--
extra : convert_revision : 091b5cc83e837858adb681ef0137a0beb30bd1b2
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
Sampling fixes. The CPU models may switch during a quiesce period, so it needs to be sure to wake up the right XC.
cpu/exec_context.hh:
Return the EndQuiesceEvent specifically.
sim/pseudo_inst.cc:
Return the EndQuiesceEvent specifically for sampling.
--HG--
extra : convert_revision : f9aa1fc8d4db8058f05319cb6a3d4605ce93b4c8
arch/alpha/isa/decoder.isa:
Mark store conditionals as serializing. This is slightly higher over head than they truly have in the 264, but it's close. Normally they block any other instructions from entering the IQ until the IQ is empty. This is higher overhead because it waits until the ROB is empty.
Also mark RPCC as unverifiable. The checker will just grab the value from the instruction and assume it's correct.
cpu/static_inst.hh:
Add unverifiable flag, specifically for the CheckerCPU.
--HG--
extra : convert_revision : cbc34d1f2f5b07105d31d4bd8f19edae2cf8158e
Get rid of more unneeded includes.
base/hostinfo.cc:
base/inet.cc:
base/remote_gdb.cc:
cpu/simple/cpu.cc:
dev/alpha_console.cc:
dev/disk_image.cc:
dev/ns_gige.cc:
dev/sinic.cc:
mem/physical.cc:
sim/param.cc:
sim/process.cc:
sim/pseudo_inst.cc:
test/cprintftest.cc:
Get rid of more unneeded includes.
--HG--
extra : convert_revision : f531ae40db3787f2c55df7d251f251ecae4ab731
into zeep.pool:/z/saidi/work/m5.newmem
base/loader/elf_object.cc:
removed SPARC32PLUS since it doesn't work.
--HG--
extra : convert_revision : 620a1c75cdeefbeeb97383d92335cf319d9c9444
arch/sparc/SConscript:
arch/sparc/process.cc:
base/loader/elf_object.cc:
Add support for sparc/solaris syscall emulation.
--HG--
extra : convert_revision : e22df8476e5c6ae14db1cab1d94d01c0578ea06c
into zeep.pool:/z/saidi/work/m5.nm_m5_pull
SConscript:
dram memory needs to be converted to newmem before we can use it
dev/ide_ctrl.cc:
don't need this printing in newmem
dev/ide_disk.cc:
will read stats in next commit
dev/sinic.cc:
merge sinic from head, still needs work
--HG--
extra : convert_revision : b9aabd8c7814d07d54ce6f971aad3ec349fa24e1
Special Regs (Hi,Lo,FCSR) are now added to the operands for use in decoder.isa.
Now it's back to just debugging execution of code for the release (those unaligned
memory access instruction pairs are still quite the pain i might add)
arch/mips/isa_traits.hh:
declare functions for .cc file
arch/mips/isa_traits.cc:
delete unnecessary overloaded functions
implement condition code functions
implement round function
arch/mips/isa/base.isa:
remove R31 constant... define in the operands.isa file instead
arch/mips/isa/decoder.isa:
wholesale changes once again to FP.
Now the FP Condition Codes are implemented and the FP programs can
run and complete to finish.
Use isnan() instead of my unorderedFP() function
Also, we now access special regs such as HI,LO,FCSR,etc. just like we do any other reg. operand
arch/mips/isa/operands.isa:
add more operands for special control regs in int and FP regfiles
arch/mips/isa/formats/branch.isa:
use R31 instead of r31
arch/mips/isa/formats/fp.isa:
use MakeCCVector to set Condition Codes in FCSR
arch/mips/regfile/float_regfile.hh:
treat control regs like any other reg. Just Index them after the regular architectural registers
arch/mips/regfile/int_regfile.hh:
treat hi,lo as regular int. regs w/special indexing
arch/mips/regfile/regfile.hh:
no longer need for special register accesses with their own function.
--HG--
rename : arch/mips/regfile.hh => arch/mips/regfile/regfile.hh
extra : convert_revision : 5d2f8fdb59606de2b2e9db3e0a085240561e479e
cpu/base_dyn_inst.hh:
Remove snoop function (did not mean to commit it).
cpu/ozone/back_end_impl.hh:
Set instruction as having its result ready, not completed.
cpu/ozone/cpu.hh:
Fixes for store conditionals. Use an additional lock addr list to make sure that the access is valid. I don't know if this is fully necessary, but it gives me a peace of mind (at some performance cost).
Make sure to schedule for cycles(1) and not just 1 cycle in the future as tick = 1ps.
Also support the new Checker.
cpu/ozone/cpu_builder.cc:
Add parameter for maxOutstandingMemOps so it can be set through the config.
Also add in the checker. Right now it's a BaseCPU simobject, but that may change in the future.
cpu/ozone/cpu_impl.hh:
Add support for the checker. For now there's a dynamic cast to convert the simobject passed back from the builder to the proper Checker type. It's ugly, but only happens at startup, and is probably a justified use of dynamic cast.
Support switching out/taking over from other CPUs.
Correct indexing problem for float registers.
cpu/ozone/dyn_inst.hh:
Add ability for instructions to wait on memory instructions in addition to source register instructions. This is needed for memory dependence predictors and memory barriers.
cpu/ozone/dyn_inst_impl.hh:
Support waiting on memory operations.
Use "resultReady" to differentiate an instruction having its registers produced vs being totally completed.
cpu/ozone/front_end.hh:
Support switching out.
Also record if an interrupt is pending.
cpu/ozone/front_end_impl.hh:
Support switching out. Also support stalling the front end if an interrupt is pending.
cpu/ozone/lw_back_end.hh:
Add checker in.
Support switching out.
Support memory barriers.
cpu/ozone/lw_back_end_impl.hh:
Lots of changes to get things to work right.
Faults, traps, interrupts all wait until all stores have written back (important).
Memory barriers are supported, as is the general ability for instructions to be dependent on other memory instructions.
cpu/ozone/lw_lsq.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
cpu/ozone/lw_lsq_impl.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
Support the checker CPU. Marks instructions as completed once the functional access is done (which has to be done for the checker to be able to verify results).
cpu/ozone/simple_params.hh:
Add max outstanding mem ops parameter.
python/m5/objects/OzoneCPU.py:
Add max outstanding mem ops, checker.
--HG--
extra : convert_revision : f4d408e1bb1f25836a097b6abe3856111e950c59
Intended Use:
A SimObject will call the serializer when it needs the state to be serializable (i.e. switchCPUs, checkpoint, switch memory access model). It will call the requestSeialization() function.
The Serializer will signal all the objects in its list to drain their state via the SimObject method drain(). Drain() has a default implementation to just signal done.
When each object is drained it will signal the Serializer that it has drained via the signalDrained() function.
The Serializer will collect these signals, when all have drained it will signal the initial requestor via serializationComplete() method in the SimObject.
Once that object is done, it will signal the Serializer to resumeExecution().
The Serializer will signal all the objects in its list to resume via the resume() method on the SimObject.
SConscript:
Add serializer object to build list
sim/sim_object.cc:
Add default behavior for drain (just signal finished, must be overided if you really must drain something)
sim/sim_object.hh:
Add functions for serializer
--HG--
extra : convert_revision : 15aa2d1b42010c2d703bef9114c11d079c216170
cpu/o3/alpha_dyn_inst.hh:
Set the instResult using a function on the base dyn inst.
cpu/o3/bpred_unit_impl.hh:
Don't need to reset the state.
cpu/o3/commit_impl.hh:
Mark instructions as completed.
Wait until all stores are written back to handle a fault.
cpu/o3/cpu.cc:
Clear instruction lists when switching out.
cpu/o3/lsq_unit.hh:
Allow wbEvent to be set externally.
cpu/o3/lsq_unit_impl.hh:
Mark instructions as completed properly. Also use events for writing back stores even if there is a hit in the dcache.
--HG--
extra : convert_revision : 172ad088b75ac31e848a5040633152b5c051444c
