Fixes for regression build errors.
--HG-- extra : convert_revision : 1f59c853cb0e327d7cf586021b5139f1242e4f28
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36581a5342
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c7e7d07ec3
4 changed files with 6 additions and 7 deletions
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@ -157,8 +157,7 @@ CPUExecContext::takeOverFrom(ExecContext *oldContext)
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cpu_id = oldContext->readCpuId();
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#if !FULL_SYSTEM
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func_exe_inst = oldContext->readFuncExeInst();
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#endif
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#else
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EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent();
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if (quiesce) {
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// Point the quiesce event's XC at this XC so that it wakes up
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@ -168,6 +167,7 @@ CPUExecContext::takeOverFrom(ExecContext *oldContext)
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if (quiesceEvent) {
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quiesceEvent->xc = proxy;
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}
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#endif
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storeCondFailures = 0;
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@ -171,8 +171,7 @@ AlphaFullCPU<Impl>::AlphaXC::takeOverFrom(ExecContext *old_context)
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setCpuId(old_context->readCpuId());
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#if !FULL_SYSTEM
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thread->funcExeInst = old_context->readFuncExeInst();
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#endif
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#else
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EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
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if (other_quiesce) {
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// Point the quiesce event's XC at this XC so that it wakes up
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@ -184,6 +183,7 @@ AlphaFullCPU<Impl>::AlphaXC::takeOverFrom(ExecContext *old_context)
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}
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// storeCondFailures = 0;
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cpu->lockFlag = false;
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#endif
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old_context->setStatus(ExecContext::Unallocated);
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@ -89,7 +89,6 @@ class OzoneCPU : public BaseCPU
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typedef typename Impl::FrontEnd FrontEnd;
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typedef typename Impl::BackEnd BackEnd;
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typedef typename Impl::DynInst DynInst;
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typedef typename Impl::DynInst DynInst;
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typedef typename Impl::DynInstPtr DynInstPtr;
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typedef TheISA::MiscReg MiscReg;
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@ -934,8 +934,7 @@ OzoneCPU<Impl>::OzoneXC::takeOverFrom(ExecContext *old_context)
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setCpuId(old_context->readCpuId());
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#if !FULL_SYSTEM
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setFuncExeInst(old_context->readFuncExeInst());
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#endif
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#else
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EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
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if (other_quiesce) {
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// Point the quiesce event's XC at this XC so that it wakes up
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@ -947,6 +946,7 @@ OzoneCPU<Impl>::OzoneXC::takeOverFrom(ExecContext *old_context)
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}
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// storeCondFailures = 0;
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cpu->lockFlag = false;
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#endif
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old_context->setStatus(ExecContext::Unallocated);
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}
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