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1440 commits

Author SHA1 Message Date
Korey Sewell
97a04b16eb mips-merge: merge hello world regress for inorder cpu 
w/latest changes
 2009-05-13 02:02:05 -04:00
Nathan Binkert
82c9e6a5fc gcc: work around a bogus gcc error 2009-05-12 22:33:05 -07:00
Korey Sewell
1f4c954590 inorder-mips: Remove eaComp & memAcc; use 'visible' eaComp 
Inorder expects eaComp to be visible through StaticInst object. This mirrors a similar change
to ALPHA... Needs to be done for SPARC and whatever other ISAs want to use InOrderCPU
 2009-05-13 01:26:46 -04:00
Korey Sewell
bc69e7947c arch-mips: add regWidth constant to float regfile 2009-05-13 01:26:38 -04:00
Korey Sewell
5d810c30e6 alpha-isa: add mt.hh so it can compile with inorder 2009-05-12 20:18:34 -04:00
Korey Sewell
db2b721380 inorder-tlb-cunit: merge the TLB as implicit to any memory access 
TLBUnit no longer used and we also get rid of memAccSize and memAccFlags functions added to ISA and StaticInst
since TLB is not a separate resource to acquire. Instead, TLB access is done before any read/write to memory
and the result is checked before it's sent out to memory.
* * *
 2009-05-12 15:01:16 -04:00
Korey Sewell
6211fe5d2e inorder-float: Fix storage of FP results 
inorder was incorrectly storing FP values and confusing the integer/fp storage view of floating point operations. A big issue was knowing trying to infer when were doing single or double precision access
because this lets you know the size of value to store (32-64 bits). This isnt exactly straightforward since alpha uses all 64-bit regs while mips/sparc uses a dual-reg view. by getting this value from
the actual floating point register file, the model can figure out what it needs to store
 2009-05-12 15:01:15 -04:00
Korey Sewell
1c7e988272 inorder-mem: skeleton support for prefetch/writehints 2009-05-12 15:01:15 -04:00
Korey Sewell
5127ea226a inorder-unified-tlb: use unified TLB instead of old TLB model 2009-05-12 15:01:14 -04:00
Korey Sewell
2012202b06 inorder/alpha-isa: create eaComp object visible to StaticInst through ISA 
Remove subinstructions eaComp/memAcc since unused in CPU Models. Instead, create eaComp that is visible from StaticInst object. Gives InOrder model capability of generating address without actually initiating access
* * *
 2009-05-12 15:01:14 -04:00
Korey Sewell
b569f8f0ed inorder-bpred: edits to handle non-delay-slot ISAs 
Changes so that InOrder can work for a non-delay-slot ISA like Alpha. Typically, changes have to do with handling misspeculated branches at different points in pipeline
 2009-05-12 15:01:14 -04:00
Korey Sewell
1c8dfd9254 inorder-alpha-port: initial inorder support of ALPHA 
Edit AlphaISA to support the inorder model. Mostly alternate constructor functions and also a few skeleton multithreaded support functions
* * *
Remove namespace from header file. Causes compiler issues that are hard to find
* * *
Separate the TLB from the CPU and allow it to live in the TLBUnit resource. Give CPU accessor functions for access and also bind at construction time
* * *
Expose memory access size and flags through instruction object
(temporarily memAccSize and memFlags to get TLB stuff working.)
 2009-05-12 15:01:13 -04:00
Korey Sewell
63db33c4b1 isa-parser: made a few changes, but not author-worthy 2009-05-12 15:01:13 -04:00
Gabe Black
7146eb79f1 X86: Precompute the default and alternate address and operand size and the stack size. 2009-04-26 16:49:24 -07:00
Gabe Black
b6bfe8af26 X86: Split out the internal memory space from the regular translate() and precompute mode. 2009-04-26 16:48:44 -07:00
Gabe Black
4ee34dfb4e X86: Centralize updates to the handy M5 reg. 2009-04-26 16:47:48 -07:00
Gabe Black
2f34a7eaeb X86: Tell the function that sends int messages who to send to instead of figuring it out itself. 2009-04-26 02:09:27 -07:00
Gabe Black
88ab4bb257 X86: Make the local APICs register themselves with the IO APIC. 
This is a hack so that the IO APIC can figure out information about the local
APICs. The local APICs still have no way to find out about each other.
Ideally, when the local APICs update state that's relevant to somebody else,
they'd send an update to everyone. Without being able to do a broadcast, that
would still require knowing who else there is to notify. Other broadcasts are
implemented using assumptions that may not always be true.
 2009-04-26 02:09:13 -07:00
Gabe Black
c5e2cf841d X86: Record the initial APIC ID which identifies an APIC in M5. 
The ID as exposed to software can be changed. Tracking those changes in M5
would be cumbersome, especially since there's no guarantee the IDs will remain
unique.
 2009-04-26 02:06:21 -07:00
Gabe Black
9d0fa27d09 SPARC: Tighten up the clone system call and SPARCs copyRegs. 2009-04-24 23:11:21 -07:00
Gabe Black
ee7055c289 X86: Put the StoreCheck flag with the others, and don't collide with other flags. 2009-04-23 01:43:00 -07:00
Nathan Binkert
43c7698f49 arm: include missing file for arm 2009-04-21 15:40:26 -07:00
Nathan Binkert
50f1570352 arm: Unify the ARM tlb. We forgot about this when we did the rest. 
This code compiles, but there are no tests still
 2009-04-21 15:40:25 -07:00
Steve Reinhardt
52b6764f31 syscall: Resolve conflicts between m5threads and Gabe's recent SE changes. 2009-04-21 08:17:36 -07:00
Daniel Sanchez
b0e9654f86 Commit m5threads package. 
This patch adds limited multithreading support in syscall-emulation
mode, by using the clone system call.  The clone system call works
for Alpha, SPARC and x86, and multithreaded applications run
correctly in Alpha and SPARC.
 2009-04-21 08:17:36 -07:00
Gabe Black
089b384086 X86: Fix the functions that manipulate large bit arrays in the local APIC. 2009-04-19 13:47:15 -07:00
Gabe Black
eee74ba427 X86: Fix up a copyright. 2009-04-19 13:17:35 -07:00
Gabe Black
6910baa015 X86: Fix how the TLB handles the storecheck flag. 2009-04-19 04:57:51 -07:00
Gabe Black
0a6ff60caa X86: Recognize and handle the lock legacy prefix. 2009-04-19 04:57:28 -07:00
Gabe Black
61edc9ba66 X86: Implement a locking version of XADD. 2009-04-19 04:56:49 -07:00
Gabe Black
209cfc89fd X86: Implement a locking version of BTC. 2009-04-19 04:56:45 -07:00
Gabe Black
e475cf85f0 X86: Implement a locking version of BTR. 2009-04-19 04:56:43 -07:00
Gabe Black
43f58927d6 X86: Implement a locking version of CMPXCHG. 2009-04-19 04:56:40 -07:00
Gabe Black
b493906eb9 X86: Implement a locking version of BTS. 2009-04-19 04:56:36 -07:00
Gabe Black
985d959ea6 X86: Implement a locking version of DEC. 2009-04-19 04:56:34 -07:00
Gabe Black
4f2d4f466a X86: Implement a locking version of INC. 2009-04-19 04:56:31 -07:00
Gabe Black
2394f73f90 X86: Implement a locking version of NEG. 2009-04-19 04:56:28 -07:00
Gabe Black
9b9b7a412c X86: Implement a locking version of NOT. 2009-04-19 04:56:25 -07:00
Gabe Black
b8f81c62a2 X86: Implement a locking version of XCHG. 2009-04-19 04:56:22 -07:00
Gabe Black
750f5a0a67 X86: Implement a locking version of XOR. 2009-04-19 04:56:20 -07:00
Gabe Black
cfb289ebeb X86: Implement a locking version of SUB. 2009-04-19 04:56:16 -07:00
Gabe Black
789b3191b9 X86: Implement a locking version of AND. 2009-04-19 04:56:14 -07:00
Gabe Black
e742cad6f4 X86: Implement a locking version of SBB. 2009-04-19 04:56:11 -07:00
Gabe Black
193265c6e5 X86: Implement a locking version of ADC. 2009-04-19 04:56:08 -07:00
Gabe Black
2f607b882c X86: Implement a locking version of OR. 2009-04-19 04:56:06 -07:00
Gabe Black
a7f79c9049 X86: Implement a locking version of ADD. 2009-04-19 04:56:02 -07:00
Gabe Black
d90456a486 X86: Implement the stul microop. 
This microop does a store and unlocks the requested address. The RISC86
microop ISA doesn't seem to have an equivalent to this, so I'm guessing that
the store following an ldstl is automatically unlocking. We don't do it this
way for performance reasons since the behavior is the same.
 2009-04-19 04:55:58 -07:00
Gabe Black
d2554ff030 X86: Implement the ldstl microop. 
This microop does a load, checks that a store would succeed, and locks the
requested address.
 2009-04-19 04:55:43 -07:00
Gabe Black
3e5f487663 Memory: Rename LOCKED for load locked store conditional to LLSC. 2009-04-19 04:25:01 -07:00
Gabe Black
ca85981478 SE mode: Make keeping track of the number of syscalls less hacky. 2009-04-19 04:15:32 -07:00
Gabe Black
5f164ba720 X86: Actually handle 16 bit mode modrm. 2009-04-19 04:14:31 -07:00
Gabe Black
93cccf7d19 X86: Make the TEST instruction set all the flags it's supposed to. 2009-04-19 04:14:16 -07:00
Gabe Black
f82c123242 X86: Implement broadcast IPIs. 2009-04-19 04:14:01 -07:00
Gabe Black
829e424353 X86: Fix the ordering of the vendor string reported by CPUID. 2009-04-19 04:13:45 -07:00
Gabe Black
18b3863127 X86: Only recognize the first startup IPI after INIT or reset. 2009-04-19 03:56:36 -07:00
Gabe Black
4d32cd10ce X86: Use recvResponse to implement the idle bit in the Local APIC ICR. 2009-04-19 03:56:24 -07:00
Gabe Black
bdda224d41 X86: Add a function which gets called when an interrupt message has been delivered. 2009-04-19 03:54:11 -07:00
Gabe Black
3eed59768c X86: Explicitly use the right width in a few places that need a 64 bit value. 2009-04-19 03:47:59 -07:00
Gabe Black
8761057c78 X86: Keep track of the pioAddr for the local APIC. 2009-04-19 03:47:12 -07:00
Gabe Black
038225a6ca X86: Implement far jmp. 2009-04-19 03:42:41 -07:00
Gabe Black
3b1b21cb15 X86: Some segment selectors can be used when "NULL". 2009-04-19 03:41:10 -07:00
Gabe Black
a0cc081997 X86: Fix a bug in the chks microop where it ignored that it found a fault. 2009-04-19 03:40:08 -07:00
Gabe Black
f2ff5b9249 X86: Make the interrupt entering microcode record the value to use, not actually use it. 2009-04-19 03:36:57 -07:00
Gabe Black
35eea4191b X86: LEA calculates an address before segmentation. 2009-04-19 03:24:51 -07:00
Gabe Black
bdd55ec8b6 X86: Implement the save machine status word instruction (SMSW). 2009-04-19 03:22:38 -07:00
Gabe Black
d86cd1d2a0 X86: Implement the load machine status word instruction (LMSW). 2009-04-19 03:17:14 -07:00
Gabe Black
eba640c963 X86: Only use %eax to select a function and look like we support sse2. 2009-04-19 03:11:24 -07:00
Gabe Black
27e54982b4 X86: Fix the mov to segment selector in real mode instruction microcode. 2009-04-19 03:08:40 -07:00
Gabe Black
633c96bd85 X86: The startup IPI delivery mode is not reserved. 2009-04-19 03:01:46 -07:00
Gabe Black
08f021aad0 X86: Implement the STARTUP IPI. 2009-04-19 02:56:03 -07:00
Gabe Black
d277feb925 X86: Implement the INIT IPI. 2009-04-19 02:53:00 -07:00
Gabe Black
a340b214cf X86: Fix the halt microop. 2009-04-19 02:51:09 -07:00
Gabe Black
641513fe08 X86: Start implementing the interrupt command register in the local APIC. 2009-04-19 02:43:22 -07:00
Gabe Black
05b5861419 X86: Condense the startupCPU code. 2009-04-19 02:20:57 -07:00
Gabe Black
f668340f2c X86: Set the local APIC ID to something meaningful. 2009-04-19 02:16:49 -07:00
Gabe Black
79a3a6aecb X86: Don't pretend to be an AMD CPU any more. We're not good enough at it. 2009-04-19 02:06:51 -07:00
Korey Sewell
d8a34a9745 mips-tlb-fix: check for alignment faults.\nMIPS was never updated to use TLBS correcty in SE mode. The error was forwarding translations directly to pageTable. The TLB should check for alignment faults at bare minimum here but in the long run we should be using TLBs in SE mode for MIPS. 2009-04-18 10:42:29 -04:00
Korey Sewell
e501e1af54 mips-syscall: mark with correct flag. \nMIPS was using wrong serialization flag on syscall instructions allowing O3 to handle SE mode syscalls incorrectly and speculate on instructions after a syscall 2009-04-18 10:42:29 -04:00
Korey Sewell
5c1742b822 o3-delay-slot-bpred: fix decode stage handling of uncdtl. branches.\n decode stage was not setting the predicted PC correctly or passing that information back to fetch correctly 2009-04-18 10:42:29 -04:00
Korey Sewell
cc9e834e93 mips-shadowsets: fix calcuations. \n Remove Shadowsets from Int & Arch. Reg Calculations 2009-04-18 10:42:28 -04:00
Steve Reinhardt
8882dc1283 Get rid of the Unallocated thread context state. 
Basically merge it in with Halted.
Also had to get rid of a few other functions that
called ThreadContext::deallocate(), including:
 - InOrderCPU's setThreadRescheduleCondition.
 - ThreadContext::exit().  This function was there to avoid terminating
   simulation when one thread out of a multi-thread workload exits, but we
   need to find a better (non-cpu-centric) way.
 2009-04-15 13:13:47 -07:00
Gabe Black
5c79191603 X86: Fix minor bug in the page table walker from TLB shuffling. 2009-04-13 04:14:15 -07:00
Nathan Binkert
18a30524d6 alpha: get rid of all turbolaser remnants 2009-04-08 22:22:49 -07:00
Nathan Binkert
e0de2c3443 tlb: More fixing of unified TLB 2009-04-08 22:21:27 -07:00
Gabe Black
7b5a96f06b tlb: Don't separate the TLB classes into an instruction TLB and a data TLB 2009-04-08 22:21:27 -07:00
Gabe Black
d080581db1 Merge ARM into the head. ARM will compile but may not actually work. 2009-04-06 10:19:36 -07:00
Stephen Hines
7a7c4c5fca arm: add ARM support to M5 2009-04-05 18:53:15 -07:00
Nathan Binkert
ac64586a99 build: fix compiler warnings in g++ 3.4 2009-03-07 21:34:50 -08:00
Nathan Binkert
cc95b57390 stats: Fix all stats usages to deal with template fixes 2009-03-05 19:09:53 -08:00
Steve Reinhardt
e3d6e8882e Get rid of 'using namespace' declarations in headers. 2009-03-05 17:15:31 -08:00
Steve Reinhardt
307905095c Fix Num_Syscall_Descs check bug in non-x86 ISAs. 
(See cset d35d2b28df38 for x86 fix.)
 2009-02-28 20:14:22 -05:00
Nathan Binkert
4523741c1c quell gcc 4.3 warning 2009-02-27 17:29:58 -08:00
Gabe Black
b69a9ad45a X86: Install the exit system call. 2009-02-27 09:26:41 -08:00
Gabe Black
9265b3d598 X86: Install the 32 bit write system call. 2009-02-27 09:26:32 -08:00
Gabe Black
b36f28472d X86: Implement shrd. 2009-02-27 09:26:26 -08:00
Gabe Black
2fe87e62ba X86: Add a structure to allow mapping between the host and guest fstat formats. 2009-02-27 09:26:17 -08:00
Gabe Black
27b751ec46 X86: Don't treat the REX prefixes as prefixes in 32 bit modes. These are inc/dec instructions. 2009-02-27 09:26:09 -08:00
Gabe Black
aa51c01d69 X86: Set address size to 64 bits when generating addresses internally. 2009-02-27 09:26:01 -08:00
Gabe Black
db3c51d3a0 X86: Add a vsyscall page for 32 bit processes to use. 2009-02-27 09:25:51 -08:00
Gabe Black
c3d7d7ed0e X86: Implement sysenter as a system call interface. 2009-02-27 09:25:43 -08:00