Gabe Black
bb6fea91da
ARM: Implement the SRS instruction.
2010-06-02 12:58:11 -05:00
Gabe Black
dbee6e0c54
ARM: Add a base class for SRS.
2010-06-02 12:58:11 -05:00
Gabe Black
a5ea52bb45
ARM: Allow flattening into any mode.
2010-06-02 12:58:11 -05:00
Gabe Black
fb23297914
ARM: Make a base class for instructions that use only an immediate.
2010-06-02 12:58:10 -05:00
Gabe Black
54ab07e636
ARM: Implement the strex instructions.
2010-06-02 12:58:10 -05:00
Gabe Black
faf6c727f6
ARM: Respect the E bit of the CPSR when doing loads and stores.
2010-06-02 12:58:10 -05:00
Gabe Black
1d5233958a
ARM: Implement the V7 version of alignment checking.
2010-06-02 12:58:10 -05:00
Gabe Black
ec4cd00b11
ARM: Add a base class for the RFE instruction.
2010-06-02 12:58:10 -05:00
Gabe Black
3caa75d53a
ARM: Squash the low order bits of the PC when performing a regular branch.
2010-06-02 12:58:10 -05:00
Gabe Black
eb0823c4f2
ARM: Fix the implementation of BX to work in thumbEE mode.
2010-06-02 12:58:09 -05:00
Gabe Black
9d4a1bf2ba
ARM: Explicitly keep track of the second destination for double loads/stores.
2010-06-02 12:58:09 -05:00
Gabe Black
6c1b10043f
ARM: Rename the RevOp base class to something more generic.
2010-06-02 12:58:08 -05:00
Gabe Black
b1158e4938
ARM: Add a register, immediate, immediate to register base for [su]bfx.
2010-06-02 12:58:08 -05:00
Gabe Black
c643b1c274
ARM: Add a base class to support usada8.
2010-06-02 12:58:07 -05:00
Gabe Black
498f9d925e
ARM: Add a base class for the sel instruction.
2010-06-02 12:58:07 -05:00
Gabe Black
554fb3774e
ARM: Add a base class for extend and add instructions.
2010-06-02 12:58:07 -05:00
Gabe Black
cb2e3b0ace
ARM: Generalize the saturation instruction bases for use in other instructions.
2010-06-02 12:58:07 -05:00
Gabe Black
61b8e33225
ARM: Implement the saturation instructions.
2010-06-02 12:58:06 -05:00
Gabe Black
c96f03a250
ARM: Implement base classes for the saturation instructions.
2010-06-02 12:58:06 -05:00
Gabe Black
be888e67e7
ARM: Implement the unsigned saturating instructions.
2010-06-02 12:58:06 -05:00
Gabe Black
c981a4de2b
ARM: Add base classes suitable for the REV* instructions.
2010-06-02 12:58:05 -05:00
Gabe Black
e157b1f52a
ARM: Implement the swp and swpb instructions.
2010-06-02 12:58:05 -05:00
Gabe Black
f0811eb208
ARM: Define versions of MSR and MRS outside the decoder.
2010-06-02 12:58:05 -05:00
Gabe Black
62e8487d57
ARM: Implement signed saturating add and/or subtract instructions.
2010-06-02 12:58:05 -05:00
Gabe Black
b6e2f5d33f
ARM: Make sure ldm exception return writes back its base in the right mode.
...
This change moves the writeback of load multiple instructions to the beginning
of the macroop. That way, the MicroLdrRetUop that changes the mode will
necessarily happen later, ensuring the writeback happens in the original mode.
The actual value in the base register if it also shows up in the register list
is undefined, so it's fine if it gets clobbered by one of the loads. For
stores where the base register is the lowest numbered in the register list,
the original value should be written back. That means stores can't write back
at the beginning, but the mode changing problem doesn't affect them so they
can continue to write back at the end.
2010-06-02 12:58:04 -05:00
Gabe Black
89060f1fd8
ARM: Rework how unrecognized/unimplemented instructions are handled.
...
Instead of panic immediately when these instructions are executed, an
UndefinedInstruction fault is returned. In FS mode (not currently
implemented), this is the fault that should, to my knowledge, be triggered in
these situations and should be handled using the normal architected
mechanisms. In SE mode, the fault causes a panic when it's invoked that gives
the same information as the instruction did. When/if support for speculative
execution of ARM is supported, this will allow a mispeculated and unrecognized
and/or unimplemented instruction from causing a panic. Only once the
instruction is going to be committed will the fault be invoked, triggering the
panic.
2010-06-02 12:58:04 -05:00
Gabe Black
14d25fbad0
ARM: Don't rely on undefined behavior to get arithmetic right shift.
...
Shifting to the right of a signed value when the MSB is one is technically
undefined behavior, even though in my experience it's done the "right thing"
and sign extended the value. This replaces the arithmetic right shift code in
ARM that uses that coincidence with some code that relies on bit math.
2010-06-02 12:58:04 -05:00
Gabe Black
739f23c64c
ARM: Add base classes for VFP load/store multiple.
2010-06-02 12:58:04 -05:00
Gabe Black
b02c7f1bcd
ARM: Move the macro mem constructor out of the isa desc.
...
This code doesn't use the parser at all, and moving it out reduces the
conceptual complexity of that code.
2010-06-02 12:58:03 -05:00
Gabe Black
e29ec7d2ed
ARM: Move the inst2string function out of the isa_desc.
...
Delete the now empty formats/util.isa.
2010-06-02 12:58:03 -05:00
Gabe Black
3430b34cff
ARM: Add base classes for multiply instructions.
2010-06-02 12:58:03 -05:00
Gabe Black
b6b2f8891a
ARM: Eliminate the old style branch instructions.
2010-06-02 12:58:03 -05:00
Gabe Black
ef3972eaae
ARM: Implement new base classes for branches.
2010-06-02 12:58:02 -05:00
Gabe Black
769f3406fe
ARM: Replace the interworking branch base class with a special operand.
2010-06-02 12:58:02 -05:00
Gabe Black
b6e7029dd5
ARM: Fix PC operand handling.
2010-06-02 12:58:02 -05:00
Gabe Black
4f08b52af2
ARM: Get rid of unnecessary flag calculating functions.
2010-06-02 12:58:02 -05:00
Gabe Black
bf903ec9a1
ARM: Get rid of the unused Jump format.
2010-06-02 12:58:02 -05:00
Gabe Black
36ca0658a4
ARM: Get rid of obsoleted predicated inst formats, etc.
2010-06-02 12:58:02 -05:00
Gabe Black
7939b48265
ARM: Implement disassembly for the new data processing classes.
2010-06-02 12:58:02 -05:00
Gabe Black
beb759912b
ARM: Move the modified_imm function from all ARM instructions to just data processing ones.
2010-06-02 12:58:02 -05:00
Gabe Black
c02f9cdddf
ARM: Add new base classes for data processing instructions.
2010-06-02 12:58:02 -05:00
Gabe Black
51bde086d5
ARM: Reimplement load/store multiple external to the decoder.
...
--HG--
rename : src/arch/arm/isa/formats/macromem.isa => src/arch/arm/isa/insts/macromem.isa
rename : src/arch/arm/isa/formats/macromem.isa => src/arch/arm/isa/templates/macromem.isa
2010-06-02 12:58:02 -05:00
Gabe Black
04300e33d4
ARM: Remove the special naming for the new memory instructions.
...
These are the only memory instructions now.
2010-06-02 12:58:01 -05:00
Gabe Black
deb6e8f805
ARM: Eliminate the old memory formats which are no longer used.
2010-06-02 12:58:01 -05:00
Gabe Black
1905024766
ARM: Eliminate decoding for the very deprecated FPA instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
3b0f3b1ee2
ARM: Add a .w to the disassembly of 32 bit thumb instructions.
...
This isn't technically correct since the .w should only be added if there are
32 and 16 bit encodings, but always having it always is better than never
having it.
2010-06-02 12:58:01 -05:00
Gabe Black
321d3a6e8c
ARM: Implement a new set of base classes for non macro memory instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
bd8812cf99
ARM: Replace the "never" condition with the "unconditional" condition.
2010-06-02 12:58:00 -05:00
Gabe Black
af91d27271
ARM: Add a base class for 32 bit thumb data processing immediate instructions.
2010-06-02 12:58:00 -05:00
Gabe Black
bfe1a194dd
ARM: Add a function to decode 32 bit thumb immediate values.
2010-06-02 12:58:00 -05:00
