Commit graph

261 commits

Author SHA1 Message Date
Kevin Lim
bb41c21d6a Merge ktlim@zizzer.eecs.umich.edu:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/m5

--HG--
extra : convert_revision : ba556bbc93275fcd920a0529383fd480bb7218de
2005-02-25 18:01:19 -05:00
Kevin Lim
5c4714c1a9 Initial light-weight OoO CPU checkin, along with gcc-3.4 fixes.
SConscript:
    Include new files.
arch/alpha/isa_desc:
    Make the eaCompPtr and memAccPtr non-const so that execute() can be called on them.
arch/alpha/isa_traits.hh:
    Add enum for total number of data registers.
arch/isa_parser.py:
base/traceflags.py:
    Include new light-weight OoO CPU model.
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
    Changes to abstract more away from the base dyn inst class.
cpu/beta_cpu/2bit_local_pred.cc:
cpu/beta_cpu/2bit_local_pred.hh:
cpu/beta_cpu/tournament_pred.cc:
cpu/beta_cpu/tournament_pred.hh:
    Remove redundant SatCounter class.
cpu/beta_cpu/alpha_dyn_inst.cc:
cpu/beta_cpu/alpha_full_cpu.cc:
cpu/beta_cpu/alpha_full_cpu.hh:
cpu/beta_cpu/bpred_unit.cc:
cpu/beta_cpu/inst_queue.cc:
cpu/beta_cpu/mem_dep_unit.cc:
cpu/beta_cpu/ras.cc:
cpu/beta_cpu/rename_map.cc:
cpu/beta_cpu/rename_map.hh:
cpu/beta_cpu/rob.cc:
    Fix for gcc-3.4
cpu/beta_cpu/alpha_dyn_inst.hh:
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
    Fixes for gcc-3.4.
    Include more variables and functions that are specific to AlphaDynInst which were once in BaseDynInst.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
    Make params match the current params inherited from BaseCPU.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
    Fixes for gcc-3.4
cpu/beta_cpu/full_cpu.cc:
    Use new params pointer in BaseCPU.
    Fix for gcc-3.4.
cpu/beta_cpu/full_cpu.hh:
    Use new params class from BaseCPU.
cpu/beta_cpu/iew_impl.hh:
    Remove unused function.
cpu/simple_cpu/simple_cpu.cc:
    Remove unused global variable.
cpu/static_inst.hh:
    Include OoODynInst for new lightweight OoO CPU

--HG--
extra : convert_revision : 34d9f2e64ca0313377391e0d059bf09c040286fa
2005-02-25 18:00:49 -05:00
Steve Reinhardt
368882a847 Fix timing modeling of faults: functionally the very next instruction after
a faulting instruction is the fault handler, which appears as an independent
instruction to the timing model.  New code will stall fetch and not fetch the
fault handler as long as there's a faulting instruction in the pipeline (i.e.,
the faulting inst has to commit first).

Also fix Ali's bad-address assertion that doesn't apply to full system.

Added some more debugging support in the process.  Hopefully we'll move to the new
cpu model soon and we won't need it anymore.

arch/alpha/alpha_memory.cc:
    Reorganize lookup() so we can trace the result of the lookup as well.
arch/alpha/isa_traits.hh:
    Add NoopMachInst (so we can insert them in the pipeline on ifetch faults).
base/traceflags.py:
    Replace "Dispatch" flag with "Pipeline" (since I added similar
    DPRINTFs in other pipe stages).
cpu/exetrace.cc:
    Change default for printing mis-speculated instructions to true (since
    that's often what we want, and right now you can't change it from the
    command line...).

--HG--
extra : convert_revision : a29a98a373076d62bbbb1d6f40ba51ecae436dbc
2005-02-25 12:41:08 -05:00
Kevin Lim
e8a564b0fd Merge ktlim@zizzer.eecs.umich.edu:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/m5

--HG--
extra : convert_revision : 8a558785c64b7c33e64523d3d887ea6e760c3d2b
2005-02-22 16:03:30 -05:00
Ali Saidi
57482491c5 build mysql version if libraries exist
add dprintf on alignment faults
fix RR benchmark rcS script name
Add Dual test without rcS script
Update Monet to be closer to the real thing
Fix p4/monet configs
Add a way to read the DRIR register with at 32bit access for validation

SConscript:
build/SConstruct:
    always use mysql if the libraries are installed
arch/alpha/alpha_memory.cc:
    Add a DPRINTF to print alignment faults when they happen
dev/tsunami_cchip.cc:
    Add a way to read the DRIR for validation.

--HG--
extra : convert_revision : 8c112c958f36b785390c46e70a889a79c6bea015
2005-02-13 23:03:04 -05:00
Kevin Lim
1e7a744c09 Hand merge
--HG--
extra : convert_revision : 86c7399b79c17558041a73056745227f70fe8b3b
2005-02-04 18:25:49 -05:00
Steve Reinhardt
0aaf8ec6b8 Add support for CPU models to execute the effective
address calculation and memory access portions separately.
Not currently used by any CPU models, but Kevin says he needs this.

Also clean up handling of execution tracing for memory accesses
(move it all into isa_desc and out of CPU models).

Got rid of some ancient unused code too.

arch/alpha/isa_desc:
    Add execute() methods to EAComp and MemAcc portions of memory
    access instructions, to allow CPU models to execute the effective
    address calculation and memory access portions separately.

    Requires the execution context to remember the effective address
    across the two invocations.  Added setEA() and getEA() methods to
    execution context to support this.  A model that does not use the
    split execution model can panic if these methods are called.

    Also added hook to call traceData->setAddr() after EA computation
    on any load or store operation.
arch/isa_parser.py:
    Call traceData->setData() on memory writes (stores).
cpu/simple_cpu/simple_cpu.cc:
    Get rid of unused code.
cpu/simple_cpu/simple_cpu.hh:
    Add (non-functional) setEA() and getEA() methods for new
    split memory access execution support.

--HG--
extra : convert_revision : bc2d2c758c4ca753812b9fa81f21038e55929ff0
2005-02-03 20:47:11 -05:00
Kevin Lim
e6b99b0768 Merge zizzer.eecs.umich.edu:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/m5-patched/m5-new

--HG--
extra : convert_revision : e802c800a478c297d3aa780a9ea3c6701453d91d
2005-01-21 18:31:30 -05:00
Nathan Binkert
6cbce7631a Add a couple statistics contexts.
arch/alpha/pseudo_inst.cc:
    rename the context for consistency.
sim/pyconfig/m5config.py:
    Add a ParamContext class so that param contexts work with
    the new config stuff.

--HG--
extra : convert_revision : 3a6b583a25c86237baca7a2b4eccc9d12f86a384
2005-01-21 04:34:01 -05:00
Kevin Lim
f58d85128d Fixes so m5 compiles on gcc 3.4, which has much stricter syntax. Most changes come from templated code,
which is evaluated slightly differently than in previous versions of gcc.

arch/alpha/alpha_linux_process.cc:
    Alphabetize includes.
arch/alpha/vptr.hh:
    Change the constants that are being used for alpha pagebytes to come from the ISA.
base/random.hh:
cpu/static_inst.cc:
sim/param.cc:
    Fix up template syntax.
base/range.hh:
    Include iostream for << operator.
base/res_list.hh:
base/statistics.hh:
cpu/simple_cpu/simple_cpu.hh:
cpu/static_inst.hh:
sim/eventq.hh:
sim/param.hh:
    Fixup for templated code to resolve different scope lookup in gcc 3.4.  This defers the lookup of the
    function/variable until actual instantiation time by making it dependent on the templated class/function.
base/trace.cc:
    Fix call to new.
base/trace.hh:
    Fix up #define to have full path.
cpu/base_cpu.cc:
    Fix up call to new.
dev/etherlink.hh:
dev/ns_gige.hh:
dev/sinic.hh:
    Fixup for friend class/function declaration.  g++ 3.4 no longer allows typedefs to be declared as
    a friend class.
dev/pcidev.hh:
    Fix up re-definition of access level to params.
kern/linux/linux_syscalls.hh:
kern/tru64/tru64_syscalls.hh:
    Fix up header.  Fix up template syntax.
sim/serialize.cc:
    Include errno.h.
sim/startup.cc:
    Change startupq.  queue was getting destructed before all things had called ~StartupCallback(), which lead
    to a segfault.  This puts startupq in global space, and we allocate it ourselves.  Other code may be similar
    to this and may need changing in the future.
sim/syscall_emul.hh:
    Include cpu/exec_context.hh and sim/process.hh, as forward declarations are no longer sufficient.
sim/universe.cc:
    Include errno.h

--HG--
extra : convert_revision : e49d08ee89eb06a28351f02bafc028ca6652d5af
2005-01-14 18:34:56 -05:00
Kevin Lim
42f3b4ffb3 Merge changes.
base/traceflags.py:
    Merge extra new CPU flags
cpu/static_inst.hh:
    Include all the execute functions in static_inst_impl.hh

--HG--
extra : convert_revision : 78eb753bf709d37400e7c2418bb35d842d7c3f63
2005-01-11 19:00:16 -05:00
Nathan Binkert
425dda00df Macros are nasty, so let's get rid of them. Convert all
all macros in ev5.hh to inline functions or constant typed
variables and make them follow our style while we're at it.

All of the stuff in this file actually belongs in the ISA
traits code, but this is a first step at getting things done
in the right manner.

arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/ev5.cc:
arch/alpha/isa_desc:
dev/ns_gige.cc:
kern/tru64/tru64_events.cc:
    deal with changes in ev5.hh
arch/alpha/ev5.hh:
    Macros are nasty, so let's get rid of them.  Convert all
    all macros to inline functions or constant typed variables.
    Make them follow our style while we're at it.

    All of the stuff in this file actually belongs in the ISA
    traits code, but this is a first step at getting things done
    in the right manner.
arch/alpha/isa_traits.hh:
    move some of the ev5 specific code into the isa
arch/alpha/vtophys.cc:
base/remote_gdb.cc:
    deal with isa addition
cpu/exec_context.hh:
    be less isa specific and use the isa traits to figure out
    what we can.
dev/alpha_console.cc:
dev/pciconfigall.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart.cc:
    deal with changes in ev5.hh
    I don't believe this masking is actually necessary.  We should
    look at removing it later.
dev/ide_ctrl.cc:
    sort #includes
    deal with changes in ev5.hh

--HG--
extra : convert_revision : c8a3adf0a4b1d198aefe38fc38b295abf289b08a
2004-11-13 14:01:38 -05:00
Nathan Binkert
bde7f4d121 defining SYSTEM_EV5 isn't all that necessary
--HG--
extra : convert_revision : 2ed4866db9483820d550bad00fdbc8dd027f95ba
2004-11-13 11:33:43 -05:00
Nathan Binkert
c4e5ef64b3 defining SYSTEM_EV5 isn't all that necessary
--HG--
extra : convert_revision : 7d39dd9f814434cb95ec769204d7f2426b0290fd
2004-11-13 11:32:17 -05:00
Nathan Binkert
338513c681 Use the inPalMode function instead of the PC_PAL macro
--HG--
extra : convert_revision : 58e0a19ba98777e5d2e2572ed02dee1914378ff7
2004-11-10 18:44:37 -05:00
Nathan Binkert
4328480b56 Don't use the global check_interrupts variable. Add a per-cpu
checkInterrupts variable and use that to determine whether an interrupt
can occur on a given cycle.

arch/alpha/ev5.cc:
    XC -> CPU (and xc -> CPU) since we're really talking about a CPU here
    Don't use the global check_interrupts variable.  Add a per-cpu
    checkInterrupts variable and use that to determine whether an interrupt
    can occur on a given cycle.

--HG--
extra : convert_revision : be4c0247e5834005c60a45796a222cffd327b64e
2004-11-10 18:37:19 -05:00
Taeho Kgil
129b885abd Add Inorder CPU model
SConscript:
arch/isa_parser.py:
cpu/static_inst.hh:
    Add inorderCPU

--HG--
extra : convert_revision : 141372808fac5f6d125f9051ee0be982d21683aa
2004-11-03 17:56:26 -05:00
Nathan Binkert
d55eb90fc7 Don't use magic numbers.
arch/alpha/isa_traits.hh:
    Move defines to non full system code section so they can
    be used elsewhere
cpu/simple_cpu/simple_cpu.cc:
    Don't use magic numbers
cpu/simple_cpu/simple_cpu.hh:
    simple format nit

--HG--
extra : convert_revision : b8d492218340d41ab9420c6ad1e81a197db1c132
2004-10-25 16:23:22 -04:00
Nathan Binkert
224acc2abc get rid of pmap.h and make things variables and inline
functions instead of preprocessor macros.

arch/alpha/vtophys.cc:
    use new constants, functions and structs to clean up the
    vtophys code.
arch/alpha/vtophys.hh:
    Clean up a little bit and make the protypes match new changes.
base/remote_gdb.cc:
dev/ide_disk.cc:
kern/tru64/tru64_events.cc:
    use new constants from isa_traits.hh instead of ones from
    old pmap.h

--HG--
extra : convert_revision : 5dce34e3b0c84ba72cefca34e5999b99898edcef
2004-10-23 10:41:35 -04:00
Nathan Binkert
3ab83348d2 in the arch/alpha directory we should use arch/alpha, not
targetarch.

arch/alpha/alpha_memory.cc:
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
arch/alpha/faults.cc:
arch/alpha/isa_traits.hh:
arch/alpha/osfpal.cc:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
    in the arch/alpha directory we should use arch/alpha, not
    targetarch.  sort includes while we're here.

--HG--
extra : convert_revision : 99a71540e2997173db5c1072cef910a26acc75b2
2004-10-23 00:39:15 -04:00
Steve Reinhardt
0da150b294 Make targetarch directory in build tree and copy arch/alpha files to it
instead of using symlink.  The symlink broke scons's built-in include
dependency tacking.

Interestingly once it was fixed scons discovered two circular dependency
problems which are also fixed now.

SConscript:
    Make targetarch directory in build tree and copy arch/alpha files to it
    instead of using symlink.  The symlink broke scons's built-in include
    dependency tacking.
arch/alpha/ev5.hh:
    Get rid of circular #include dependence.
kern/kernel_stats.cc:
    Add needed header file.
kern/linux/linux_syscalls.hh:
kern/tru64/tru64_syscalls.hh:
    Replace targetarch/syscalls.hh with single template class declaration.

--HG--
extra : convert_revision : b8551623c1d441c6eb8d0651387e97e373128814
2004-10-22 22:49:12 -04:00
Ali Saidi
3ef950abba Fixes for bigendian platforms
arch/alpha/vtophys.cc:
    PGOFSET -> ALPHA_PGOFSET to avoid include file problems
base/callback.hh:
    Added  a class to create a callback from a function
base/intmath.hh:
    make FloorLog2 inlined
dev/pcidev.cc:
    more work in getting pciconfig space happy with different endiannesses
dev/uart.cc:
    used an incorrect size for write uint64_t instead of uint8_t
sim/system.cc:
    when writing things into system data structures we need to pay
    attention to endianness

--HG--
extra : convert_revision : 52f441b5789c45db30ef2f6fd4975cbc7323a381
2004-10-16 19:10:51 -05:00
Kevin Lim
e3fb9afa79 Update to make multiple instruction issue and different latencies work.
Also change to ref counted DynInst.

SConscript:
    Add branch predictor, BTB, load store queue, and storesets.
arch/isa_parser.py:
    Specify the template parameter for AlphaDynInst
base/traceflags.py:
    Add load store queue, store set, and mem dependence unit to the
    list of trace flags.
cpu/base_dyn_inst.cc:
    Change formating, add in debug statement.
cpu/base_dyn_inst.hh:
    Change DynInst to be RefCounted, add flag to clear whether or not this
    instruction can commit.  This is likely to be removed in the future.
cpu/beta_cpu/alpha_dyn_inst.cc:
    AlphaDynInst has been changed to be templated, so now this CC file
    is just used to force instantiations of AlphaDynInst.
cpu/beta_cpu/alpha_dyn_inst.hh:
    Changed AlphaDynInst to be templated on Impl.  Removed some unnecessary
    functions.
cpu/beta_cpu/alpha_full_cpu.cc:
    AlphaFullCPU has been changed to be templated, so this CC file is now
    just used to force instantation of AlphaFullCPU.
cpu/beta_cpu/alpha_full_cpu.hh:
    Change AlphaFullCPU to be templated on Impl.
cpu/beta_cpu/alpha_impl.hh:
    Update it to reflect AlphaDynInst and AlphaFullCPU being templated
    on Impl.  Also removed time buffers from here, as they are really
    a part of the CPU and are thus in the CPU policy now.
cpu/beta_cpu/alpha_params.hh:
    Make AlphaSimpleParams inherit from the BaseFullCPU so that it doesn't
    need to specifically declare any parameters that are already in the
    BaseFullCPU.
cpu/beta_cpu/comm.hh:
    Changed the structure of the time buffer communication structs.  Now
    they include the size of the packet of instructions it is sending.
    Added some parameters to the backwards communication struct, mainly
    for squashing.
cpu/beta_cpu/commit.hh:
    Update typenames to reflect change in location of time buffer structs.
    Update DynInst to DynInstPtr (it is refcounted now).
cpu/beta_cpu/commit_impl.hh:
    Formatting changes mainly.  Also sends back proper information
    on branch mispredicts so that the bpred unit can update itself.
    Updated behavior for non-speculative instructions (stores, any
    other non-spec instructions): once they reach the head of the ROB,
    the ROB signals back to the IQ that it can go ahead and issue the
    non-speculative instruction.  The instruction itself is updated so that
    commit won't try to commit it again until it is done executing.
cpu/beta_cpu/cpu_policy.hh:
    Added branch prediction unit, mem dependence prediction unit, load
    store queue.  Moved time buffer structs from AlphaSimpleImpl to here.
cpu/beta_cpu/decode.hh:
    Changed typedefs to reflect change in location of time buffer structs
    and also the change from DynInst to ref counted DynInstPtr.
cpu/beta_cpu/decode_impl.hh:
    Continues to buffer instructions even while unblocking now.  Changed
    how it loops through groups of instructions so it can properly block
    during the middle of a group of instructions.
cpu/beta_cpu/fetch.hh:
    Changed typedefs to reflect change in location of time buffer structs
    and the change to ref counted DynInsts.  Also added in branch
    brediction unit.
cpu/beta_cpu/fetch_impl.hh:
    Add in branch prediction.  Changed how fetch checks inputs and its
    current state to make for easier logic.
cpu/beta_cpu/free_list.cc:
    Changed int regs and float regs to logically use one flat namespace.
    Future change will be moving them to a single scoreboard to conserve
    space.
cpu/beta_cpu/free_list.hh:
    Mostly debugging statements.  Might be removed for performance in future.
cpu/beta_cpu/full_cpu.cc:
    Added in some debugging statements.  Updated BaseFullCPU to take
    a params object.
cpu/beta_cpu/full_cpu.hh:
    Added params class within BaseCPU that other param classes will be
    able to inherit from.  Updated typedefs to reflect change in location
    of time buffer structs and ref counted DynInst.
cpu/beta_cpu/iew.hh:
    Updated typedefs to reflect change in location of time buffer structs
    and use of ref counted DynInsts.
cpu/beta_cpu/iew_impl.hh:
    Added in load store queue, updated iew to be able to execute non-
    speculative instructions, instead of having them execute in commit.
cpu/beta_cpu/inst_queue.hh:
    Updated change to ref counted DynInsts.  Changed inst queue to hold
    non-speculative instructions as well, which are issued only when
    commit signals backwards that a nonspeculative instruction is at
    the head of the ROB.
cpu/beta_cpu/inst_queue_impl.hh:
    Updated to allow for non-speculative instructions to be in the inst
    queue.  Also added some debug functions.
cpu/beta_cpu/regfile.hh:
    Added debugging statements, changed formatting.
cpu/beta_cpu/rename.hh:
    Updated typedefs, added some functions to clean up code.
cpu/beta_cpu/rename_impl.hh:
    Moved some code into functions to make it easier to read.
cpu/beta_cpu/rename_map.cc:
    Changed int and float reg behavior to use a single flat namespace.  In
    the future, the rename maps can be combined to a single rename map to
    save space.
cpu/beta_cpu/rename_map.hh:
    Added destructor.
cpu/beta_cpu/rob.hh:
    Updated it with change from DynInst to ref counted DynInst.
cpu/beta_cpu/rob_impl.hh:
    Formatting, updated to use ref counted DynInst.
cpu/static_inst.hh:
    Updated forward declaration for AlphaDynInst now that it is templated.

--HG--
extra : convert_revision : 1045f240ee9b6a4bd368e1806aca029ebbdc6dd3
2004-09-23 14:06:03 -04:00
Ali Saidi
ac422ac949 Merge zizzer:/bk/m5 into zeep.eecs.umich.edu:/z/saidi/work/m5-smp
--HG--
extra : convert_revision : 19dc01e1c0d2c0ba6b4d804b902429fb0a6a5552
2004-09-22 18:39:37 -04:00
Ali Saidi
eb7d329076 fix unaligned memory offset and some small fixes to interrupt binning
code

arch/alpha/alpha_memory.cc:
    Fixed unaligned trap faults
arch/alpha/ev5.cc:
    little more verbose faulting information
kern/linux/linux_system.cc:
    more descriptive errors, and the correct offsets from symbols
sim/system.cc:
    load local pal symbols

--HG--
extra : convert_revision : 0c81badf77321d5e1a060dcae2d42204e5a1fc84
2004-09-22 18:25:06 -04:00
Erik Hallnor
15d08a3422 Update copies to work around alignment faults.
arch/alpha/isa_desc:
    whitespace fix.
cpu/simple_cpu/simple_cpu.cc:
    Add support to make sure we don't get alignment faults in copies. Warn if we go over an 8k page boundary.

--HG--
extra : convert_revision : 98b38da86a66215d80ea9eb6e6f1f68ee573cb57
2004-09-20 22:00:35 -04:00
Ali Saidi
af620e1187 added system option to bin interrupt code seperately.
arch/alpha/ev5.cc:
    set the mode explictly rather than having a bool user/notuser
cpu/simple_cpu/simple_cpu.hh:
    there is no class Kernel
kern/kernel_stats.cc:
    use cpu_mode_num
kern/kernel_stats.hh:
    add interrupt mode and use cpu_mode_num rather than constant
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
kern/system_events.cc:
kern/system_events.hh:
    add events to change the mode to/from interrupt
sim/system.cc:
sim/system.hh:
    add a pal symbol table

--HG--
extra : convert_revision : 9d30e826b72122062a5ea12d094f94760e75c66a
2004-09-03 14:12:59 -04:00
Kevin Lim
04745696b6 Check in of new CPU. This checkin works under non-Fullsystem mode, with no caches.
SConscript:
    Added new CPU files to build.
arch/alpha/isa_desc:
    Changed rduniq and wruniq to be nonspeculative because the uniq register is not renamed.
arch/isa_parser.py:
    Added new CPU exec method.
base/statistics.hh:
    Minor change for namespace conflict.  Probably can change back one the new CPU files are cleaned up.
base/traceflags.py:
    Added new CPU trace flags.
cpu/static_inst.hh:
    Changed static inst to use a file that defines the execute functions.

--HG--
extra : convert_revision : bd4ce34361308280168324817fc1258dd253e519
2004-08-20 14:54:07 -04:00
Nathan Binkert
9023f5c96d - Clean up and factor out all of the binning code into a
single place so it's easier to work with.
-  Add support for binning kernel/user/idle time separately from
lisa's binning stuff, but make the two compatible.
-  KernelStats used to directly implement the pImpl idiom, but
it makes more sense to just remove the level of indirection and
make the exec context have a pointer to the stats.
-  Factor common code out of LinuxSystem and Tru64System and put
it into the System base class.  While doing that, make all
constructors take a pointer to a parameter struct instead of
naming the parameters individually to make it much easier to add
parameters to these classes.

SConscript:
    Move the function tracking and binning stuff around.
arch/alpha/ev5.cc:
    kernelStats is now a pointer
arch/alpha/pseudo_inst.cc:
    kernelStats is now a pointer
    the parameters to the system have been moved into their own
    struct
base/trace.hh:
    provide a little functor class for wrapping a string that
    can allow you to define name() in any scope very simply
    for use with DPRINTF
cpu/base_cpu.cc:
    New order of arguments for consistency.
cpu/exec_context.cc:
    kernelStats no longer has the level of indirection in it,
    execContext has the indirection now.  so, kernelStats is a pointer.
    We also need a pointer to the kernelBinning stuff from the system
    and we need to figure out if we want to do binning or not.
    Move a whole bunch of code into kern_binning.cc so it's all
    in the same place.
cpu/exec_context.hh:
    We want pointers to the kernel binning/stats stuff and we'll
    have the exec_context and system have the level of indirection
    instead of having the extra layer in the kernel stats class.
cpu/simple_cpu/simple_cpu.cc:
    call through the exec context to do the special binning
    stuff.
kern/kernel_stats.cc:
kern/kernel_stats.hh:
    Re-organize the stats stuff and remove the level of indirection
    (that was there to simplify building) and move the binning stuff
    into its own class/file.
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
sim/system.cc:
sim/system.hh:
    move lots of common system code into the base system class so
    that it can be shared between linux, tru64, and whatever else
    we decide to support in the future.

    Make the constructor take a pointer to a parameter struct so that
    it is easier to pass parameters to the parent.
kern/system_events.cc:
    move the majority of the binning code into the Kernel::Binning class
    in the kern_binning file
kern/system_events.hh:
    FnEvents only need to know the bin
    create the Idle start event to find the PCBB of the idle
    process when it starts.
kern/tru64/tru64_events.cc:
    memCtrl -> memctrl
sim/process.cc:
sim/process.hh:
    re-order args for consistency

--HG--
extra : convert_revision : 86cb39738c41fcd680f2aad125c9dde000227b2b
2004-08-20 11:35:31 -04:00
Ali Saidi
8f19fd2cbe merged full_cpu.ini, system.ini and devtime.c
util/ccdrv/devtime.c:
    coding style

--HG--
extra : convert_revision : 972941e100ba13a2ece0986454c4a3485841d9cb
2004-08-02 17:16:54 -04:00
Ali Saidi
6c954de33e added m5 debug and m5 switch cpu instruction (doesn't work yet) and
a p4 memory/cpu config

arch/alpha/alpha_memory.cc:
    Added code to fault on an unaligned access
arch/alpha/isa_desc:
arch/alpha/pseudo_inst.cc:
arch/alpha/pseudo_inst.hh:
    Added m5debug break and m5switchcpu (the latter doesn't work)

--HG--
extra : convert_revision : 409e73adb151600a4fea49f35bf6f503f66fa916
2004-08-02 17:10:02 -04:00
Ali Saidi
b376c6f420 Added debug printk support
arch/alpha/ev5.hh:
    Added max address PAL code can be at
arch/alpha/vtophys.cc:
    Check max address pal can be at so we don't do the wrong conversion
    if gdb asks for an unaligned access.

--HG--
extra : convert_revision : b44f6a8fcd8582337a7d4033f28137c7e718a6a8
2004-07-30 17:13:24 -04:00
Ali Saidi
02dfbe92fc fixed a bad merge from linux<->tru64
--HG--
extra : convert_revision : d7a5acd89a2bdc013c8a2bd022cc7048a3920f01
2004-07-08 00:28:02 -04:00
Nathan Binkert
0e575e9f26 Need to #include <unistd.h> to build with pread
--HG--
extra : convert_revision : 1e5b3e5f1eaba3853d7d3da5546387c16932ab6a
2004-07-02 12:30:06 -04:00
Nathan Binkert
6083c8280b implement the readfile pseudo instruction that will read
a realworld file.

arch/alpha/isa_desc:
arch/alpha/pseudo_inst.hh:
    implement the readfile pseudo instruction that will read a
    chunk of a realworld file.
arch/alpha/pseudo_inst.cc:
    implement the readfile pseudo instruction that will read a
    chunk of a realworld file.  The filename is a per system
    parameter and comes from the system itself.
kern/linux/linux_system.cc:
sim/system.hh:
    Create a per-system readfile parameter for use by the readfile
    pseudo instruction.  That way each system can get its own file.

--HG--
extra : convert_revision : 941b3a3e20702a6252b219ca66a6d90da2944c50
2004-07-01 18:03:05 -04:00
Nathan Binkert
671cff5937 rename CopyData to CopyOut and implement CopyIn to copy data
from the simulator into the simulatee

kern/tru64/dump_mbuf.cc:
    rename CopyData -> CopyOut

--HG--
extra : convert_revision : e3ef27a5762dfc495dcb84a372470464c27557d2
2004-07-01 18:00:18 -04:00
Nathan Binkert
ee765958b4 add asn when tracing tlb stuff
--HG--
extra : convert_revision : abc774179b3d4c979efd98e32d1d071b142e7b48
2004-06-30 14:51:40 -04:00
Nathan Binkert
838273a196 fix up the recordEvent stuff to support ignoring events
arch/alpha/ev5.cc:
cpu/simple_cpu/simple_cpu.cc:
    update for new event interface
base/stats/events.cc:
    implement the ignore event function which matches sim objects from which
    to ignore events.

    Make insert event like insert data and make it able to insert many
    events in a single transaction with the database.
base/stats/events.hh:
    Make it possible to ignore events
sim/sim_object.cc:
    make recordEvent a member function of SimObject to implement
    the ignore function easily
sim/sim_object.hh:
    implement the ignore event stuff in the sim object.  This is a
    bit of a hack, but an easy place to put it.

--HG--
extra : convert_revision : ba3f25a14ad03662c53fb35514860d69be8cd4f0
2004-06-28 16:49:35 -04:00
Ali Saidi
f37eb6f5c7 ifdefed ev5 vs. ev6 differences so Tlaser can work in the linux tree
arch/alpha/alpha_memory.cc:
arch/alpha/ev5.hh:
    Ifdefed TLASER code
arch/alpha/vtophys.cc:
    added back some code andrew removed and couldn't remember why.

--HG--
extra : convert_revision : f00d255f7a8a7bdb6e74f061dd014188e3b39e73
2004-06-22 17:20:19 -04:00
Ali Saidi
4deb819894 pull from head before pushing linux tree
--HG--
extra : convert_revision : 345f91c5c16c69db22035dc716e82fd77041380f
2004-06-22 13:48:49 -04:00
Steve Reinhardt
d53c6c168a Get software prefetching to work in full-system mode.
Mostly a matter of keeping prefetches to invalid addrs
from messing up VM IPRs.  Also discovered that wh64s were
not being treated as prefetches, when they really should be
(for the most part, anyway).

arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
    - Get rid of intrlock flag for locking VM fault regs (a la EV5);
    instead, just don't update regs on VPTE loads (a la EV6).
    - Add NO_FAULT MemReq flag to indicate references that should not
    cause page faults (i.e., prefetches).
arch/alpha/ev5.cc:
    - Get rid of intrlock flag for locking VM fault regs (a la EV5);
    instead, just don't update regs on VPTE loads (a la EV6).
    - Add Fault trace flag.
arch/alpha/isa_desc:
    - Add NO_FAULT MemReq flag to indicate references that should not
    cause page faults (i.e., prefetches).
    - Mark wh64 as a "data prefetch" instruction so it gets controlled
    properly by the FullCPU data prefetch control switch.
    - Align wh64 EA in decoder so issue stage doesn't need to worry about it.
arch/alpha/isa_traits.hh:
    - Get rid of intrlock flag for locking VM fault regs (a la EV5);
    instead, just don't update regs on VPTE loads (a la EV6).
base/traceflags.py:
    - Add Fault trace flag.
cpu/simple_cpu/simple_cpu.hh:
    - Pass MemReq flags to writeHint() operation.
cpu/static_inst.hh:
    Update comment re: prefetches.

--HG--
extra : convert_revision : 62e466b0f4c0ff9961796270fa2e371ec24bcbb6
2004-06-15 10:48:08 -07:00
Ali Saidi
02f69b94c5 Fixes for detailed boot, made cttz and ctlz instructions more compact,
and started cleaning up config files.

arch/alpha/isa_desc:
    Made implementation of cttz and ctlz more compact
base/remote_gdb.cc:
    Added comment about PALcode debugger accesses
dev/baddev.cc:
dev/baddev.hh:
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/tsunami_uart.cc:
dev/tsunami_uart.hh:
    Cleaned up includes and changed device from FunctionalMemory to
    PioDevice for detailed boot
dev/ns_gige.cc:
    The ethernet dev uses two BARs, and the first bars size was being set
    incorrectly.
dev/tsunamireg.h:
    I don't know why we were using the superpage as the PCI memory addr.
    Changed and works correctly with detailed boot.

--HG--
extra : convert_revision : b535e76612cb90b544305dc1aa8c5e0e774564bd
2004-06-10 13:30:58 -04:00
Ali Saidi
2f316082e4 Updated Copyright with information in bitkeeper changelogs
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_linux_process.hh:
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/alpha_tru64_process.cc:
arch/alpha/alpha_tru64_process.hh:
arch/alpha/aout_machdep.h:
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
arch/alpha/faults.cc:
arch/alpha/faults.hh:
arch/alpha/isa_traits.hh:
arch/alpha/osfpal.cc:
arch/alpha/osfpal.hh:
arch/alpha/pseudo_inst.cc:
arch/alpha/pseudo_inst.hh:
arch/alpha/vptr.hh:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
base/bitfield.hh:
base/callback.hh:
base/circlebuf.cc:
base/circlebuf.hh:
base/compression/lzss_compression.cc:
base/compression/lzss_compression.hh:
base/compression/null_compression.hh:
base/cprintf.cc:
base/cprintf.hh:
base/cprintf_formats.hh:
base/date.cc:
base/dbl_list.hh:
base/endian.hh:
base/fast_alloc.cc:
base/fast_alloc.hh:
base/fifo_buffer.cc:
base/fifo_buffer.hh:
base/hashmap.hh:
base/hostinfo.cc:
base/hostinfo.hh:
base/hybrid_pred.cc:
base/hybrid_pred.hh:
base/inet.cc:
base/inet.hh:
base/inifile.cc:
base/inifile.hh:
base/intmath.cc:
base/intmath.hh:
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/object_file.cc:
base/loader/object_file.hh:
base/loader/symtab.cc:
base/loader/symtab.hh:
base/misc.cc:
base/misc.hh:
base/mod_num.hh:
base/mysql.cc:
base/mysql.hh:
base/pollevent.cc:
base/pollevent.hh:
base/predictor.hh:
base/random.cc:
base/random.hh:
base/range.cc:
base/range.hh:
base/refcnt.hh:
base/remote_gdb.cc:
base/remote_gdb.hh:
base/res_list.hh:
base/sat_counter.cc:
base/sat_counter.hh:
base/sched_list.hh:
base/socket.cc:
base/socket.hh:
base/statistics.cc:
base/statistics.hh:
base/stats/events.cc:
base/stats/events.hh:
base/stats/flags.hh:
base/stats/mysql.cc:
base/stats/mysql.hh:
base/stats/mysql_run.hh:
base/stats/output.hh:
base/stats/statdb.cc:
base/stats/statdb.hh:
base/stats/text.cc:
base/stats/text.hh:
base/stats/types.hh:
base/stats/visit.cc:
base/stats/visit.hh:
base/str.cc:
base/str.hh:
base/time.cc:
base/time.hh:
base/trace.cc:
base/trace.hh:
base/userinfo.cc:
base/userinfo.hh:
cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/exetrace.cc:
cpu/exetrace.hh:
cpu/full_cpu/op_class.hh:
cpu/full_cpu/smt.hh:
cpu/inst_seq.hh:
cpu/intr_control.cc:
cpu/intr_control.hh:
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
cpu/pc_event.cc:
cpu/pc_event.hh:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/static_inst.cc:
cpu/static_inst.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/baddev.cc:
dev/baddev.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.cc:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.cc:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ide_disk.cc:
dev/ide_disk.hh:
dev/io_device.cc:
dev/io_device.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/ns_gige_reg.h:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/pcidev.cc:
dev/pcidev.hh:
dev/pcireg.h:
dev/platform.cc:
dev/platform.hh:
dev/simple_disk.cc:
dev/simple_disk.hh:
dev/tsunami.cc:
dev/tsunami.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/tsunami_uart.hh:
dev/tsunamireg.h:
docs/stl.hh:
kern/linux/linux.hh:
kern/linux/linux_syscalls.cc:
kern/linux/linux_syscalls.hh:
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
kern/system_events.cc:
kern/system_events.hh:
kern/tru64/dump_mbuf.cc:
kern/tru64/dump_mbuf.hh:
kern/tru64/mbuf.hh:
kern/tru64/printf.cc:
kern/tru64/printf.hh:
kern/tru64/tru64.hh:
kern/tru64/tru64_events.cc:
kern/tru64/tru64_events.hh:
kern/tru64/tru64_syscalls.cc:
kern/tru64/tru64_syscalls.hh:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
sim/async.hh:
sim/builder.cc:
sim/builder.hh:
sim/debug.cc:
sim/debug.hh:
sim/eventq.cc:
sim/eventq.hh:
sim/host.hh:
sim/main.cc:
sim/param.cc:
sim/param.hh:
sim/process.cc:
sim/process.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_events.cc:
sim/sim_events.hh:
sim/sim_exit.hh:
sim/sim_object.cc:
sim/sim_object.hh:
sim/stat_control.cc:
sim/stat_control.hh:
sim/stats.hh:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
sim/system.cc:
sim/system.hh:
sim/universe.cc:
test/bitvectest.cc:
test/circletest.cc:
test/cprintftest.cc:
test/initest.cc:
test/lru_test.cc:
test/nmtest.cc:
test/offtest.cc:
test/paramtest.cc:
test/rangetest.cc:
test/sized_test.cc:
test/stattest.cc:
test/strnumtest.cc:
test/symtest.cc:
test/tokentest.cc:
test/tracetest.cc:
util/m5/m5.c:
util/m5/m5op.h:
util/tap/tap.cc:
    Updated Copyright
dev/console.cc:
dev/console.hh:
    This code isn't ours, and shouldn't have our copyright

--HG--
extra : convert_revision : 598f2e5eab5d5d3de2c1e862b389086e3212f7c4
2004-06-08 13:37:27 -04:00
Ali Saidi
e44fc6db33 Added ctlz and cttz instructions to isa_desc for use in the PAL code.
--HG--
extra : convert_revision : 74dec35113b795e792b7fc03947a05349a4ff669
2004-06-04 18:10:50 -04:00
Ali Saidi
caf5cad959 Merge saidi@zizzer:/z/m5/Bitkeeper/m5/
into zeep.eecs.umich.edu:/z/saidi/work/m5

--HG--
extra : convert_revision : 89e0bdd427b23a8f52b8ba53b18451df7be22f14
2004-06-01 16:03:16 -04:00
Steve Reinhardt
53dde8579b Renamed OpClass enum members: they all end in 'Op' now.
Got rid of two inconsistent sets of strings that corresponded
to this enum, and replaced with a single set that clearly
matches the enum names.

arch/alpha/isa_desc:
arch/isa_parser.py:
cpu/full_cpu/op_class.hh:
    Renamed OpClass enum members.

--HG--
extra : convert_revision : bf596f7568a20b2e77c07ac349f253135141aef4
2004-05-31 16:19:31 -07:00
Ali Saidi
93983de0cf Merged head into linux tree
base/stats/mysql.hh:
    Rename of Statsistics namespace to stats... merge from head

--HG--
extra : convert_revision : a5a7f6268b35e75fba1b1800a74fcd6dbd09d974
2004-05-31 18:58:54 -04:00
Kevin Lim
6964ecd1cf Updated FastCPU model with all the recent changes.
arch/alpha/ev5.cc:
    Updated to support new forms of setIntReg and setFloatRegDouble.  Will need to be cleaned up in the future.
arch/isa_parser.py:
    Added in FastCPU model.

--HG--
extra : convert_revision : 384a27efcb50729ea6c3cc11653f395c300e48db
2004-05-28 14:42:59 -04:00
Kevin Lim
67b5f6afc1 Merged in new FastCPU stuff with existing code.
arch/alpha/ev5.cc:
    Added templatized processInterrupts() function that can be used by all of the CPU models.
arch/alpha/isa_desc:
    Merged in changes to remove CPU dependence.
arch/isa_parser.py:
    Merged in changes.
cpu/static_inst.hh:
    Includes FastCPU execute methods.

--HG--
extra : convert_revision : fcaa1dca35a9b316c73982bec8680df564f50bd8
2004-05-28 11:41:52 -04:00
Kevin Lim
a896960cbf FastCPU model added. It's very similar to the SimpleCPU, just without a lot of the stats tracking.
Also various changes to make the CPU model less ISA dependent, which includes moving the code that checks for interrupts up to the ISA level, moving code that zeroes the zero registers up to the ISA level, and removing opcode and ra from the regfile.

arch/alpha/alpha_memory.cc:
    The regfile has been changed so it no longer has the opcode and ra.  Instead the xc holds the actual instruction, and from there the opcode and ra can be obtained with OPCODE() and RA().
arch/alpha/ev5.cc:
    Moved code that once existed within simpleCPU to ev5, and templatized it.
    This way the CPU models can call processInterrupts and the ISA specific interrupt handling is left to the ISA's code.
    Also moved ISA specific zero registers from simpleCPU to here.
arch/alpha/ev5.hh:
    Added macros for obtaining the opcode and ra from the instruction itself, as there is no longer opcode or ra in the regfile.
arch/alpha/isa_desc:
    Added in declarations for the FastCPU model.
arch/alpha/isa_traits.hh:
    Removed opcode and ra from the regfile.  The xc now holds the actual instruction, and the opcode and ra can be obtained through it.
    Also added the declaration for the templated zeroRegisters() function, which will set the zero registers to 0.
arch/isa_parser.py:
    Added in FastCPUExecContext so it will generate code for the FastCPU model as well.
cpu/exec_context.cc:
    Added in a more generic trap function so "ev5_trap" doesn't need to be called.  It currently still calls the old method, with plans for making this ISA dependent in the future.
cpu/exec_context.hh:
    Exec context now has the instruction within it.  Also added methods for exec context to read an instruction from memory, return the current instruction, and set the instruction if needed.
    Also has declaration for more generic trap() function.
cpu/simple_cpu/simple_cpu.cc:
    Removed references to opcode and ra, and instead sets the xc's instruction with the fetched instruction.
cpu/static_inst.hh:
    Added declaration for execute() using FastCPUExecContext.

--HG--
extra : convert_revision : 0441ea3700ac50b733e485395d4dd4ac83666f92
2004-05-27 17:46:16 -04:00
Nathan Binkert
f622d74f81 add a few statistics events
arch/alpha/ev5.cc:
    Add an event for faults
cpu/simple_cpu/simple_cpu.cc:
    add events for uncached reads/writes

--HG--
extra : convert_revision : 747bdf12761e2de6ebbf54fecc9e0b71915b3a02
2004-05-21 13:58:39 -04:00
Nathan Binkert
62d756f253 rename namespace Statistics to Stats
--HG--
extra : convert_revision : 28f1703f8d7d8cf33fb952ae450f66bdba860fb7
2004-05-21 13:39:20 -04:00
Nathan Binkert
b4405682d9 Change the namespace Statistics to Stats
--HG--
extra : convert_revision : 3084b292bbe2e8a392af8e99a31763ca0b0a9467
2004-05-21 13:03:17 -04:00
Andrew Schultz
f5c7b1358c Remove the uncacheable bit 39 check (needs to be merged in with head tree
if Tru64 is to continue to be supported on Turbolaser) and fixed
translation of physical addresses by clearing PA<42:35> when the real
uncachable bit (43) is set

arch/alpha/ev5.hh:
    Change to support 256 ASNs and seperate VA_SPACE checks for EV5 and EV6
    also add support proper translation of uncacheable physical addresses
dev/ide_ctrl.cc:
    Fix to work with real address translation

--HG--
extra : convert_revision : aa3d1c284b8271d4763a8da2509c91bbcf83189a
2004-05-19 15:58:24 -04:00
Steve Reinhardt
27a6e8258d Add a level of indirection to the register accessors used in
instruction execute methods.  Register i now means the instruction's
i'th src (or dest) operand, not architectural register i.  Current
models that use the architectural reg index can look that up easily
in the instruction object.  Future models that do register renaming
should find this much simpler to deal with.

arch/isa_parser.py:
    Generate register accessors with an extra level of indirection.
cpu/simple_cpu/simple_cpu.hh:
    Modify register accessors to use an extra level of indirection.

--HG--
extra : convert_revision : f4c7d6bfa92fb2ea6251f31ee368809c3643f08f
2004-05-18 22:09:13 -07:00
Steve Reinhardt
4c55d26e66 Replace explicit xc->misspeculating() tests in execute() methods
with an IsNonSpeculative flag.
No effect on results of non-full-system or SimpleCPU.
Very small impact on full-system FullCPU runs since old wrong-path
call_pal insts used to change the PC, where now they're treated
as no-ops.

arch/alpha/isa_desc:
    Get rid of xc->misspeculating() checks, use IsNonSpeculative flag instead.
cpu/static_inst.hh:
    Add IsNonSpeculative flag and isNonSpeculative() method to test it.

--HG--
extra : convert_revision : 7ec536bfc28b905c429c09eb920ed73ef2beeeba
2004-05-18 16:09:02 -07:00
Lisa Hsu
a0ccdf8aba merge m5 with linux for the event and binning lifting
--HG--
extra : convert_revision : 09d3678746c2e9a93a9982dc75d5e1ac309cb2fa
2004-05-18 01:40:03 -04:00
Steve Reinhardt
1d545281b9 Significant changes to ISA description to completely factor
out CPU model.  ISA description now generates multiple
output source files to (in theory) reduce compilation time.

arch/alpha/isa_desc:
    Update for parser changes.  Move most constructors
    out of class declarations (which are now in decoder.hh)
    and into decoder.cc.  Move all execute() methods into
    exec output.
arch/isa_parser.py:
    Significant changes to make ISA description completely
    independent of CPU model, and isolate model-dependent parts
    of parser into one little class (CpuModel).  Also split up code
    output into multiple files (a header, a main source file, and
    per-cpu execute() method files).

    Noticeable changes to language as a result.  See updated Doxygen
    documentation.
cpu/simple_cpu/simple_cpu.hh:
    SimpleCPUExecContext typedef no longer needed.
    Add forward declaration of Process.
cpu/static_inst.hh:
    SimpleCPUExecContext and FullCPUExecContext typedefs no longer needed.
    Make eaCompInst() and memAccInst() return const refs.

--HG--
extra : convert_revision : 71471f267804fafd0a881bac7445677e76334daf
2004-05-17 11:49:46 -07:00
Nathan Binkert
f13926c099 Add VPtr class that makes it possible to esentially create
a pointer to an object that lives inside simulated memory.
Useful for doing a bit of analysis of what's going on in
the running kernel.

--HG--
extra : convert_revision : d78089cce5ec4334483a710ba512eaf18d9b0319
2004-05-13 08:08:42 -04:00
Nathan Binkert
2d8777a79b remove the annotation junk
arch/alpha/isa_desc:
    remove the annotation junk
    Move some code to AlphaPseudo where it belongs
arch/alpha/pseudo_inst.cc:
arch/alpha/pseudo_inst.hh:
    remove the annotation junk
    add pseudo instruction code that was previously misplaced

--HG--
extra : convert_revision : 97db8402aa34e0bdf044b138c52331fc9e714986
2004-05-13 08:03:36 -04:00
Nathan Binkert
8bc3ce93cb pass the address of both the old an new pcbb on context
switches.  (Makes other uncommitted code easier to merge.)

arch/alpha/ev5.cc:
    pass the address of both the old an new pcbb on context
    switches

--HG--
extra : convert_revision : bff8c8d1b532ad5f9af6270169bbfb1b5c05256a
2004-05-13 07:28:54 -04:00
Lisa Hsu
16800971d0 successful merge, linux still builds and runs as far it used to, network device still transmit ARP packet.
arch/alpha/alpha_memory.cc:
    change to the main m5 tree convention for naming
base/traceflags.py:
    add ide and pciconfigall traceflags
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
    kill some old binning styled stuff

--HG--
extra : convert_revision : 0558878906817975a714b1c7c08f9ee405468535
2004-05-11 22:42:45 -04:00
Lisa Hsu
a5f90eba3b first pass at merging m5 with linux
--HG--
extra : convert_revision : dfe23349b80ae3b34d3cb95c5734e01ef62f700e
2004-05-11 01:15:18 -04:00
Steve Reinhardt
7cab07268f Do a better job of factoring out CPU model in ISA description.
(Still not perfect though.)

arch/alpha/isa_desc:
    Do a better job of factoring out CPU model.  (Still not perfect though.)
    Pull execute() methods out of class declarations into separate section
    of file, allowing (1) easier replication for different CPU models and
    (2) a path to putting them all in a separate file.  Force all instruction
    execution context into a single model-dependent class (SimpleCPU itself
    for SimpleCPU, DynInst for FullCPU).
arch/isa_parser.py:
    Do a better job of factoring out CPU model.  (Still not perfect though.)
    Pull execute() methods out of class declarations into separate section
    of file, allowing (1) easier replication for different CPU models and
    (2) a path to putting them all in a separate file.
    Also restructure top level to allow parser to run under interactive
    interpreter session for easier debugging.
cpu/exec_context.hh:
    Add a few new methods to clean up isa_desc.
cpu/simple_cpu/simple_cpu.cc:
cpu/static_inst.hh:
    StaticInst::execute no longer takes a CPU and an ExecContext,
    just a unified FooCPUExecContext.
cpu/simple_cpu/simple_cpu.hh:
    Add methods to redirect calls to ExecContext so SimpleCPU
    can act as sole instruction execution context for itself.
    Typedef SimpleCPU to SimpleCPUExecContext.

--HG--
extra : convert_revision : ecc445503bc585585da5663fe61796580e744da6
2004-05-10 16:10:47 -07:00
Ali Saidi
3c7071a6be Added ULL for 64bit ints
Added function to skip determine_cpu_caches(). We may have to update this in the
future: see note below.

arch/alpha/alpha_memory.cc:
dev/ide_ctrl.cc:
dev/tsunamireg.h:
    Added ULL for 64bit ints
kern/linux/linux_system.cc:
    Added a function to skip determine_cpu_caches, right now it is only used for
    printing in proc, however in the future we may either want to implement the SC_CTL
    IPR register or manually set alpha_l1i_cacheshape, alpha_l1d_cacheshape,
    alpha_l2_cacheshape, alpha_l3_cacheshape to ((size << 10) | (linesize>>1)<<4 | way)
kern/linux/linux_system.hh:
    added event to skip determine_cpu_caches()

--HG--
extra : convert_revision : 1065f2091bbe6832b730af490f5b4672c2afedce
2004-05-09 20:14:18 -04:00
Andrew Schultz
4a5dcc37bf Whole mess'o'changes.. see individual files
arch/alpha/vtophys.cc:
    Removed buggy code that tries to fix PAL addresses (may cause problems
    while trying to debug in PAL code, but that should do this fix outside
    of vtophys)
base/loader/symtab.cc:
base/loader/symtab.hh:
cpu/exetrace.cc:
    Changed InstExec traces to always print a symbol name
dev/ide_ctrl.cc:
dev/ide_disk.cc:
    Tabs
dev/ide_disk.hh:
    Change buffer size
dev/tsunami_pchip.cc:
    Fix translatePciToDma to support scatter gather mapping
kern/linux/linux_system.cc:
    Force simulator to wait until remote debugger attaches (should be removed
    or turned on/off with a flag)

--HG--
extra : convert_revision : 1d08aebe3f448c87a963dd613de3e2e0cff0d48d
2004-05-06 15:21:07 -04:00
Nathan Binkert
25a358983a Major stats package cleanup
Add support for generic visitors for stats and use them
to implement independent output functions.

Support for mysql output and some initial code for hacking
on mysql output with python

arch/alpha/pseudo_inst.cc:
base/hybrid_pred.cc:
base/hybrid_pred.hh:
base/sat_counter.cc:
base/sat_counter.hh:
cpu/simple_cpu/simple_cpu.cc:
kern/tru64/tru64_events.cc:
sim/main.cc:
sim/process.cc:
sim/process.hh:
sim/sim_events.cc:
sim/sim_object.cc:
sim/system.hh:
    update for changes in stats package
base/statistics.cc:
    move the python output code to base/stats/puthon.(cc|hh)
    and reimplement it as a visitor.

    move the text output code to base/stats/text.(cc|hh) and
    reimplement it as a visitor.

    move the database stuff into base/stats/statdb.(cc|hh) and
    get rid of the class.  Put everything as globals in the
    Statistics::Database namespace.

    allocate unique ids for all stats.

    directly implement the check routine and get rid of the
    various dumping routines since they're now in separate files.

    make sure that no two stats have the same name

    clean up some loops
base/statistics.hh:
    major changes to the statistics package again

    lots of code was factored out of statistics.hh into several
    separate files in base/stats/ (this will continue)

    There are now two Stat package types Result and Counter that
    are specified to allow the user to keep the counted type
    separate from the result type.  They are currently both doubles
    but that's an experiment.  There is no more per stat ability to
    set the type.  Statistics::Counter is not the same as Counter!

    Implement a visitor for statistics output so that new output
    types can be implemented independently from the stats package
    itself.

    Add a unique id to each stat so that it can be used to keep
    track of stats more simply.  This number can also be used in
    debugging problems with stats.

    Tweak the bucket size stuff a bit to make it work better.

    fixed VectorDist size bug
cpu/memtest/memtest.cc:
    Fix up for changes in stats package
    Don't use value() since it doesn't work with binning.  If you
    want a number as a stat, and to use it in the program itself,
    you really want two separate variables, one that's a stat,
    and one that's not.
cpu/memtest/memtest.hh:
    Fix up for changes in stats package
test/Makefile:
    Try to build stuff now that directories matter
test/stattest.cc:
    test all new output types
    choose which one with command line options

--HG--
extra : convert_revision : e3a3f5f0828c67c0e2de415d936ad240adaddc89
2004-05-04 17:01:00 -04:00
Steve Reinhardt
d4069233eb Beta version of Python configuration tool. Generates .ini files from
Python script description.

arch/alpha/alpha_memory.cc:
dev/io_device.cc:
    Add DEFINE_SIM_OBJECT_CLASS_NAME for intermediate SimObjects.
test/paramtest.cc:
    Fix stupid spelling.

--HG--
extra : convert_revision : dc020208cb6507c1afb1ed771a7218daba678e09
2004-04-06 10:02:00 -07:00
Steve Reinhardt
65205b82ac More {Itb,Dtb} -> {ITB,DTB} renames (forgot to test build KERNEL).
Also missed renames in a bunch of config files somehow.
(See previous changeset for list of renames.)

arch/alpha/alpha_memory.cc:
arch/alpha/ev5.cc:
arch/alpha/faults.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/simple_cpu/simple_cpu.hh:
    More {Itb,Dtb} -> {ITB,DTB} renames (forgot to test build KERNEL).

--HG--
extra : convert_revision : b2c6ca0916b72b59895520fcacaf028667560a0d
2004-04-03 13:46:10 -08:00
Steve Reinhardt
782fb42992 Basic cleanup pass to get rid of a few things that made the Python
configuration unnecessarily awkward.  Biggest changes are:

- External and internal object names now match in all cases.  The
macros still allow them to be different; the only reason I didn't
get rid of that is that the macros themselves should be going away
soon.  In the few conflicting cases, I sometimes renamed the C++ object
and sometimes renamed the config object.  The latter sets of substitions
are:

s/BaseBus/Bus/;
s/MemoryObject/FunctionalMemory/;
s/MemoryControl/MemoryController/;
s/FUPool/FuncUnitPool/;

- SamplingCPU is temporarily broken... we need to change the model
of how this works in the .ini file.  Having it as a CPU proxy is
really awkward.

arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
cpu/simple_cpu/simple_cpu.cc:
sim/process.cc:
    Rename objects to match config name.
cpu/base_cpu.cc:
    Uncomment SimObject define since SamplingCPU no longer
    does this for us.
dev/ethertap.cc:
    Use unsigned instead of uint16_t for params.
kern/tru64/tru64_system.cc:
    Use unsigned instead of uint64_t for init_param param.
test/paramtest.cc:
    Fix old SimObjectParam.

--HG--
extra : convert_revision : 378ebbc6a71ad0694501d09979a44d111a59e8dc
2004-04-02 22:57:08 -08:00
Nathan Binkert
832a0917cf ULL()
--HG--
extra : convert_revision : 543313ec248457e6cb2f8315881f030545e8cf45
2004-03-24 02:59:43 -05:00
Lisa Hsu
3bc8cffc75 merge with m5 head
--HG--
extra : convert_revision : c90339248d1ee74df1c6b90a77ec9ea41f646311
2004-03-11 18:52:29 -05:00
Erik Hallnor
1d09cd71a4 Reenable functioning copies.
arch/alpha/isa_desc:
    Reenable copies.

--HG--
extra : convert_revision : 99259c0ff65e742e617cba1c14f5d1bf4be2fee8
2004-03-04 20:03:38 -05:00
Erik Hallnor
8ad803058f Automerged
--HG--
extra : convert_revision : 7b56535ee32551f27db8d98172159f63e5099835
2004-03-04 15:06:34 -05:00
Erik Hallnor
7c089b2001 Copy implementations
arch/alpha/isa_desc:
    Need to return fault for copy operations.
cpu/exec_context.hh:
    Add temporary storage to pass source address from copy load to copy store
cpu/simple_cpu/simple_cpu.cc:
    Implement copy functions.
cpu/simple_cpu/simple_cpu.hh:
    Return fault

--HG--
extra : convert_revision : 98e5ce563449d6057ba45c70eece9235f1649a90
2004-03-04 14:57:57 -05:00
Erik Hallnor
cbc42f1d71 Remove copys from isa_desc, and implement a store and forward bus bridge
arch/alpha/isa_desc:
    Just to make sure, remove the new copy instructions until everything works.

--HG--
extra : convert_revision : cdd3d4c8fa415175aaee04f4a99340dcf82dbc3a
2004-02-29 22:41:11 -05:00
Nathan Binkert
27960f6d85 fix rpcc
arch/alpha/ev5.cc:
    actually implement the cycle count register
arch/alpha/isa_desc:
    the rpcc instruction really just reads the cycle count
    register

--HG--
extra : convert_revision : a0edec85672377a62b90950efc17b62b375220b1
2004-02-29 14:54:52 -05:00
Steve Reinhardt
c79deda8cd Fix handling of rpcc in full-system mode.
arch/alpha/ev5.cc:
    Handle writing IPR_CC and IPR_CC_CTL slightly more intelligently.
    (Very slightly).
arch/alpha/isa_desc:
    Upper half of rpcc result comes from value written
    to IPR_CC, not actual cycle counter.

--HG--
extra : convert_revision : 7161989db8a3f040d0558e2e5a1a162ed1cb4125
2004-02-28 17:21:32 -05:00
Erik Hallnor
cfb6f8fd01 Added copy instructions to the ISA. Well it didn't break anything yet...
arch/alpha/isa_desc:
    Add copy_load and copy_store insts (ldf and stf respectively)
cpu/simple_cpu/simple_cpu.hh:
    Add copy functions to SimpleCPU as well

--HG--
extra : convert_revision : 1fa041da582b418c47d4eefc22dabba978a50e2d
2004-02-27 02:40:43 -05:00
Erik Hallnor
c3784e37ce Initial copy support in the pipeline. Add copypal counting.
arch/alpha/osfpal.cc:
    Add a string for copypal.
arch/alpha/osfpal.hh:
    Add a code for copypal.
cpu/static_inst.hh:
    Add an IsCopy flag.

--HG--
extra : convert_revision : 19e3d90368454806029ad492eace19cd0924fe9f
2004-02-27 00:45:21 -05:00
Steve Reinhardt
6f5e104fc5 Make SW prefetch flag a parameter again, and add code to make
it actually do something on FullCPU.  Still disabled, as it
causes detailed-boot to hang when you turn it on.

arch/alpha/isa_desc:
    Add EAComp and MemAcc pseudo-instructions to prefetch StaticInst.
cpu/simple_cpu/simple_cpu.hh:
    Changed prefetch() return type from Fault to void.

--HG--
extra : convert_revision : c7cb42682bfea6af117c87d4dfdb06176b6fe6b7
2004-02-26 07:05:36 -08:00
Andrew Schultz
d4637757f8 Remote an old hack that is now unnecessary
base/cprintf_formats.hh:
    Add additional format modifiers

--HG--
extra : convert_revision : f9ec0a664eeb96db7dacacd6b7636e3cb47555e7
2004-02-19 16:32:13 -05:00
Andrew Schultz
e3fb3d1ad0 Misspeculation fix and (more importantly) change to allow for the ev6 style
physical addressing.  This has the uncacheable bit as bit 40 as opposed
to bit 39.  Additionally, we now support (at least superficially) a 44-bit
physical address.  To deal with superpage access in this scheme, any super
page access with either bit 39 or 40 set is sign extended.

--HG--
extra : convert_revision : 05ddbcb9a6a92481109a63b261743881953620ab
2004-02-19 16:30:06 -05:00
Andrew Schultz
12747d3084 Change the physical memory logic, and also add misspeculation fix to
tlb index calls that are called from ExecContext::readIpr

arch/alpha/ev5.cc:
    Fix misspeculation bugs for misspeculated IPR accesses

--HG--
extra : convert_revision : c9ffcf9ef8123dfcaee1606c05aee8ad60d893d7
2004-02-18 21:38:55 -05:00
Andrew Schultz
59a6e9d705 Merge
arch/alpha/alpha_memory.cc:
    SCCS merged

--HG--
extra : convert_revision : 0348e29c833684fd593a6c02913319f45f24e76e
2004-02-16 22:04:55 -05:00
Andrew Schultz
a73e263f94 Change logic for translating a memory addresses, extra checks for invalid
physical addresses.

--HG--
extra : convert_revision : efb4a5229d88cb3c024e0b24f5916048bd42d589
2004-02-16 21:56:38 -05:00
Andrew Schultz
9984412671 Fix bug with physical address translation
--HG--
extra : convert_revision : 2bfc338decdceaaf57f4a391b93882a8e0715a56
2004-02-15 16:33:16 -05:00
Andrew Schultz
092ec1978d Fix to remote debugger while in PAL
arch/alpha/vtophys.cc:
base/remote_gdb.cc:
    Fix to remote debugger while in PAL code
dev/pcidev.cc:
    Remove extra debug printf

--HG--
extra : convert_revision : e64988846ad05cd3ddf47034d72d99dae3501591
2004-02-13 18:15:04 -05:00
Nathan Binkert
8232c9743d fix up vtophys a bit
arch/alpha/vtophys.cc:
    fix up vtophys to deal with translations if there
    is no ptbr, and to deal with PAL addresses
    add ptomem which is just a wrapper for dma_addr
arch/alpha/vtophys.hh:
    add ptomem which is a wrapper for dma_addr with the
    same usage as vtomem

--HG--
extra : convert_revision : 1ae22073d400e87b708a4a7ef501124227fc6c39
2004-02-13 15:36:21 -05:00
Steve Reinhardt
5e82f8d84c Merge zizzer:/bk/m5 into isabel.reinhardt.house:/z/stever/bk/m5
--HG--
extra : convert_revision : 964126edcf72faf572a9272599264ba2f5cd7aa1
2004-02-10 21:44:08 -08:00
Steve Reinhardt
d38f995aee Fixes for Linux syscall emulation.
arch/alpha/alpha_linux_process.cc:
    Fixes for Linux emulation:
    - stat struct alignment
    - osf_{get,set}sysinfo return values
    - additional syscall numbers
    - initialize $r0 to 0
sim/syscall_emul.cc:
    brk(0) just returns brk value (don't update it!)

--HG--
extra : convert_revision : 78e22458321c81e81540d101c9e65e2e4b0ad117
2004-02-10 21:43:57 -08:00
Nathan Binkert
087334bfe5 Merge zizzer.eecs.umich.edu:/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/.automount/ziff/z/binkertn/research/m5/memory

--HG--
extra : convert_revision : 9f385ee5b6958373a9a1bc600eb3e5e8b7987f38
2004-02-09 10:36:32 -05:00
Nathan Binkert
411d5497fa Add that one IPR memory space address that we keep seeing
--HG--
extra : convert_revision : 81b365ac9ca8b33cae99107e5b1900f7c46f0866
2004-02-09 09:06:20 -05:00
Steve Reinhardt
730296f7f9 Results of automatic (yet incomplete) merge.
--HG--
extra : convert_revision : 3ad9a929051bfe111a1e10618c8595acbbade542
2004-02-09 00:30:16 -08:00
Steve Reinhardt
d7b7363444 Add support for memory barriers.
arch/alpha/isa_desc:
    Add cache port bindings for mb & wmb.

--HG--
extra : convert_revision : 72f76150fe471d0dc97bd41598cad4d86a035e39
2004-02-09 00:22:43 -08:00
David Oehmke
95c248c213 Modify the emulated system calls to support running the SPEC Int
benchmarks for alpha-linux.

arch/alpha/alpha_linux_process.cc:
    Added some more ioctl commands to ignore.
    Set unlink and rename to the new functions.
    Ignore setrlimit, times and rt_sigaction.
    Should eventually provide a function for times.
arch/alpha/alpha_tru64_process.cc:
    Added some more ioctl commands to ignore.
    Set unlink and rename to the new functions.
    Ignore setrlimit.
sim/syscall_emul.cc:
    Added implementations for unlink and rename.
sim/syscall_emul.hh:
    Added unlink and rename functions.
    Added a couple more ioctl requests to ignore.
    Print out the PC of any ioctl commands that fail.

--HG--
extra : convert_revision : 8af21c7fa7d0645d3f9324c9ce70ad33590c3c8e
2004-02-05 12:16:17 -05:00
Steve Reinhardt
b6ff600bca Add support for "serializing" instructions that flush
execution pipeline (Alpha trapb & excb).

Add support for write memory barriers (mostly impacts
store buffer).

Add StaticInst flag to indicate memory barriers, though
this is not modeled in the pipeline yet.

arch/alpha/isa_desc:
    Implement trapb, excb, mb, and wmb as insts with
    no execution effect (empty execute() function) but
    with flags that indicate their side effects.

    Also make sure every instruction that needs to go to
    the execute stage has a real opClass value, since we
    are now using No_OpClass to signal insts that can get
    dropped at dispatch.

    StaticInst::branchTarget() is now a const method.
cpu/static_inst.hh:
    Add flags to indicate serializing insts (trapb, excb) and
    memory and write barriers.

    Also declare some StaticInst methods as const methods.
dev/etherlink.hh:
sim/eventq.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_object.hh:
    Make name() return value const.

--HG--
extra : convert_revision : 39520e71469fa20e0a7446b2e06b494eec17a02c
2004-02-04 21:42:00 -08:00
Steve Reinhardt
3e5070a3f1 Fix bug: forgot branchTarget() method on indirect branches.
arch/alpha/isa_desc:
    Add missing branchTarget() method for indirect branches.
cpu/static_inst.hh:
    Add comment clarifying when branchTarget() can be used
    on indirect branches.

--HG--
extra : convert_revision : 0dcfb36a9792a338cefceb3d1501825abace7ac5
2004-02-03 07:19:05 -08:00
Steve Reinhardt
7b07b0877f Change MemReqPtr parameters to references.
This avoids incrementing and decrementing the MemReq
reference counters on every call and return.

arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
cpu/exec_context.hh:
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
    Change MemReqPtr parameters to references.

--HG--
extra : convert_revision : 3ba18bdd9f996563988402576bfdd3430e1ab1e5
2004-02-02 10:47:21 -08:00
Nathan Binkert
801c46d250 a bunch of warning fixes
arch/alpha/isa_desc:
    don't say warn: Warning:
base/misc.cc:
    avoid printing two newlines in a row
sim/main.cc:
    print out a message just before we enter the event queue

--HG--
extra : convert_revision : 2a824d4b67661903fc739a0fb0759aa91d72382c
2004-01-27 17:56:23 -05:00
Erik Hallnor
003d2d724c Merge ehallnor@zizzer:/bk/m5 into zazzer.eecs.umich.edu:/z/ehallnor/m5
--HG--
extra : convert_revision : 52437e42f15899db46525ad91b2e43c2a96ace36
2004-01-13 02:10:48 -05:00
Erik Hallnor
413bfc68e6 Change to a new centralized way to specify the memory hierarchy parameters (do_data and do_events). If you use the defaults (false and true respectively) you don't have to change your INI files.
arch/alpha/isa_traits.hh:
    Add a constant for the maximum address value called MaxAddr.

--HG--
extra : convert_revision : 1371e8b713cc6ed134093e9c208db35dc9741ac7
2004-01-13 02:10:35 -05:00
Steve Reinhardt
510eef0fa0 Modify handling of serialize:dir parameter to make it more useful.
Move global checkpoint-related functions and vars into Checkpoint class (as statics).

arch/alpha/pseudo_inst.cc:
dev/disk_image.cc:
    Move global checkpoint-related functions and vars
    into Checkpoint class (as statics).
sim/serialize.cc:
    Move global checkpoint-related functions and vars
    into Checkpoint class (as statics).

    Checkpoint constructor now takes checkpoint directory name instead
    of file name.

    Make serialize:dir parameter actually set checkpoint directory name
    instead of directory in which checkpoint directory is created.  If
    the value contains a '%', the curTick value is sprintf'd into the
    format to create the directory name.  The default is backwards compatible
    with the old fixed name ("m5.%012d").
sim/serialize.hh:
    Move global checkpoint-related functions and vars
    into Checkpoint class (as statics).

    Checkpoint constructor now takes checkpoint directory name instead
    of file name.

--HG--
extra : convert_revision : d0aa87b62911f405a4f5811271b9e6351fdd9fe4
2004-01-11 15:24:18 -08:00
Nathan Binkert
255ac8372d Make stuff build on openbsd
arch/alpha/alpha_tru64_process.cc:
    So, I don't know why linux uses an off_t here.
    I'm also not sure why linux defines an off_t to be a long
    Let's just use long here since it works for linux, and that's
    what bsd does
base/inifile.cc:
    correct #include for OpenBSD
dev/disk_image.cc:
    the correct type for this is streampos

--HG--
extra : convert_revision : f3ac3a3b8515d66e07ffb9780d8a9e387297b6a0
2003-12-19 00:02:20 -05:00
Steve Reinhardt
16021aa436 Fix previously committed call_pal fix... the main problem was in the
makefile, such that decoder.cc was not getting rebuilt.
Also add -fno-strict-aliasing to fix all the bizarre problems
I've been having with g++ 3.3.x.

arch/alpha/isa_desc:
    Fix compilation problems.  AlphaISA is a class now, not a namespace.

--HG--
extra : convert_revision : 1583cebc1258c57cbd286c1955d11648150fa1f4
2003-12-16 11:46:52 -08:00
Steve Reinhardt
2cd5e980d2 Fixes for full-system call_pal instruction.
arch/alpha/alpha_memory.cc:
    Rename md_mode_type to mode_type.
arch/alpha/ev5.cc:
    simPalCheck() only gets called on correct path now, so
    there's no need to test misspeculating().
arch/alpha/isa_desc:
    Get privileged call_pall detection right this time (I hope).
    ExecContext::simPalCheck() and Annotate::Callpal() are now
    called only on non-speculative executions... this should fix
    the bogus pal-call stats we've been seeing (since these are
    incremented in simPalCheck()).
    Also check for invalid call_pall function codes.

--HG--
extra : convert_revision : 465d6724884007d3fa066d14cd5e6db0cd3954e1
2003-12-15 21:06:09 -08:00
Steve Reinhardt
777c1ebfab Stats & serialization tweaks & cleanup. Unserializing from
a checkpoint now gives identical results to running from scratch
and doing at switchover at the same cycle!
- CPUs start at cycle 0 again, not cycle 1.
- curTick is now serialized & unserialized.
- Stats get reset in main (before event loop).  Since this is done
after curTick is unserialized, simTicks gets set correctly for
running from a checkpoint.
- Simplify serialization to happen in a single pass.
- s/Serializeable/Serializable/

arch/alpha/isa_traits.hh:
dev/etherlink.hh:
sim/eventq.cc:
sim/eventq.hh:
    s/Serializeable/Serializable/
kern/tru64/tru64_system.cc:
sim/process.cc:
    Make initial CPU activation on cycle 0 again (not 1).
sim/main.cc:
    Reset stats before getting started.
    Make error message on falling out of event loop
    more meaningful.
sim/serialize.cc:
sim/serialize.hh:
    Get rid of now-useless initial pass; serialization is
    done in a single pass now.
    Serialize & unserialize curTick.
    Wrap curTick and mainEventQueue in a "globals" Serializable object.
    s/Serializeable/Serializable/
sim/sim_object.cc:
    Add static function to serialize all SimObjects.
sim/sim_object.hh:
    Add static function to serialize all SimObjects.
    s/Serializeable/Serializable/

--HG--
extra : convert_revision : 9dcc411d0009b54b8eb61c3a509680b81b9f6f68
2003-12-11 00:16:46 -08:00
Steve Reinhardt
4ce6118fda Factor ExecContext::setStatus(), BaseCPU::execCtxStatusChange(),
and SimpleCPU::setStatus() into separate functions.  For example,
setStatus(Active) is now activate().

--HG--
extra : convert_revision : 4392e07caf6c918db0b535f613175109681686fe
2003-12-10 17:47:28 -08:00
Steve Reinhardt
f13509e968 Generate a fault when a privileged PAL call is
executed in non-privileged (non-PAL) mode.

--HG--
extra : convert_revision : c8823a1eec27d801a1ed6110ade07354c4dd2a32
2003-12-09 14:19:35 -08:00
Steve Reinhardt
9984b2bd6c Formatting & doxygen docs for new syscall emulation code.
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_linux_process.hh:
arch/alpha/alpha_tru64_process.cc:
arch/alpha/alpha_tru64_process.hh:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    Formatting & doxygen.

--HG--
extra : convert_revision : 4f07dd37e254120800dd0d5c0eb47acc9c00cb3f
2003-12-01 22:39:27 -08:00
Steve Reinhardt
7976794aad Restructuring of LiveProcess etc. to support multiple emulated OS syscall
interfaces, and specific support for Alpha Linux.  Split syscall emulation
functions into several groups, based on whether they depend on the specific
OS and/or architecture (and all combinations of above), including the use of
template functions to support syscalls with slightly different constants
or interface structs.

arch/alpha/alpha_tru64_process.cc:
    Incorporate full Tru64 object definition here, including structure and constant definitions.
    This way we can wrap all of the functions inside the object, and not worry about namespace
    conflicts because no one outside this file will ever see it.
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/object_file.cc:
base/loader/object_file.hh:
    Add enums to ObjectFile to indicate the object's architecture and operating system.
cpu/exec_context.cc:
    prog.hh is now process.hh
cpu/exec_context.hh:
    prog.hh is now process.hh
    move architecture-specific syscall arg accessors into ExecContext
cpu/simple_cpu/simple_cpu.cc:
    No need to include prog.hh (which has been renamed)
sim/process.cc:
sim/process.hh:
    LiveProcess is now effectively an abstract base class.
    New LiveProcess::create() function takes an object file and dynamically picks the
    appropriate subclass of LiveProcess to handle the syscall interface that file expects
    (currently Tru64 or Linux).

--HG--
rename : arch/alpha/fake_syscall.cc => arch/alpha/alpha_tru64_process.cc
rename : sim/prog.cc => sim/process.cc
rename : sim/prog.hh => sim/process.hh
extra : convert_revision : 4a03ca7d94a34177cb672931f8aae83a6bad179a
2003-12-01 19:34:38 -08:00
Steve Reinhardt
0a7f82da7d Rewrite getdirentries to replace SS-derived version.
--HG--
extra : convert_revision : 72eced315bbb331d3068279e60f1f0a390eb687a
2003-11-12 08:40:32 -08:00
Nathan Binkert
7f7dcf4e1f add a couple of hacks to get thigns going for ISCA
arch/alpha/pseudo_inst.hh:
    Give temporary access of these functions to full cpu junk
    (this is a hack!)

--HG--
extra : convert_revision : 35499d6bf03b1c21dc918ccc09a6d21719262120
2003-11-07 05:06:22 -05:00
Steve Reinhardt
e4b52476bc Automerge
--HG--
extra : convert_revision : 2ca18ecbf04a1de72391073d0a5309fdbbdfefda
2003-11-03 20:35:05 -08:00
Steve Reinhardt
02795babaf Fix bugs in and expand syscall emulation code.
arch/alpha/fake_syscall.cc:
    Fix a couple of bugs:
    - error return codes weren't making it through due to inadvertent cast to unsigned
    - sigreturn broken in not one but two ways
    - make all file descriptors look like plain files (not ttys)
    Added implementations of setuid, getgid, fcntl, and getdirentries from Dave Oehmke

--HG--
extra : convert_revision : 53d3f13e1b05e3bde9e68ada3774ca39fa4c0d4c
2003-11-03 20:31:15 -08:00
Steve Reinhardt
40b9a3878a Minor changes to instruction trace output.
arch/alpha/isa_desc:
    A few disassembly changes to make it easier to compare with old machine.def traces:
    - Make lds prefetches print f31 instead of r31 as dest.
    - Don't print mode suffixes on FP if SS_COMPATIBLE_DISASSEMBLY
cpu/exetrace.cc:
    Left-justify instruction in field, and increase width by 1.

--HG--
extra : convert_revision : 9ffd56728f1bb772aa3ccda5f027b93d4c3a4135
2003-11-03 20:26:51 -08:00
Nathan Binkert
c55e6b495e Make it so the quiesce instruction is conditionally enabled
arch/alpha/isa_desc:
    move the quiesce instruction out of here so I can conditionally
    enable it.
arch/alpha/pseudo_inst.cc:
    conditionally enable quiesce
arch/alpha/pseudo_inst.hh:
    add quiesce

--HG--
extra : convert_revision : e1c474c4bf8761ff58073785d82b2bec9f632885
2003-11-03 16:47:08 -05:00
Nathan Binkert
491fb95919 ok, let's get this right
arch/alpha/pseudo_inst.cc:
    yes is not a real value, use true

--HG--
extra : convert_revision : 30b998ae6f13641d70c9158777a12b00df8742fe
2003-11-02 22:12:20 -05:00
Nathan Binkert
c307c22257 Fix a bug in the pseudo instruction context
arch/alpha/pseudo_inst.cc:
    Don't forget the descriptions

--HG--
extra : convert_revision : f208ea24d5b34283e962916cb4c7dff976406285
2003-11-02 21:58:23 -05:00
Nathan Binkert
136ee73a58 Add the option to ignore some of the pseudo instructions
--HG--
extra : convert_revision : 2010782749ca9c5dd029f71480956b8a1fa96394
2003-11-02 20:52:40 -05:00
Nathan Binkert
d76445f9f3 Move the m5 pseudo instructions into their own file
arch/alpha/isa_desc:
    Move the pseudo instructions out of the isa_desc, into their own
    file and call out to them when they're to be accessed
sim/sim_events.cc:
sim/sim_events.hh:
sim/sim_exit.hh:
    move SimExit to sim_exit.cc

--HG--
extra : convert_revision : 1c393adb1c18bd0fef065057d7f4e9cf60ac4197
2003-11-02 20:43:39 -05:00
Nathan Binkert
667cbb6690 Implement more m5 pseduo opcodes:
resetstats
dumpstats
dumpresetstats
m5checkpoint

Lots of cleanup of serialization and stats dumping/resetting to
work with these new instructions

arch/alpha/isa_desc:
    Implement more m5 pseduo opcodes:
    resetstats
    dumpstats
    dumpresetstats
    m5checkpoint

    All of these functions take two optional parameters, the first is a delay,
    and the second is a period.  The delay tells the simulator to wait the
    specified number of nanoseconds before triggering the event, the period
    tells the simulator to repeat the event with a specified frequency
base/statistics.cc:
base/statistics.hh:
    regReset RegResetCallback
dev/disk_image.cc:
    serializeFilename -> CheckpointFile()
sim/debug.cc:
    Move this debugging statement to sim_stats.cc
sim/eventq.cc:
    Don't AutoDelete an event if it is scheduled since the process()
    function could potentially schedule the event again.
sim/main.cc:
    DumpStatsEvent is now Statistics::SetupEvent(Dump, curTick)
sim/serialize.cc:
    Change the serialize event so that it's possible to cause the
    event to repeat.  Also make the priority such that the event
    happens just before the simulator would exit if both events
    were scheduled for the same cycle.

    get rid of the serializeFilename variable and provide a CheckpointFile()
    function.  This function takes a basename that is set in the
    configuration, and appends the current cycle to the name so that
    multiple checkpoints can be dumped from the same simulation.

    Also, don't exit the simulation when a checkpoint file is dumped.
sim/serialize.hh:
    serializeFilename -> CheckpointFile()
    SetupCheckpoint function to tell the simulator to prepare
    to checkpoint at a certain time with a certain period
sim/sim_events.cc:
    DumpStatsEvent stuff gets move to sim_stats.(cc|hh)
    The context stuff gets moved into the already existing
    stats context in stat_context.cc
sim/sim_events.hh:
    DumpStatsEvent stuff gets move to sim_stats.(cc|hh)
sim/universe.cc:
    Provide some simple functions for converting times into
    ticks.  These use floating point math to get as close as
    possible to the real values.  Multipliers are set up ahead
    of time

--HG--
extra : convert_revision : d06ef26a9237529a1e5060cb1ac2dcc04d4ec252
2003-11-02 18:02:58 -05:00
Nathan Binkert
780b3b4bcd SimExit takes a time now
arch/alpha/isa_desc:
    regen

--HG--
extra : convert_revision : a9da9d2a5fc8a0414491e437747cde48dfb61a20
2003-11-02 13:01:08 -05:00
Nathan Binkert
c7d6745b07 deprecate the m5exit instruction and rename it to m5exit_old
Implement a new m5exit instruction with an optional delay

arch/alpha/isa_desc:
    move m5exit to m5exit old.  The old version of the
    instruction is now deprecated

    Implement the new exit instruction with the optional delay
sim/sim_events.cc:
sim/sim_events.hh:
    Make SimExit take a cycle
sim/universe.cc:
    provide ticksPerMS, ticksPerUS, and ticksPerNS so we don't
    have to do math during the cycle

--HG--
extra : convert_revision : e2ed47a2e5cfcd57c82086c6fcb4a28bf801c214
2003-11-02 02:07:31 -05:00
Steve Reinhardt
5a1eb9049d Support for Serializable non-SimObject things like events.
Can now serialize & unserialize DmaRequestEvents and DmaTransferEvents.
Also support serialize/unserialize of pointers to SimObjects and
other Serializable objects.

arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/isa_traits.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/simple_cpu/simple_cpu.hh:
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
    unserialize() now takes a Checkpoint* instead of an IniFile*.
cpu/simple_cpu/simple_cpu.cc:
    unserialize() now takes a Checkpoint* instead of an IniFile*.
    Put ExecContext in its own section so its _status fields doesn't conflict.
sim/eventq.cc:
sim/eventq.hh:
    unserialize() now takes a Checkpoint* instead of an IniFile*.
    Events get serialized by the event queue only if they're marked
    as AutoSerialize... others are assumed to be serialized by something
    else (e.g. an owning SimObject) or to not matter.
sim/param.cc:
    Shift 'const' in case T is a ptr type.
sim/serialize.cc:
sim/serialize.hh:
    Define Checkpoint object to encapsulate everything you need to know
    about a checkpoint.  Use it to allow lookups of named Serializable
    objects (and SimObjects) during unserialization.
    unserialize() now takes a Checkpoint* instead of an IniFile*.

--HG--
extra : convert_revision : 8e6baab32405f8f548bb67a097b2f713296537a5
2003-10-29 21:45:39 -08:00
Steve Reinhardt
af5277a678 Serialization support for Alpha TLBs, PhysicalMemory, and SimpleCPU.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
    Serialize TLB contents.
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
    Complete serialization of SimpleCPU (including owned events).
sim/eventq.cc:
sim/eventq.hh:
    Basic serialization for events.
    Still need to handle dynamic events (not owned by a SimObject).
sim/serialize.cc:
sim/serialize.hh:
    Export serialization filename so PhysicalMemory can
    derive its filename from that.

--HG--
extra : convert_revision : 4db851c5880f73f576ca092d5e5ad4256048eb51
2003-10-29 13:35:07 -08:00
Steve Reinhardt
8da9fcdd75 Flesh out ExecContext serialize/unserialize (including RegFile).
Add support for serializing enums.

arch/alpha/isa_traits.hh:
    Add serialize/unserialize functions for RegFile
    (defined in new isa_traits.cc).
cpu/exec_context.cc:
    Flesh out serialize/unserialize.
sim/serialize.hh:
    Add {UN}SERIALIZE_ENUM().

--HG--
extra : convert_revision : 9e30c7e7b3b290dc8ea0888ba3636fc93ee89052
2003-10-29 08:50:25 -08:00
Steve Reinhardt
aa12cac9fd Rename SERIALIZE_MEMBER to SERIALIZE_SCALAR.
--HG--
extra : convert_revision : 848cfcf3323d224cdb2ff14df6f6996607a5c27f
2003-10-29 00:46:26 -08:00
Steve Reinhardt
1511370d09 More progress on checkpointing... we can now write out a checkpoint and read it back in,
though most objects don't actually serialize any data.

arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/isa_traits.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/simple_cpu/simple_cpu.hh:
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
    Change unserialize param from IniFile& to const IniFile*.
cpu/simple_cpu/simple_cpu.cc:
    Change unserialize param from IniFile& to const IniFile*.
    Make unserialize call ExecContext::unserialize.
sim/eventq.cc:
    Rename MainEventQueue (no spaces) for easier parsing in checkpoints.
    Disable event serialization for now, so we can focus on the easy stuff.
sim/serialize.cc:
    Change paramIn and arrayParamIn param from IniFile& to const IniFile*.
sim/serialize.hh:
    Change unserialize, paramIn, and arrayParamIn params from IniFile& to const IniFile*.

--HG--
extra : convert_revision : 6e8853ed375eddec0e140c95a01dd51bd225f7b9
2003-10-29 00:41:24 -08:00
Steve Reinhardt
e12e64a071 Merge zizzer:bk/m5 into isabel.reinhardt.house:/z/stever/ser/m5
--HG--
extra : convert_revision : 50aa3791d27a17c4ea2fb4aee1a67011bd2abec1
2003-10-28 12:56:17 -08:00
Steve Reinhardt
b90f810575 Revamp serialization to make it easier.
--HG--
extra : convert_revision : c57a538d7cf606dbdf5fa244f92da46bd830e335
2003-10-28 12:55:12 -08:00
Steve Reinhardt
1820520697 Clean up a few spots where we weren't handling of misspeculation correctly.
arch/alpha/ev5.cc:
    Don't call kernelStats.hwrei() or system->breakpoint() on misspeculated paths.
arch/alpha/isa_desc:
    Don't write reegs.intrflag, do Annotate::Callpal, or call xc->syscall
    on misspeculated paths.

--HG--
extra : convert_revision : e73b96fbe4ac5be85fb20aa218fd05fd56d5b2f3
2003-10-28 09:09:45 -08:00
Nathan Binkert
cec7f73abf emulate callpal halt for non FULL_SYSTEM
in the process make m5_exit more generic

arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
    There's no reason that this needs to be in an arch specific file
arch/alpha/isa_desc:
    m5_exit -> SimExit
    Emulate callpal halt and cause the simulator to exit
    while we're at it, sort #includes
sim/sim_events.cc:
sim/sim_events.hh:
    move the m5_exit function here, renaming it to SimExit.
    Also Allow the caller to pass in the termination message.

--HG--
extra : convert_revision : 54b43b17a412ab387b8672c27ef0b04fce10ee15
2003-10-28 10:05:58 -05:00
Steve Reinhardt
ced22d81a6 Fix some problems with stats reset & floss counters.
arch/alpha/isa_desc:
    Keep m5 pseudo-instructions (like resetstats) from taking effect
    on misspeculated paths.

--HG--
extra : convert_revision : 7f0b0490164bca377ff2b14abc35a6c26bac9e6d
2003-10-26 22:37:14 -08:00
Steve Reinhardt
9508bf0a87 Merge stever@zizzer:/bk/m5 into isabel.reinhardt.house:/z/stever/bk/m5
--HG--
extra : convert_revision : 921d26b6fe29870fa532394b388bc0fe6cac183e
2003-10-24 23:37:28 -07:00
Steve Reinhardt
02d80c96b7 Move some common full-system CPU initialization from the
SimpleCPU & FullCPU constructors to AlphaISA::initCPU().

cpu/simple_cpu/simple_cpu.cc:
    Move some common full-system CPU initialization from the
    SimpleCPU & FullCPU constructors to AlphaISA::initCPU().
    Make 'fault' local to SimpleCPU::tick.
cpu/simple_cpu/simple_cpu.hh:
    Make 'fault' local to SimpleCPU::tick (not an object member).

--HG--
extra : convert_revision : e878dedfff06aac0548aca8b14d66c18b8916895
2003-10-24 23:20:27 -07:00
Andrew Schultz
47399b6c5e Added m5func "resetstats" to allow scriptable reset of statistics inside sim
--HG--
extra : convert_revision : 35a93fe085c2ca7ca1fc8bf887539e0b9c704aaf
2003-10-24 16:28:04 -04:00
Steve Reinhardt
cc9a838f4c Merge stever@zizzer:/bk/m5 into isabel.reinhardt.house:/z/stever/bk/m5
--HG--
extra : convert_revision : b0f93bd35d767fd3a520a9fed70a71d40b0056db
2003-10-23 19:09:18 -07:00
Steve Reinhardt
f5da73b688 Initial support for CPU switching. New SamplingCPU object encompasses a set
of CPUs that get switched round-robin (though currently we're only shooting for
two CPUs and one switch event, and even that doesn't quite work yet).  Registration
of ExecContexts with System/Process object factored out so we can create two CPUs
but only register one of them at a time.  Also worked at making behavior and naming
in System and Process objects more consistent.

arch/alpha/ev5.cc:
    Rename ipr_init to initIPRs and get rid of unused mem arg.
arch/alpha/fake_syscall.cc:
    Process:numCpus is now a function (not a data member).
base/remote_gdb.hh:
    Support for ExecContext switching.
cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/simple_cpu/simple_cpu.hh:
    Support for ExecContext switching.
    Renamed contexts array to execContexts to be consistent with Process.
    CPU ID now auto-assigned by system object.
cpu/simple_cpu/simple_cpu.cc:
    Support for ExecContext switching.
    Renamed contexts array to execContexts to be consistent with Process.
    CPU ID now auto-assigned by system object.
    Cleaned up MP full-system initialization a bit.
dev/alpha_console.cc:
    Renamed xcvec array to execContexts to be consistent with Process.
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
    Support for ExecContext switching.
    CPU ID now auto-assigned by system object.
sim/prog.cc:
sim/prog.hh:
    Support for ExecContext switching.
    Process:numCpus is now a function (not a data member).
sim/system.cc:
sim/system.hh:
    Support for ExecContext switching.
    Renamed xcvec array to execContexts to be consistent with Process.

--HG--
extra : convert_revision : 79649cffad5bf3e83de8df44236941907926d791
2003-10-23 19:07:52 -07:00
Erik Hallnor
320540829d Move to non-architecture specific MemReq
arch/alpha/alpha_memory.hh:
cpu/exec_context.hh:
cpu/pc_event.hh:
    Move to non architecture specific MemReq

--HG--
extra : convert_revision : 2445943b6f1c8af86b90cfa9c2f9b1eb4a6a1aa2
2003-10-23 16:40:08 -04:00
Andrew Schultz
f600cff5c2 Created new M5 instruction to allow an integer parameter (init_param) to be specified in the INI and then read inside the simulator.
arch/alpha/isa_desc:
    Added new M5FUNC instruction to put allow reading of init_param inside simulator
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
sim/system.cc:
sim/system.hh:
    Added support for init_param

--HG--
extra : convert_revision : 8253f0b4239b194d4f04665c9deec1fcdf665c8a
2003-10-21 17:18:17 -04:00
Nathan Binkert
e0b065ff7c Separate the stuff for SimObject from SimObject builder.
This makes testing a bit easier.

arch/alpha/alpha_memory.cc:
cpu/intr_control.cc:
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
dev/alpha_console.cc:
dev/console.cc:
dev/disk_image.cc:
dev/etherbus.cc:
dev/etherdump.cc:
dev/etherlink.cc:
dev/ethertap.cc:
dev/simple_disk.cc:
kern/tru64/tru64_system.cc:
sim/main.cc:
sim/prog.cc:
    Need to include builder.hh
    sort #includes
sim/sim_object.cc:
sim/sim_object.hh:
    Separate the SimObjectBuilder stuff into its own file

--HG--
extra : convert_revision : e8395e0cc6ae1f180f9cd6f100795a1ac44aeed5
2003-10-20 20:17:01 -04:00
Steve Reinhardt
f951b00d89 Get rid of obsolete code, most of it '#if 0'ed anyway.
Mostly vestiges of Dave's long-gone instruction prefetching stuff.

arch/alpha/isa_traits.hh:
    Delete unused extractInstructionPrefetchTarget().
base/inifile.cc:
    Delete '#if 0' code
cpu/base_cpu.hh:
    Delete unused filterThisInstructionPrefetch() function.
cpu/exetrace.hh:
    Delete '#if 0' code (obsolete flags).

--HG--
extra : convert_revision : c8317f56ba0a0e568daa785825ee938584987bed
2003-10-19 17:30:26 -07:00
Steve Reinhardt
83d32482dc Add comment to elaborate on store-conditional result code (and remove
stale reference to machine.def).

arch/alpha/isa_desc:
    Add comment describing store-conditional result code
cpu/exec_context.hh:
    update comments

--HG--
extra : convert_revision : ac59e0ad7a9440cb6656617fdf05495b59c68f55
2003-10-18 21:21:14 -07:00
Steve Reinhardt
8b4f16a727 Minor documentation tweaks.
arch/alpha/aout_machdep.h:
    Comment aout_exechdr fields to make doxygen happy.

--HG--
extra : convert_revision : 23fe88cb7ee511ccd83d2779024daf015133c9ce
2003-10-16 12:41:35 -07:00
Nathan Binkert
638a07d15a Merge
cpu/pc_event.cc:
    SCCS merged

--HG--
extra : convert_revision : f7046f2bf6053be9b00150390fabe3d4f82b0981
2003-10-14 16:53:52 -04:00
Nathan Binkert
4759c203c7 Remove all of the Tru64 specific stuff from the base System object
into its own Tru64System object.  Also remove the System builder
stuff and create a Tru64System builder.  This makes it much
simpler to support more operating systems.

arch/alpha/ev5.cc:
    Each system provides its own mechanism for doing a breakpoint.
base/remote_gdb.hh:
    #include <map>
cpu/pc_event.cc:
cpu/pc_event.hh:
    Separate out System specific PCEvents
cpu/simple_cpu/simple_cpu.cc:
    each system provides its own init script
kern/tru64/dump_mbuf.cc:
kern/tru64/printf.cc:
    Stick this in a namespace

--HG--
extra : convert_revision : 9f74527ed2ff8010431d9aff34357aaecc1fb3f6
2003-10-14 12:19:59 -04:00
Steve Reinhardt
af5cdc1d8c Rename CPU object to FullCPU
arch/alpha/isa_desc:
arch/alpha/isa_traits.hh:
cpu/static_inst.hh:
    CPU -> FullCPU

--HG--
extra : convert_revision : 2bed1ed9372ca9e33f7e391a1aa47bbc02675691
2003-10-13 22:21:19 -07:00
Steve Reinhardt
75e5460579 Rename full_cpu/cpu.cc,hh to full_cpu.cc,hh.
arch/alpha/isa_desc:
    Fix include: cpu.hh renamed to full_cpu.hh
cpu/pc_event.cc:
    Didn't need cpu.hh, just base_cpu.hh.
sim/sim_events.cc:
    Didn't need cpu.hh, just param.hh.

--HG--
extra : convert_revision : 2e3fd36476c639af950ba2113f67e8ea24c22be8
2003-10-13 21:51:34 -07:00
Steve Reinhardt
1348e57ac1 Fix up decoder.cc generation... this got broken at the directory reorg.
arch/isa_parser.py:
    Fix include path (bitfield.hh -> base/bitfield.hh).

--HG--
extra : convert_revision : 2ce02d0a5986694a6a6ebcab1e5e0a306d6e5a49
2003-10-13 21:47:27 -07:00