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9484 commits

Author SHA1 Message Date
James Clarkson
fdcfbda38d m5: Expose m5 pseudo-instructions to C/C++ via a static library
Updated the util/m5/Makefile.arm so that m5op_arm.S is used to create
a static library - libm5.a. Allowing users to insert m5
psuedo-instructions into their applications for fine-grained
checkpointing, switching cpus or dumping statistics. e.g.

#include <m5op.h>

void foo(){
	...
	m5_reset_stats(<delay>,<period>)
	m5_work_begin(<workid>,<threadid>);
	...
	m5_work_end(<workid>,<threadid>);
	m5_dump_stats(<delay>,<period>);
}
2012-10-09 12:58:25 +01:00
Dam Sunwoo
81406018b0 ARM: dump stats and process info on context switches
This patch enables dumping statistics and Linux process information on
context switch boundaries (__switch_to() calls) that are used for
Streamline integration (a graphical statistics viewer from ARM).
2012-11-02 11:32:01 -05:00
Chander Sudanthi
322daba74c base: Fix a few incorrectly handled print format cases
This patch ensures cases like %0.6u, %06f, and %.6u are processed correctly.
The case like %06f is ambiguous and was made to match printf.  Also, this patch
removes the goto statement in cprintf.cc in favor of a function call.
2012-11-02 11:32:00 -05:00
Chander Sudanthi
55787cc0d0 base: split out the VncServer into a VncInput and Server classes
This patch adds a VncInput base class which VncServer inherits from.
Another class can implement the same interface and be used instead
of the VncServer, for example a class that replays Vnc traffic.

--HG--
rename : src/base/vnc/VncServer.py => src/base/vnc/Vnc.py
rename : src/base/vnc/vncserver.cc => src/base/vnc/vncinput.cc
rename : src/base/vnc/vncserver.hh => src/base/vnc/vncinput.hh
2012-11-02 11:32:00 -05:00
Dam Sunwoo
ac161c1d72 ISA: generic Linux thread info support
This patch takes the Linux thread info support scattered across
different ISA implementations (currently in ARM, ALPHA, and MIPS), and
unifies them into a single file.

Adds a few more helper functions to read out TGID, mm, etc.

ISA-specific information (e.g., ALPHA PCBB register) is now moved to
the corresponding isa_traits.hh files.
2012-11-02 11:32:00 -05:00
Ali Saidi
d0678d1c31 sim: Fix as issue where exit events on instr queues are used after freed. 2012-11-02 11:32:00 -05:00
Mrinmoy Ghosh
4440332bdd o3: Fix a couple of issues with the local predictor.
Fix some issues with the local predictor and the way it's indexed.
2012-11-02 11:32:00 -05:00
Andreas Sandberg
7e25052fee Partly revert [4f54b0f229b5] and move draining to m5.changeToTiming
Changeset 4f54b0f229b5 removed the call to doDrain in changeToTiming
based on the assumption that the system does not need draining when
running in atomic mode. This is a false assumption since at least the
System class requires the system to be drained before it allows
switching of memory modes. This patch reverts that part of the
changeset.
2012-11-02 11:32:00 -05:00
Andreas Hansson
3d98119717 mem: Fix typo in port comments
This patch merely fixes a few typos in the port comments.
2012-10-31 09:28:23 -04:00
Andreas Hansson
4e984e0962 stats: Update stats for fixed simple-atomic-mp config
This patch updates the stats for the regressions that were affected by
the typo in the simple-atomic-mp configuration.
2012-10-31 08:39:45 -04:00
Andreas Hansson
ab0bd51315 config: Fix a typo in the simple-atomic-mp configuration
This patch fixes a minor typo that managed to sneak into the
simple-atomic-mp regression configuration.
2012-10-31 08:39:43 -04:00
Andreas Hansson
10b70d5452 stats: Update stats for unified cache configuration
This patch updates the stats to reflect the changes in the L2 MSHRs,
as the latter are now uniform across the regressions.
2012-10-30 09:35:32 -04:00
Andreas Hansson
9cbe1cb653 config: Unify caches used in regressions and adjust L2 MSHRs
This patch unified the L1 and L2 caches used throughout the
regressions instead of declaring different, but very similar,
configurations in the different scripts.

The patch also changes the default L2 configuration to match what it
used to be for the fs and se scripts (until the last patch that
updated the regressions to also make use of the cache config). The
MSHRs and targets per MSHR are now set to a more realistic default of
20 and 12, respectively.

As a result of both the aforementioned changes, many of the regression
stats are changed. A follow-on patch will bump the stats.
2012-10-30 07:44:08 -04:00
Nilay Vaish
30f5bf5f23 regressions: update stats for ruby fs test 2012-10-27 16:05:06 -05:00
Malek Musleh
d2d431f439 ruby: set the is_icache param for caches
This patch sets the is_icache param for the L1 caches used in
the MESI and the MOESI CMP directory protocols.
2012-10-27 16:04:30 -05:00
Jason Power ext:(%2C%20Joel%20Hestness%20%3Chestness%40cs.wisc.edu%3E)
931ec6b7cc Ruby: Use block size in configuring directory bits in address
This patch replaces hard coded values used in Ruby's configuration files
for setting directory bits with values based on the block size in use.
2012-10-27 16:01:09 -05:00
Andreas Hansson
a4d8996fd9 config: Add a check for fastmem only used with Atomic CPU
This patch adds an additional check to ensure that the fastmem option
is only used if the system is using the Atomic CPU.
2012-10-26 06:42:45 -04:00
Andreas Hansson
7cd01cf769 config: Remove unused mem_size in fs.py
This patch removes a segment of dead code that is never used.
2012-10-26 06:42:43 -04:00
Andreas Hansson
651de2d9af config: Fix the cache class naming in regression scripts
This patch unifies the naming of the default L1 and L2 caches in the
regression configs to be in line with what is used in the se and fs
scripts.
2012-10-26 06:42:42 -04:00
Andreas Hansson
b387d8e213 stats: Update the stats to reflect the 1GHz default system clock
This patch updates the stats to reflect the change in the default
system clock from 1 THz to 1GHz. The changes are due to the DMA
devices now injecting requests at a lower pace.
2012-10-25 13:15:59 -04:00
Andreas Hansson
6f6adbf0f6 dev: Make default clock more reasonable for system and devices
This patch changes the default system clock from 1THz to 1GHz. This
clock is used by all modules that do not override the default (parent
clock), and primarily affects the IO subsystem. Every DMA device uses
its clock to schedule the next transfer, and the change will thus
cause this inter-transfer delay to be longer.

The default clock of the bus is removed, as the clock inherited from
the system provides exactly the same value.

A follow-on patch will bump the stats.
2012-10-25 13:14:44 -04:00
Andreas Hansson
8fe556338d stats: Update stats to reflect use of SimpleDRAM
This patch bumps the stats to match the use of SimpleDRAM instead of
SimpleMemory in all inorder and O3 regressions, and also all
full-system regressions. A number of performance-related stats change,
and a whole bunch of stats are added for the memory controller.
2012-10-25 13:14:42 -04:00
Andreas Hansson
66e331c7bb config: Use SimpleDRAM in full-system, and with o3 and inorder
This patch favours using SimpleDRAM with the default timing instead of
SimpleMemory for all regressions that involve the o3 or inorder CPU,
or are full system (in other words, where the actual performance of
the memory is important for the overall performance).

Moving forward, the solution for FSConfig and the users of fs.py and
se.py is probably something similar to what we use to choose the CPU
type. I envision a few pre-set configurations SimpleLPDDR2,
SimpleDDR3, etc that can be choosen by a dram_type option. Feedback on
this part is welcome.

This patch changes plenty stats and adds all the DRAM controller
related stats. A follow-on patch updates the relevant statistics. The
total run-time for the entire regression goes up with ~5% with this
patch due to the added complexity of the SimpleDRAM model. This is a
concious trade-off to ensure that the model is properly tested.
2012-10-25 13:14:38 -04:00
Andreas Hansson
d22796c03c config: Use shared cache config for regressions
This patch uses the common L1, L2 and IOCache configuration for the
regressions that all share the same cache parameters. There are a few
regressions that use a slightly different configuration (memtest,
o3-timing=mp, simple-atomic-mp and simple-timing-mp), and the latter
are not changed in this patch. They will be updated in a future patch.

The common cache configurations are changed to match the ones used in
the regressions, and are slightly changed with respect to what they
were. Hopefully this means we can converge on a common base
configuration, used both in the normal user configurations and
regressions.

As only regressions that shared the same cache configuration are
updated, no regressions are affected.
2012-10-25 04:32:44 -04:00
Andreas Hansson
1fdc4e850e arm: Use table walker clock that is inherited from CPU
This patch simplifies the scheduling of the next walk for the ARM
table walker. Previously it used the CPU clock, but as the table
walker inherits the clock from the CPU, it is cleaner to simply use
its own clock (which is the same).
2012-10-25 04:32:42 -04:00
Andreas Hansson
a4329af937 stats: Update stats for DMA port send
This patch updates the stats after removing the zero-time send used in
the DMA port.
2012-10-23 04:49:48 -04:00
Andreas Hansson
69e82539fd dev: Remove zero-time loop in DMA timing send
This patch removes the zero-time loop used to send items from the DMA
port transmit list. Instead of having a loop, the DMA port now uses an
event to schedule sending of a single packet.

Ultimately this patch serves to ease the transition to a blocking
4-phase handshake.

A follow-on patch will update the regression statistics.
2012-10-23 04:49:33 -04:00
Andreas Hansson
37ded2c2cc stats: Update t1000 stats to match recent changes
This patch brings the t1000 stats up to date.
2012-10-23 04:24:32 -04:00
Nilay Vaish
52d8693677 ruby: functional access updates to network test protocol
I had forgotten to change the network test protocol while making changes to
ruby for supporting functional accesses. This patch updates the protocol so
that it can compile correctly.
2012-10-18 18:35:42 -05:00
Nilay Vaish
de3b3ed140 regressions: update stats for eio tests 2012-10-16 14:47:31 -05:00
Nilay Vaish
b6b5cde132 regressions: update stats due to change to ruby memory system 2012-10-15 19:13:59 -05:00
Nilay Vaish
5ffc165939 ruby: improved support for functional accesses
This patch adds support to different entities in the ruby memory system
for more reliable functional read/write accesses. Only the simple network
has been augmented as of now. Later on Garnet will also support functional
accesses.
The patch adds functional access code to all the different types of messages
that protocols can send around. These messages are functionally accessed
by going through the buffers maintained by the network entities.
The patch also rectifies some of the bugs found in coherence protocols while
testing the patch.

With this patch applied, functional writes always succeed. But functional
reads can still fail.
2012-10-15 17:51:57 -05:00
Nilay Vaish
07ce90f7aa memtest: move check on outstanding requests
The Memtest tester allows for only one request to be outstanding for a
particular physical address. The check has been written separately for
reads and writes. This patch moves the check earlier than its current
position so that it need not be written separately for reads and writes.
2012-10-15 17:27:17 -05:00
Nilay Vaish
61434a9943 ruby: register multiple memory controllers
Currently the Ruby System maintains pointer to only one of the memory
controllers. But there can be multiple controllers in the system. This
patch adds a vector of memory controllers.
2012-10-15 17:27:17 -05:00
Nilay Vaish
c14e6cfc4e ruby: remove AbstractMemOrCache
The only place where this abstract class is in use is the memory controller,
which it self is an abstract class. Does not seem useful at all.
2012-10-15 17:27:16 -05:00
Nilay Vaish
3e607f146f ruby: allow function definition in slicc structs
This patch adds support for function definitions to appear in slicc structs.
This is required for supporting functional accesses for different types of
messages. Subsequent patches will use this to development.
2012-10-15 17:27:16 -05:00
Nilay Vaish
c7b0901b97 ruby banked array: do away with event scheduling
It seems unecessary that the BankedArray class needs to schedule an event
to figure out when the access ends. Instead only the time for the end of access
needs to be tracked.
2012-10-15 17:27:15 -05:00
Nilay Vaish
6a65fafa52 ruby: reset timing after cache warm up
Ruby system was recently converted to a clocked object. Such objects maintain
state related to the time that has passed so far. During the cache warmup, Ruby
system changes its own time and the global time. Later on, the global time is
restored. So Ruby system also needs to reset its own time.
2012-10-15 17:27:15 -05:00
Andreas Hansson
b6bd4f34b4 Mem: Fix incorrect logic in bus blocksize check
This patch fixes the logic in the blocksize check such that the
warning is printed if the size is not 16, 32, 64 or 128.
2012-10-15 12:51:21 -04:00
Andreas Hansson
2a740aa096 Port: Add protocol-agnostic ports in the port hierarchy
This patch adds an additional level of ports in the inheritance
hierarchy, separating out the protocol-specific and protocl-agnostic
parts. All the functionality related to the binding of ports is now
confined to use BaseMaster/BaseSlavePorts, and all the
protocol-specific parts stay in the Master/SlavePort. In the future it
will be possible to add other protocol-specific implementations.

The functions used in the binding of ports, i.e. getMaster/SlavePort
now use the base classes, and the index parameter is updated to use
the PortID typedef with the symbolic InvalidPortID as the default.
2012-10-15 08:12:35 -04:00
Andreas Hansson
9baa35ba80 Mem: Separate the host and guest views of memory backing store
This patch moves all the memory backing store operations from the
independent memory controllers to the global physical memory. The main
reason for this patch is to allow address striping in a future set of
patches, but at this point it already provides some useful
functionality in that it is now possible to change the number of
memory controllers and their address mapping in combination with
checkpointing. Thus, the host and guest view of the memory backing
store are now completely separate.

With this patch, the individual memory controllers are far simpler as
all responsibility for serializing/unserializing is moved to the
physical memory. Currently, the functionality is more or less moved
from AbstractMemory to PhysicalMemory without any major
changes. However, in a future patch the physical memory will also
resolve any ranges that are interleaved and properly assign the
backing store to the memory controllers, and keep the host memory as a
single contigous chunk per address range.

Functionality for future extensions which involve CPU virtualization
also enable the host to get pointers to the backing store.
2012-10-15 08:12:32 -04:00
Andreas Hansson
d7ad8dc608 Checkpoint: Make system serialize call children
This patch changes how the serialization of the system works. The base
class had a non-virtual serialize and unserialize, that was hidden by
a function with the same name for a number of subclasses (most likely
not intentional as the base class should have been virtual). A few of
the derived systems had no specialization at all (e.g. Power and x86
that simply called the System::serialize), but MIPS and Alpha adds
additional symbol table entries to the checkpoint.

Instead of overriding the virtual function, the additional entries are
now printed through a virtual function (un)serializeSymtab. The reason
for not calling System::serialize from the two related systems is that
a follow up patch will require the system to also serialize the
PhysicalMemory, and if this is done in the base class if ends up being
between the general parts and the specialized symbol table.

With this patch, the checkpoint is not modified, as the order of the
segments is unchanged.
2012-10-15 08:12:29 -04:00
Andreas Hansson
0c58106b6e Mem: Use deque instead of list for bus retries
This patch changes the data structure used to keep track of ports that
should be told to retry. As the bus is doing this in an FCFS way,
there is no point having a list. A deque is a better match (and is at
least in theory a better choice from a performance point of view).
2012-10-15 08:12:25 -04:00
Andreas Hansson
93a159875a Fix: Address a few minor issues identified by cppcheck
This patch addresses a number of smaller issues identified by the code
inspection utility cppcheck. There are a number of identified leaks in
the arm/linux/system.cc (although the function only get's called once
so it is not a major problem), a few deletes in dev/x86/i8042.cc that
were not array deletes, and sprintfs where the character array had one
element less than needed. In the IIC tags there was a function
allocating an array of longs which is in fact never used.
2012-10-15 08:12:23 -04:00
Andreas Hansson
d52adc4eb6 Stats: Update stats for cache timings in cycles
This patch updates the stats to reflect the change in how cache
latencies are expressed. In addition, the latencies are now rounded to
multiples of the clock period, thus also affecting other stats.
2012-10-15 08:12:21 -04:00
Andreas Hansson
88554790c3 Mem: Use cycles to express cache-related latencies
This patch changes the cache-related latencies from an absolute time
expressed in Ticks, to a number of cycles that can be scaled with the
clock period of the caches. Ultimately this patch serves to enable
future work that involves dynamic frequency scaling. As an immediate
benefit it also makes it more convenient to specify cache performance
without implicitly assuming a specific CPU core operating frequency.

The stat blocked_cycles that actually counter in ticks is now updated
to count in cycles.

As the timing is now rounded to the clock edges of the cache, there
are some regressions that change. Plenty of them have very minor
changes, whereas some regressions with a short run-time are perturbed
quite significantly. A follow-on patch updates all the statistics for
the regressions.
2012-10-15 08:10:54 -04:00
Andreas Hansson
d17f5084ed Stats: Update memtest stats after setting clock
This patch updates the memtest stats to reflect the addition of a
clock other than the default one.
2012-10-15 08:10:52 -04:00
Andreas Hansson
072a91ee51 Configs: Set the memtest clock to a reasonable value
This patch changes the memtest clock from 1THz (the default) to 2GHz,
similar to the CPUs in the other regressions. This is useful as the
caches will adopt the same clock as the CPU. The bus clock rate is
scaled accordingly, and the L1-L2 bus is kept at the CPU clock while
the memory bus is at half that frequency.

A separate patch updates the affected stats.
2012-10-15 08:09:57 -04:00
Andreas Hansson
54227f9e57 Stats: Update stats for new default L1-to-L2 bus clock and width
This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.
2012-10-15 08:09:54 -04:00
Andreas Hansson
1c321b8847 Regression: Use CPU clock and 32-byte width for L1-L2 bus
This patch changes the CoherentBus between the L1s and L2 to use the
CPU clock and also four times the width compared to the default
bus. The parameters are not intending to fit every single scenario,
but rather serve as a better startingpoint than what we previously
had.

Note that the scripts that do not use the addTwoLevelCacheHiearchy are
not affected by this change.

A separate patch will update the stats.
2012-10-15 08:08:08 -04:00