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Author SHA1 Message Date
Ali Saidi 8c0baf2ce4 Update make release, README, and RELEASE_NOTES for b5 
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extra : convert_revision : a4958e934f599bff24b251507da7c266c89430fc
 2008-02-26 17:28:31 -05:00
Gabe Black 8833b4cd44 Bus: Update the stats for the recent bus fix. 
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extra : convert_revision : dc29f7b5e6fa30a50305193cb0e5aed942f7e407
 2008-02-26 02:20:40 -05:00
Gabe Black ec1a4cbbc7 Bus: Fix the bus timing to be more realistic. 
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extra : convert_revision : acd70dc98ab840e55b114706fbb6afb2a95e54bc
 2008-02-26 02:20:08 -05:00
Vilas Sridharan 2e079ce038 add instruction count fast forwaing and max instruction options 
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extra : convert_revision : 8fe45e512229cdc3e0dcd23e3e5c54516c445d0f
 2008-02-22 17:48:10 -05:00
Stephen Hines ceee3ba96e Added ARM_SE as a build option. 
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extra : convert_revision : 905e3acfa58bd14f8101e29dadc0de71d23a79cc
 2008-02-19 16:42:32 -05:00
Steve Reinhardt 3204f96809 Update stats for new writeback behavior. 
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extra : convert_revision : 3e932b5773f5fb9a119822d5bf497f61e9409c14
 2008-02-16 14:58:37 -05:00
Steve Reinhardt 4597a71cef Make L2+ caches allocate new block for writeback misses 
instead of forwarding down the line.

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extra : convert_revision : b0d6e7862c92ea7a2d21f817d30398735e7bb8ba
 2008-02-16 14:58:03 -05:00
Steve Reinhardt 69ce7f953b Update stats for some unknown minor x86 changes 
(assuming someone just forgot to do this... tsk tsk).

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extra : convert_revision : 303d7bbf5e2c892d5f4498a9de2e2b82496ccd0e
 2008-02-16 13:53:12 -05:00
Ali Saidi 9faec83ac5 CPU: move the PC Events code to a place where the code won't be executed multiple times if an instruction faults. 
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extra : convert_revision : 19c8e46a4eea206517be7ed4131ab9df0fe00e68
 2008-02-14 16:14:35 -05:00
Ali Saidi fc38e9c630 Configs: Change Simulation.py to return a subclass of the CPU models rather than the original class. Without this changes elsewhere in the config script (e.g. the DriveSys frequency can change the TestSys frequency. 
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extra : convert_revision : f972207c616590a60a6e103daa5de469cf124b44
 2008-02-14 16:13:50 -05:00
Ali Saidi a33a3f7c55 Update copyright dates 
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extra : convert_revision : 547e7ddff6b8005a9eaad60970bc51984e84fcd1
 2008-02-11 12:35:28 -05:00
Steve Reinhardt 71835d42df Automated merge with file:/home/stever/hg/m5-orig 
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extra : convert_revision : 86a55cd98a9704f756a70aa0cbd2820cf92c821d
 2008-02-11 08:31:26 -08:00
Steve Reinhardt 2f7421b12b EXTRAS now points to src instead of needing 'src' subdir. 
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extra : convert_revision : 8e7e4516ace8c7852eeea3c479bfd567839a8061
 2008-02-11 08:04:01 -08:00
Steve Reinhardt 476a2ee950 Wait to set BUILD_DIR until *after* env is copied. 
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extra : convert_revision : 03153e7aaa1fb2a435900eab08a98ec1a6ce62db
 2008-02-11 07:47:44 -08:00
Nicolas Zea 4c7eb21119 Bus: Only update port cache when there is an item to update it with. 
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extra : convert_revision : 84848fd48bb9e6693a0518c862364142b1969aa8
 2008-02-10 19:41:03 -05:00
Ali Saidi d167e2bb97 IGbE: Fix a couple of bugs. 
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extra : convert_revision : a1f16bd82b6fbd5b6b5dc0f08b9e69858bea86ca
 2008-02-10 19:32:12 -05:00
Steve Reinhardt 9d7a69c582 Fix #include lines for renamed cache files. 
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extra : convert_revision : b5008115dc5b34958246608757e69a3fa43b85c5
 2008-02-10 14:45:25 -08:00
Steve Reinhardt d56e77c180 Rename cache files for brevity and consistency with rest of tree. 
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rename : src/mem/cache/base_cache.cc => src/mem/cache/base.cc
rename : src/mem/cache/base_cache.hh => src/mem/cache/base.hh
rename : src/mem/cache/cache_blk.cc => src/mem/cache/blk.cc
rename : src/mem/cache/cache_blk.hh => src/mem/cache/blk.hh
rename : src/mem/cache/cache_builder.cc => src/mem/cache/builder.cc
rename : src/mem/cache/miss/mshr.cc => src/mem/cache/mshr.cc
rename : src/mem/cache/miss/mshr.hh => src/mem/cache/mshr.hh
rename : src/mem/cache/miss/mshr_queue.cc => src/mem/cache/mshr_queue.cc
rename : src/mem/cache/miss/mshr_queue.hh => src/mem/cache/mshr_queue.hh
rename : src/mem/cache/prefetch/base_prefetcher.cc => src/mem/cache/prefetch/base.cc
rename : src/mem/cache/prefetch/base_prefetcher.hh => src/mem/cache/prefetch/base.hh
rename : src/mem/cache/prefetch/ghb_prefetcher.cc => src/mem/cache/prefetch/ghb.cc
rename : src/mem/cache/prefetch/ghb_prefetcher.hh => src/mem/cache/prefetch/ghb.hh
rename : src/mem/cache/prefetch/stride_prefetcher.cc => src/mem/cache/prefetch/stride.cc
rename : src/mem/cache/prefetch/stride_prefetcher.hh => src/mem/cache/prefetch/stride.hh
rename : src/mem/cache/prefetch/tagged_prefetcher.cc => src/mem/cache/prefetch/tagged.cc
rename : src/mem/cache/prefetch/tagged_prefetcher.hh => src/mem/cache/prefetch/tagged.hh
rename : src/mem/cache/tags/base_tags.cc => src/mem/cache/tags/base.cc
rename : src/mem/cache/tags/base_tags.hh => src/mem/cache/tags/base.hh
rename : src/mem/cache/tags/Repl.py => src/mem/cache/tags/iic_repl/Repl.py
rename : src/mem/cache/tags/repl/gen.cc => src/mem/cache/tags/iic_repl/gen.cc
rename : src/mem/cache/tags/repl/gen.hh => src/mem/cache/tags/iic_repl/gen.hh
rename : src/mem/cache/tags/repl/repl.hh => src/mem/cache/tags/iic_repl/repl.hh
extra : convert_revision : ff7a35cc155a8d80317563c45cebe405984eac62
 2008-02-10 14:15:42 -08:00
Stephen Hines 6cc1573923 Make the Event::description() a const function 
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extra : convert_revision : c7768d54d3f78685e93920069f5485083ca989c0
 2008-02-06 16:32:40 -05:00
Stephen Hines 0ccf9a2c37 Add base ARM code to M5 
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extra : convert_revision : d811bf87d1a0bfc712942ecd3db1b48fc75257af
 2008-02-05 23:44:13 -05:00
Steve Reinhardt b96631e1a0 Cleaned up os.path imports a bit. 
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extra : convert_revision : ee75bf9abd249ab053e804739cc50972475cd5b6
 2008-02-05 17:43:45 -08:00
Steve Reinhardt d725ff450d Make EXTRAS work for SConsopts too. 
Requires pushing source files down into 'src' subdir relative
to directory listed in EXTRAS.

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extra : convert_revision : ca04adc3e24c60bd3e7b63ca5770b31333d76729
 2008-02-05 17:40:08 -08:00
Gabe Black ca313e2303 X86: Put an SMBios/DMI table in memory. 
This is basically just the header right now, but there's an untested
mechanism in place to fill out the table and make sure everything is
updated correctly.

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extra : convert_revision : c1610c0dfa211b7e0d091a04133695d84f500a1c
 2008-01-23 15:28:54 -05:00
Gabe Black 423bbe6499 X86: Optomize the bit scanning instruction microassembly a little. More can be done. 
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extra : convert_revision : 3cf6e972f0e41e3529a633ecbb31289e1bd17f0f
 2008-01-23 08:18:27 -05:00
Gabe Black 60c2d98fc0 X86: Implement and attach the BSR and BSF instructions. 
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extra : convert_revision : be7e11980092e5d1baff0e05d4ec910305966908
 2008-01-22 00:10:33 -05:00
Gabe Black f809637011 X86: Fill out group17 in the decoder. 
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extra : convert_revision : 66ab9c0fc3086f66e3d6d82d47964ecf406c3a8a
 2008-01-21 16:27:40 -05:00
Gabe Black 657b52fea1 X86: Use the existing boot_osflags instead of duplicating it. 
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extra : convert_revision : e04e438d7d261a61c52b946c23cd126ed648814a
 2008-01-21 04:32:34 -05:00
Ali Saidi 48295aa514 Update long o3 regressions for o3 change in previous changeset 
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extra : convert_revision : 00242105076eb4466cce21038858f2b9d20b2fe2
 2008-01-16 11:11:55 -05:00
Steve Reinhardt a1d5beab95 Update O3 ref outputs: very minor stats change due to previous cset. 
(from Steve on behalf of m5test).

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extra : convert_revision : 696efdaa3dd7680dfc9c797a6a46a5053238c7d2
 2008-01-15 13:13:08 -05:00
Ke Meng 0b6876a0c0 The reason is that the event is supposed to put the instructions ready to execute for next cycle. And the FUCompletion event has a lower priority than CPU tick event. It is called after the iew->tick() for current cycle has already been executed and the issueToExecuteQueue has already advanced this time. And assume the issueToExecuteLatency is 1, to catch up, the increasement should be made at access(-1) instead of access(0). Otherwise I found it could increase the actual op_latency of the instructions to execute by 1 cycle and potentially put the simulated CPU into a permanent idle state. 
Signed-off by: Ali Saidi <saidi@eecs.umich.edu>

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extra : convert_revision : dafc16814383e8e8f8320845edf6ab2bcfed1e1d
 2008-01-14 11:47:32 -05:00
Gabe Black c08b7802a9 X86: Redo the bit test instructions. 
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extra : convert_revision : 433c2a9f3675ed02f3be5ce759a440f2686d2ccd
 2008-01-12 06:41:32 -05:00
Gabe Black b705eba6e5 X86: Fix the wrmsr instruction. 
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extra : convert_revision : 12bc7e71226ebafb8eedadf6a3db82929e15e722
 2008-01-12 06:40:55 -05:00
Gabe Black 0ee67d4210 X86: Make the effective segment base shadow the regular one, not the selector. 
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extra : convert_revision : 498c7c16d664c784b196885b1f35c3c6386c9cfc
 2008-01-12 06:40:10 -05:00
Gabe Black 223e48e6ae X86: Make the IO ports work using extra physical address lines. Add a serial port. 
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extra : convert_revision : a14cb4fc9afedfc0ff58b11a7f8fb5516d462cc6
 2008-01-12 06:39:15 -05:00
Gabe Black 0e394fdfa4 X86: Fix the general IO instructions dataSize. 
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extra : convert_revision : 9774a52cb6a8e7632d1b1dc0706e5791cc18d238
 2008-01-12 06:37:35 -05:00
Geoffrey Blake f9c54d5a4b Temporary fix for ll/sc bug see flyspray task for more info: 
http://www.m5sim.org/flyspray/task/197

Signed-off by: Ali Saidi <saidi@eecs.umich.edu>

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extra : convert_revision : cdeece7e3163de9abf2c6c7435f1bc93570fab81
 2008-01-06 00:19:45 -05:00
Steve Reinhardt d4cca11bdb Very minor memtest regression stats changes from recent coherence bug fixes. 
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extra : convert_revision : 5e7f8ce91ea8f98e6503ac9e10aae68c62f9e510
 2008-01-02 15:35:09 -08:00
Steve Reinhardt 6c5a3ab8b2 Add ReadRespWithInvalidate to handle multi-level coherence situation 
where we defer a response to a read from a far-away cache A, then later
defer a ReadExcl from a cache B on the same bus as us.  We'll assert
MemInhibit in both cases, but in the latter case MemInhibit will keep
the invalidation from reaching cache A.  This special response tells
cache A that it gets the block to satisfy its read, but must immediately
invalidate it.

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extra : convert_revision : f85c8b47bb30232da37ac861b50a6539dc81161b
 2008-01-02 15:22:38 -08:00
Steve Reinhardt bf9b3821bd Mark cache-to-cache MSHRs as downstreamPending when necessary. 
Don't mark upstream MSHR as pending if downstream MSHR is already in service.

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extra : convert_revision : e1c135ff00217291db58ce8a06ccde34c403d37f
 2008-01-02 15:18:33 -08:00
Steve Reinhardt 538da9e24d Don't DPRINTF in the middle of a PrintReq. 
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extra : convert_revision : 6358c014d14a19a34111c39827b05987507544bb
 2008-01-02 14:42:42 -08:00
Steve Reinhardt 87e5fd1755 Bug fix: functional cache port now needs otherPort set. 
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extra : convert_revision : fb007df73a77535a5dba19341f7b0b32e8c99548
 2008-01-02 14:42:24 -08:00
Steve Reinhardt cde5a79eab Additional comments and helper functions for PrintReq. 
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extra : convert_revision : 7eadf9b7db8c0289480f771271b6efe2400006d4
 2008-01-02 13:46:22 -08:00
Steve Reinhardt 3952e41ab1 Add functional PrintReq command for memory-system debugging. 
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extra : convert_revision : 73b753e57c355b7e6873f047ddc8cb371c3136b7
 2008-01-02 12:20:15 -08:00
Steve Reinhardt 659aef3eb8 Fix formatting and comments in cache_impl.hh 
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extra : convert_revision : 26d71cca5420ad03e16bf174e15dabe7f902da41
 2008-01-02 12:15:48 -08:00
Gabe Black 2cb7d4f068 SPARC: Fix a bug where the TLB would match against the wrong entries. 
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extra : convert_revision : 631b3b6a1416121b54bd9717ca1cdccdd5b8a1eb
 2008-01-01 18:20:08 -05:00
Ali Saidi 45ea1549c9 Checkpointing: Fix a bug in the simulation script when restoring without standard switch and change some ifs to work with the default port since every port is now connected to something. 
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extra : convert_revision : 72507cf13e58465291b0dce6322e853bee5a2b89
 2007-12-18 01:52:57 -05:00
Ali Saidi 71909a50de CPU: Update where the simple cpus read their cpu id from the thread context to init() to make sure they read the right value. This fixes a bug with multi-processor full-system configurations. 
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extra : convert_revision : 4f2801967a271b43817d88e147c2f80c4480b2c3
 2007-12-16 03:48:13 -05:00
Steve Reinhardt b7ea470a97 Fix minor bug in util/style.py 
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extra : convert_revision : d37accc884c2967d87dd267debab5afeb8b6ed85
 2007-12-11 10:41:30 -08:00
Gabe Black 948269d8aa X86: Update the parser reference output which has mysteriously changed again? 
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extra : convert_revision : 9b1439096509633d6e9b5bc0c661608f40a63c5f
 2007-12-03 14:33:33 -08:00
Gabe Black 27cc351688 X86: Please excuse my dear Aunt Sally. (precedence bug) 
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extra : convert_revision : 9ad4f31e7a962c3177896bcbfb93e2e54720d117
 2007-12-03 14:32:56 -08:00