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33 commits

Author SHA1 Message Date
Andreas Hansson
607c277291 stats: Update stats to reflect recent changes to floats 
Mostly just splitting out the floats ops and corresponding
reads/writes.
 2016-10-19 06:20:04 -04:00
Curtis Dunham
c87b717dbd stats: update references 2016-10-13 23:21:40 +01:00
Andreas Sandberg
55ed9609f1 stats: Update to match classic memory changes 2016-08-12 14:12:59 +01:00
Curtis Dunham
84f138ba96 stats: update references 2016-07-21 17:19:18 +01:00
Andreas Sandberg
9c8710430e stats: Update stats to reflect ARM changes 2016-06-21 16:42:04 +01:00
Andreas Sandberg
85997e66a0 stats: Add power stats to test references 
Change-Id: Ic827213134b199446822f128b81d4a480e777fee
 2016-06-06 17:16:44 +01:00
Curtis Dunham
62b6ff22ec stats: update for snoop filter tweak 
--HG--
extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
 2016-05-31 11:07:18 +01:00
Andreas Hansson
b006ad26d4 stats: Update stats to reflect cache changes 
Removed unused stats, now counting WriteLineReq, and changed how
uncacheable writes are handled while responses are outstanding.
 2016-04-21 04:48:24 -04:00
Andreas Hansson
d9193d1b20 stats: Match current behaviour 
Small changes to the branch predictor and BTB caused stats changes
throughout.
 2016-04-09 12:13:40 -04:00
Andreas Hansson
7a40e7864a stats: Bump stats to match cache changes 
Update stats to match current behaviour. As a result of the earlier
conflict check we are seeing a few prefetch requests being ignored
before being sent as upward snoops.
 2016-03-17 09:51:21 -04:00
Steve Reinhardt
f5d1dd75e5 stats: overdue updates to long regressions 2016-03-16 13:03:49 -07:00
Andreas Hansson
28289e5995 stats: Update stats to reflect forwarding of InvalidateReq 2016-02-24 04:16:59 -05:00
Andreas Hansson
c6cede244b stats: Update stats to reflect changes to cache and crossbar 2016-02-10 04:08:27 -05:00
Andreas Sandberg
bbcbe028fe stats: Update to reflect changes to PCI handling 2015-12-05 00:11:25 +00:00
Andreas Sandberg
5a249e03a4 stats: Update to reflect changes to RealView platform code 2015-12-04 00:19:05 +00:00
Andreas Hansson
324bc9771d stats: Update stats to match cache changes 2015-11-06 03:26:50 -05:00
Joel Hestness
735c4a8766 stats: Update for UDelayEvent quiesce change 2015-10-10 16:45:41 -05:00
Andreas Hansson
806e1fbf0f stats: Update stats to reflect snoop-filter changes 2015-09-25 07:27:03 -04:00
Nilay Vaish
0d6a6dfd7b stats: updates due to recent changesets including d0934b57735a 2015-09-15 08:14:09 -05:00
Andreas Sandberg
023f6eb0f2 stats: Update ARM stats to include programmable oscillators 2015-08-07 15:39:17 +01:00
Andreas Hansson
d8f732273e stats: Update stats for clean eviction addition 2015-07-30 03:42:27 -04:00
Nilay Vaish
9954eb74df stats: update stale config.ini files, eio and few other stats. 2015-07-04 10:43:47 -05:00
Andreas Hansson
25e1b1c1f5 stats: Update stats for cache, crossbar and DRAM changes 
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.

Needless to say, almost every regression is affected.
 2015-07-03 10:15:03 -04:00
Andreas Hansson
4bc7dfb697 stats: Update MinorCPU regressions after accounting fix 2015-05-26 03:21:39 -04:00
Andreas Hansson
80cd107e51 stats: Update stats to reflect cache changes 2015-05-05 03:22:39 -04:00
Andreas Hansson
d5e03beac2 tests: Update stats for cache block alignment 2015-03-27 04:55:57 -04:00
Steve Reinhardt
1483496803 stats: update Minor stats due to PF bug fix 
A recent changeset of mine (http://repo.gem5.org/gem5/rev/4cfe55719da5)
inadvertently fixed a bug in the Minor CPU model which caused it to treat
software prefetches as regular loads.  Prior to this changeset, Minor
did an ad-hoc generation of memory commands that left out the PF check;
because it now uses the common code that the other CPU models use,
it generates prefetches properly.  These stat changes reflect the fact
that the Minor model now issues SoftPFReqs.
 2015-03-19 08:41:32 -04:00
Andreas Hansson
8909843a76 stats: Update stats to reflect cache and interconnect changes 
This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
 2015-03-02 05:04:20 -05:00
Nilay Vaish
e979e8d75e stats: changes due to recent changesets. 2015-01-04 13:02:12 -06:00
Andreas Hansson
df8df4fd0a stats: Bump stats for decoder, TLB, prefetcher and DRAM changes 
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
 2014-12-23 09:31:20 -05:00
Andreas Hansson
6489598fb4 stats: Bump stats for fixes, mostly TLB and WriteInvalidate 2014-12-02 06:08:25 -05:00
Ali Saidi
2c2c3a4ce9 arm, tests: Forgot the system.terminal files for the new regressions. 2014-10-30 00:04:12 -05:00
Ali Saidi
29cd50e14e arm, tests: Add 64-bit ARM regression tests 2014-10-29 23:50:15 -05:00